To all our customers Regarding the change of names mentioned in the document, such as Mitsubishi Electric and Mitsubishi XX, to Renesas Technology Corp. The semiconductor operations of Hitachi and Mitsubishi Electric were transferred to Renesas Technology Corporation on April 1st 2003. These operations include microcomputer, logic, analog and discrete devices, and memory chips other than DRAMs (flash memory, SRAMs etc.
MITSUBISHI 4-BIT SINGLE-CHIP MICROCOMPUTER 4500 SERIES 4513/4514 Group User’s Manual
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Preface This user’s manual describes the hardware and instructions of Mitsubishi’s 4513/4514 Group CMOS 4-bit microcomputer. After reading this manual, the user should have a through knowledge of the functions and features of the 4513/4514 Group and should be able to fully utilize the product. The manual starts with specifications and ends with application examples. In this manual, the 4514 Group is mainly described. The differences from the 4513 Group are described at the related points.
BEFORE USING THIS USER’S MANUAL This user’s manual consists of the following three chapters. Refer to the chapter appropriate to your conditions, such as hardware design or software development. 1. Organization CHAPTER 1 HARDWARE This chapter describes features of the microcomputer and operation of each peripheral function. CHAPTER 2 APPLICATION This chapter describes usage and application examples of peripheral functions, based mainly on setting examples of related registers.
Table of contents Table of contents CHAPTER 1 HARDWARE DESCRIPTION ................................................................................................................................ 1-3 FEATURES ...................................................................................................................................... 1-3 APPLICATION ................................................................................................................................
Table of contents CHAPTER 2 APPLICATION 2.1 I/O pins .................................................................................................................................... 2-2 2.1.1 I/O ports .......................................................................................................................... 2-2 2.1.2 Related registers ............................................................................................................ 2-4 2.1.3 Port application examples ..........
Table of contents CHAPTER 3 APPENDIX 3.1 Electrical characteristics ..................................................................................................... 3-2 3.1.1 Absolute maximum ratings ............................................................................................ 3-2 3.1.2 Recommended operating conditions ............................................................................ 3-3 3.1.3 Electrical characteristics .........................................................
List of figures List of figures CHAPTER 1 HARDWARE PIN CONFIGURATION (TOP VIEW) 4513 Group ..................................................................... 1-4 PIN CONFIGURATION (TOP VIEW) 4514 Group ..................................................................... 1-5 BLOCK DIAGRAM (4513 Group) ................................................................................................. 1-6 BLOCK DIAGRAM (4514 Group) ............................................................................
List of figures Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. 42 43 44 45 46 47 48 49 50 51 52 Ceramic resonator external circuit ............................................................................... 1-58 External clock input circuit ............................................................................................ 1-58 External 0 interrupt program example ......................................................................... 1-59 External 1 interrupt program example ......
List of figures CHAPTER 3 APPENDIX Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. Fig. vi 3.2.1 A-D conversion characteristics data ........................................................................ 3-14 44 External 0 interrupt program example ......................................................................... 3-21 45 External 1 interrupt program example .........................................................................
List of tables List of tables CHAPTER 1 HARDWARE Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Selection of system clock ................................................................................................ 1-11 1 ROM size and pages .................................................................................................... 1-20 2 RAM size .................................
List of tables Table Table Table Table Table Table Table Table Table Table Table Table 2.5.1 A-D control register Q1 .......................................................................................... 2-50 2.5.2 A-D control register Q2 .......................................................................................... 2-50 2.5.3 Recommended operating conditions (when using A-D converter) ................... 2-53 2.6.1 Voltage comparator control register Q3 ....................................
CHAPTER 1 HARDWARE DESCRIPTION FEATURES APPLICATION PIN CONFIGURATION BLOCK DIAGRAM PERFORMANCE OVERVIEW PIN DESCRIPTION FUNCTION BLOCK OPERATIONS ROM ORDERING METHOD LIST OF PRECAUTIONS SYMBOL LIST OF INSTRUCTION FUNCTION INSTRUCTION CODE TABLE MACHINE INSTRUCTIONS CONTROL REGISTERS BUILT-IN PROM VERSION
HARDWARE 1-2 4513/4514 Group User’s Manual
HARDWARE DESCRIPTION/FEATURES/APPLICATION/PIN CONFIGURATION DESCRIPTION The 4513/4514 Group is a 4-bit single-chip microcomputer designed with CMOS technology. Its CPU is that of the 4500 series using a simple, high-speed instruction set. The computer is equipped with serial I/O, four 8-bit timers (each timer has a reload register), and 10-bit A-D conver ter. The various microcomputers in the 4513/4514 Group include variations of the built-in memory type and package as shown in the table below.
HARDWARE PIN CONFIGURATION PIN CONFIGURATION (TOP VIEW) 4513 Group 1 32 P13 D1 2 31 P12 D2 3 30 P11 D3 4 29 P10 D4 5 28 P03 D5 6 27 P02 D6/CNTR0 7 26 P01 D7/CNTR1 8 25 P00 P20/SCK 9 24 AIN3/CMP1+ 23 AIN2/CMP1- 22 AIN1/CMP0+ 21 AIN0/CMP0- 20 P31/INT1 10 P22/SIN 11 M34513E4SP P21/SOUT M34513Mx-XXXSP D0 RESET 12 CNVSS 13 XOUT 14 19 P30/INT0 XIN 15 18 VDCE VSS 16 17 VDD 25 P03 26 P10 27 P11 28 P12 30 D0 29 P13 31 D1 32 D2 Outline 32P4B
HARDWARE PIN CONFIGURATION PIN CONFIGURATION (TOP VIEW) 4514 Group 42 P12 D0 2 41 P11 D1 3 40 P10 D2 4 39 P03 D3 5 38 P02 D4 6 D6/CNTR0 8 D7/CNTR1 9 P50 10 P51 11 P52 12 P53 13 P20/SCK 14 P21/SOUT 15 P22/SIN 16 M34514E8FP D5 7 M34514Mx-XXXFP P13 1 RESET 17 CNVSS 18 XOUT 37 P01 36 P00 35 P43/AIN7 34 P42/AIN6 33 P41/AIN5 32 P40/AIN4 31 AIN3/CMP1+ 30 AIN2/CMP129 AIN1/CMP0+ 28 AIN0/CMP027 P33 26 P32 25 P31/INT1 24 P30/INT0 19 XIN 20 23 VDCE 22 VDD VSS 21 Outline 42P2R-A 4513/4514 Grou
1-6 Port P0 | [ Port g o P1 1 4 4513/4514 Group User’s Manual Serial I/O (8 bits ✕ 1) A-D converter (10 bits ✕ 4 ch) Watchdog timer (16 bits) Timer 4 (8 bits) Timer 3 (8 bits) Timer 2 (8 bits) Timer 1 (8 bits) Timer Port P2 3 Register A (4 bits) Register B (4 bits) Register D (3 bits) Register E (8 bits) Stack register SK (8 levels) Interrupt stack register SDP (1 level) ALU (4 bits) 4500 Series CPU core Voltage comparator (2 circuits) Internal peripheral functions I/O port 4 Port D 8
Port P0 Port P1 4 Port P2 3 4 Port P4 Port D 8 4513/4514 Group User’s Manual Serial I/O (8 bits ✕ 1) A-D converter (10 bits ✕ 8 ch) Register A (4 bits) Register B (4 bits) Register D (3 bits) Register E (8 bits) Stack register SK (8 levels) Interrupt stack register SDP (1 level) ALU (4 bits) 384 words × 4 bits RAM 6144, 8192 words × 10 bits ROM Memory Watchdog timer (16 bits) XIN—XOUT System clock generating circuit Port P5 4 Voltage drop detection circuit 4500 Series CPU core Volta
HARDWARE PERFORMANCE OVERVIEW PERFORMANCE OVERVIEW Parameter 4513 Group Number of 4514 Group basic instructions Minimum instruction execution time M34513M2 Memory sizes ROM M34513M4/E4 M34513M6 M34513M8/E8 M34514M6 M34514M8/E8 RAM M34513M2 M34513M4/E4 M34513M6 M34513M8/E8 M34514M6 M34514M8/E8 I/O (Input is Input/Output D0 –D7 examined by ports skip decision) P00–P03 I/O P10–P13 I/O P20–P22 Input P30–P33 I/O Timers P40–P43 P50–P53 CNTR0 CNTR1 INT0 INT1 Timer 1 Timer 2 Timer 3 Timer 4 I/O I/O I/O I/O Inpu
HARDWARE PIN DESCRIPTION PIN DESCRIPTION Pin VDD VSS VDCE Name Input/Output Power supply — Ground — Voltage drop detecInput tion circuit enable CNVSS RESET CNVSS Reset input XIN XOUT D0 –D7 System clock input System clock output I/O port D (Input is examined by skip decision.
HARDWARE PIN DESCRIPTION MULTIFUNCTION Pin D6 D7 P20 P21 P22 P30 P31 Multifunction CNTR0 CNTR1 SCK SOUT SIN INT0 INT1 Pin CNTR0 CNTR1 SCK SOUT SIN INT0 INT1 Multifunction D6 D7 P20 P21 P22 P30 P31 Pin AIN0 AIN1 AIN2 AIN3 P40 P41 P42 P43 Multifunction CMP0CMP0+ CMP1CMP1+ AIN4 AIN5 AIN6 AIN7 Pin CMP0CMP0+ CMP1CMP1+ AIN4 AIN5 AIN6 AIN7 Multifunction AIN0 AIN1 AIN2 AIN3 P40 P41 P42 P43 Notes 1: Pins except above have just single function.
HARDWARE PIN DESCRIPTION PORT FUNCTION Port Port D Pin Port P0 D0–D5 D6/CNTR0 D7/CNTR1 P00 –P03 Port P1 Port P2 Port P3 (Note 1) Port P4 (Note 2) Port P5 (Note 2) Input Output I/O (8) Output structure N-channel open-drain I/O unit 1 Control instructions SD, RD SZD CLD OP0A IAP0 Control registers Remark W6 I/O (4) N-channel open-drain 4 PU0, K0 P10 –P13 I/O (4) N-channel open-drain 4 OP1A IAP1 PU0, K0 P20 /SCK P21 /SOUT P22 /SIN P30 /INT0 P31 /INT1 P32 , P33 P40 /AIN4 –P43 /AIN7 P50
HARDWARE PIN DESCRIPTION PORT BLOCK DIAGRAMS K00 Pull-up transistor Key-on wakeup input PU00 IAP0 instruction Register A P00,P01 Ai D OP0A instruction T Q K01 Pull-up transistor Key-on wakeup input PU01 IAP0 instruction Register A P02,P03 Ai D OP0A instruction T Q K02 Pull-up transistor Key-on wakeup input PU02 IAP1 instruction P10,P11 Register A Ai D OP1A instruction T Q K0 3 Pull-up transistor Key-on wakeup input PU03 IAP1 instruction Register A Ai OP1A instruction
HARDWARE PIN DESCRIPTION PORT BLOCK DIAGRAMS (continued) IAP2 instruction Register A Synchronous clock input for serial transfer J11 P20/SCK 0 Synchronous clock output for serial transfer 1 J10 IAP2 instruction Register A J11 P21/SOUT 0 Serial data output 1 Serial data input IAP2 instruction Register A P22/SIN Key-on wakeup input External interrupt circuit IAP3 instruction Register A P30/INT0,P31/INT1 D Ai OP3A instruction T Q IAP3 instruction Register A Ai OP3A instruction P32,P33 D
HARDWARE PIN DESCRIPTION PORT BLOCK DIAGRAMS (continued) Q1 Decoder Analog input Q30 CMP0 AIN0/CMP0- + Q32 Q1 Decoder AIN1/CMP0+ Analog input Q1 Decoder Analog input Q31 CMP1 AIN2/CMP1- + Q33 Q1 Decoder AIN3/CMP1+ Analog input IAP4 instruction P40/AIN4–P43/AIN7 Register A Ai OP4A instruction D T Q Q1 Decoder Analog input This symbol represents a parasitic diode on the port. • • i represents 0, 1, 2, or 3. • The 4513 Group does not have port P4.
HARDWARE PIN DESCRIPTION PORT BLOCK DIAGRAMS (continued) Direction register FR0i Ai D OP5A instruction T P50–P53 Q Register A IAP5 instruction Register Y Decoder Skip decision (SZD instruction) CLD instruction D0–D5 S SD instruction RD instruction R Q Skip decision (SZD instruction) Clock input for timer 2 event count Register Y Decoder CLD instruction S SD instruction R RD instruction Q W60 0 Timer 1 underflow signal divided by 2 or signal of AND operation between timer 1 underflow
HARDWARE PIN DESCRIPTION I12 Falling One-sided edge detection circuit 0 I11 0 P30/INT0 1 EXF0 External 0 interrupt EXF1 External 1 interrupt 1 Both edges detection circuit Rising Wakeup Skip SNZI0 I22 Falling One-sided edge detection circuit 0 I21 0 P31/INT1 1 1 Both edges detection circuit Rising Wakeup Skip SNZI1 This symbol represents a parasitic diode on the port.
HARDWARE FUNCTION BLOCK OPERATIONS FUNCTION BLOCK OPERATIONS CPU (CY) (1) Arithmetic logic unit (ALU) (M(DP)) The arithmetic logic unit ALU performs 4-bit arithmetic such as 4bit data addition, comparison, AND operation, OR operation, and bit manipulation. Addition ALU (A) (2) Register A and carry flag Register A is a 4-bit register used for arithmetic, transfer, exchange, and I/O operation.
HARDWARE FUNCTION BLOCK OPERATIONS (5) Stack registers (SKS) and stack pointer (SP) Stack registers (SKs) are used to temporarily store the contents of program counter (PC) just before branching until returning to the original routine when; • branching to an interrupt service routine (referred to as an interrupt service routine), • performing a subroutine call, or • executing the table reference instruction (TABP p).
HARDWARE FUNCTION BLOCK OPERATIONS (8) Program counter (PC) Program counter Program counter (PC) is used to specify a ROM address (page and address). It determines a sequence in which instructions stored in ROM are read. It is a binary counter that increments the number of instruction bytes each time an instruction is executed.
HARDWARE FUNCTION BLOCK OPERATIONS PROGRAM MEMOY (ROM) The program memory is a mask ROM. 1 word of ROM is composed of 10 bits. ROM is separated every 128 words by the unit of page (addresses 0 to 127). Table 1 shows the ROM size and pages. Figure 10 shows the ROM map of M34514M8/E8.
HARDWARE FUNCTION BLOCK OPERATIONS DATA MEMORY (RAM) Table 2 RAM size 1 word of RAM is composed of 4 bits, but 1-bit manipulation (with the SB j, RB j, and SZB j instructions) is enabled for the entire memory area. A RAM address is specified by a data pointer. The data pointer consists of registers Z, X, and Y. Set a value to the data pointer certainly when executing an instruction to access RAM. Table 2 shows the RAM size. Figure 12 shows the RAM map.
HARDWARE FUNCTION BLOCK OPERATIONS INTERRUPT FUNCTION The interrupt type is a vectored interrupt branching to an individual address (interrupt address) according to each interrupt source. An interrupt occurs when the following 3 conditions are satisfied. • An interrupt activated condition is satisfied (request flag = “1”) • Interrupt enable bit is enabled (“1”) • Interrupt enable flag is enabled (INTE = “1”) Table 3 shows interrupt sources.
HARDWARE FUNCTION BLOCK OPERATIONS (4) Internal state during an interrupt The internal state of the microcomputer during an interrupt is as follows (Figure 14). • Program counter (PC) An interrupt address is set in program counter. The address to be executed when returning to the main routine is automatically stored in the stack register (SK). • Interrupt enable flag (INTE) INTE flag is cleared to “0” so that interrupts are disabled.
HARDWARE FUNCTION BLOCK OPERATIONS (6) Interrupt control registers • Interrupt control register V1 Interrupt enable bits of external 0, external 1, timer 1 and timer 2 are assigned to register V1. Set the contents of this register through register A with the TV1A instruction. The TAV1 instruction can be used to transfer the contents of register V1 to register A. • Interrupt control register V2 Interrupt enable bits of timer 3, timer 4, A-D and serial I/O are assigned to register V2.
HARDWARE FUNCTION BLOCK OPERATIONS (7) Interrupt sequence Interrupts only occur when the respective INTE flag, interrupt enable bits (V10–V1 3 and V20 –V23 ), and interrupt request flag are “1.” The interrupt actually occurs 2 to 3 machine cycles after the cycle in which all three conditions are satisfied. The interrupt oc- curs after 3 machine cycles only when the three interrupt conditions are satisfied on execution of other than one-cycle instructions (Refer to Figure 16).
HARDWARE FUNCTION BLOCK OPERATIONS EXTERNAL INTERRUPTS The 4513/4514 Group has two external interrupts (external 0 and external 1). An external interrupt request occurs when a valid waveform is input to an interrupt input pin (edge detection). The external interrupts can be controlled with the interrupt control registers I1 and I2.
HARDWARE FUNCTION BLOCK OPERATIONS (1) External 0 interrupt request flag (EXF0) (2) External 1 interrupt request flag (EXF1) External 0 interrupt request flag (EXF0) is set to “1” when a valid waveform is input to P30/INT0 pin. The valid waveforms causing the interrupt must be retained at their level for 4 clock cycles or more of the system clock (Refer to Figure 16). The state of EXF0 flag can be examined with the skip instruction (SNZ0).
HARDWARE FUNCTION BLOCK OPERATIONS (3) External interrupt control registers • Interrupt control register I1 Register I1 controls the valid waveform for the external 0 interrupt. Set the contents of this register through register A with the TI1A instruction. The TAI1 instruction can be used to transfer the contents of register I1 to register A. • Interrupt control register I2 Register I2 controls the valid waveform for the external 1 interrupt.
HARDWARE FUNCTION BLOCK OPERATIONS TIMERS The 4513/4514 Group has the programmable timers. • Programmable timer The programmable timer has a reload register and enables the frequency dividing ratio to be set. It is decremented from a setting value n. When it underflows (count to n + 1), a timer interrupt request flag is set to “1,” new data is loaded from the reload register, and count continues (auto-reload function).
HARDWARE FUNCTION BLOCK OPERATIONS The 4513/4514 Group timer consists of the following circuits. • Prescaler : frequency divider • Timer 1 : 8-bit programmable timer • Timer 2 : 8-bit programmable timer • Timer 3 : 8-bit programmable timer • Timer 4 : 8-bit programmable timer (Timers 1 to 4 have the interrupt function, respectively) • 16-bit timer Prescaler and timers 1 to 4 can be controlled with the timer control registers W1 to W6.
HARDWARE FUNCTION BLOCK OPERATIONS Instruction clock Prescaler W13 Divistion circuit (divided by 2) MR3 XIN 1 0 Internal clock generating circuit (divided by 3) I12 0 P30/INT0 1/4 0 1 1/16 1 1 0 Both edges detection circuit Rising ORCLK I11 One-sided edge detection circuit Falling W12 0 (Note 1) SQ 1 I10 W10 1 0 R W11 (Note 3) 0 Timer 1 (8) T1F Timer 1 interrupt T2F Timer 2 interrupt 1 Reload register R1 (8) T1AB (TAB1) (TR1AB) T1AB Register B Register A Timer 1 unde
HARDWARE FUNCTION BLOCK OPERATIONS Table 10 Timer control registers Timer control register W1 at reset : 00002 W13 Prescaler control bit W12 Prescaler dividing ratio selection bit W11 Timer 1 control bit W10 Timer 1 count start synchronous circuit control bit 0 1 0 1 0 1 0 1 Timer control register W2 W23 Timer 2 control bit W22 Not used 0 1 0 1 W21 W20 0 0 0 1 1 0 1 1 Timer 2 count source selection bits W20 Timer control register W3 Timer 3 control bit W32 Timer 3 count start synchronous
HARDWARE FUNCTION BLOCK OPERATIONS (1) Timer control registers (4) Timer 1 (interrupt function) • Timer control register W1 Register W1 controls the count operation of timer 1, the selection of count start synchronous circuit, and the frequency dividing ratio and count operation of prescaler. Set the contents of this register through register A with the TW1A instruction. The TAW1 instruction can be used to transfer the contents of register W1 to register A.
HARDWARE FUNCTION BLOCK OPERATIONS (6) Timer 3 (interrupt function) (9) Timer I/O pin (D 6/CNTR0, D7/CNTR1) Timer 3 is an 8-bit binary down counter with the timer 3 reload register (R3). Data can be set simultaneously in timer 3 and the reload register (R3) with the T3AB instruction. Data can be written to reload register (R3) with the TR3AB instruction.
HARDWARE FUNCTION BLOCK OPERATIONS WATCHDOG TIMER Watchdog timer provides a method to reset the system when a program runs wild. Watchdog timer consists of a 16-bit timer (WDT), watchdog timer enable flag (WEF), and watchdog timer flags (WDF1, WDF2). The timer WDT downcounts the instruction clocks as the count source. The underflow signal is generated when the count value reaches “000016 .” This underflow signal can be used as the timer 2 count source.
HARDWARE FUNCTION BLOCK OPERATIONS SERIAL I/O Table 11 Serial I/O pins The 4513/4514 Group has a built-in clock synchronous serial I/O which can serially transmit or receive 8-bit data. Serial I/O consists of; • serial I/O register SI • serial I/O mode register J1 • serial I/O transmission/reception completion flag (SIOF) • serial I/O counter Registers A and B are used to perform data transfer with internal CPU, and the serial I/O pins are used for external data transfer.
HARDWARE FUNCTION BLOCK OPERATIONS When transmitting (D7–D0 : transfer data) Serial I/O register (SI) When receiving SIN pin SOUT pin SOUT pin SIN pin Serial I/O register (SI) ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 ∗ D7 D6 D5 D4 D3 D2 D1 ∗ ∗ Transfer started D7 D6 D5 D4 D3 D2 ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ ∗ Transfer data to be set D0 ∗ ∗ ∗ ∗ ∗ ∗ ∗ D1 D0 Transfer completed ∗ ∗ ∗ ∗ ∗ ∗ D7 D6 D5 D4 D3 D2 D1 D0 Fig.
HARDWARE FUNCTION BLOCK OPERATIONS (5) How to use serial I/O Figure 24 shows the serial I/O connection example. Serial I/O interrupt is not used in this example. In the actual wiring, pull up the Slave (external clock) Master (clock control) SRDY signal D5 ✕ ✕ (Bit 3) 0 ✕ 1 ✕ 1 D5 SCK SCK SOUT SIN SIN SOUT (Bit 0) (Bit 3) wiring between each pin with a resistor. Figure 25 shows the data transfer timing and Table 13 shows the data transfer sequence.
HARDWARE FUNCTION BLOCK OPERATIONS Master SOUT M7’ SIN S7’ S0 M3 M2 M1 M0 S1 M4 S2 S3 M5 S4 M6 S5 M7 S6 S7 SST instruction SCK Slave SST instruction SRDY signal SOUT SIN S1 S0 S7’ M7’ M0 S2 M1 S3 M2 S4 M3 S5 M4 S6 M5 S7 M6 M7 M0–M7 : the contents of master serial I/O S0–S7 : the contents of slave serial I/O register Rising of SCK : serial input Falling of SCK : serial output Fig.
HARDWARE FUNCTION BLOCK OPERATIONS Table 13 Processing sequence of data transfer from master to slave Master (transmission) [Initial setting] • Setting the serial I/O mode register J1 and interrupt control register V2 shown in Figure 24. TJ1A and TV2A instructions • Setting the port received the reception enable signal (SRDY ) to the input mode. (Port D5 is used in this example) SD instruction * [Transmission enable state] • Storing transmission data to serial I/O register SI.
HARDWARE FUNCTION BLOCK OPERATIONS A-D CONVERTER Table 14 A-D converter characteristics Parameter Characteristics Conversion format Successive comparison method Resolution 10 bits Relative accuracy Linearity error: ±2LSB Non-linearity error: ±0.9LSB Conversion speed 46.5 µs (High-speed mode at 4.0 MHz oscillation frequency) Analog input pin 4 for 4513 Group 8 for 4514 Group The 4513/4514 Group has a built-in A-D conversion circuit that performs conversion by 10-bit successive comparison method.
HARDWARE FUNCTION BLOCK OPERATIONS Table 15 A-D control registers A-D control register Q1 Q13 at reset : 00002 Not used Q12 Q11 Analog input pin selection bits (Note 2) Q10 0 1 Q12Q11 Q10 0 0 0 0 0 1 0 1 0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 A-D control register Q2 Q23 Q22 Q21 Q20 P4 3/A IN7 and P42/A IN6 pin function selection bit (Not used for the 4513 Group) P41/A IN5 pin function selection bit (Not used for the 4513 Group) P40/A IN4 pin function selection bit (Not used for the 4513 Group) 0 1 0 1 0
HARDWARE FUNCTION BLOCK OPERATIONS (7) Operation description A-D conversion is started with the A-D conversion start instruction (ADST). The internal operation during A-D conversion is as follows: ➀ When A-D conversion starts, the register AD is cleared to “000 16.” ➁ Next, the topmost bit of the register AD is set to “1,” and the comparison voltage Vref is compared with the analog input voltage VIN. ➂ When the comparison result is Vref < VIN, the topmost bit of the register AD remains set to “1.
HARDWARE FUNCTION BLOCK OPERATIONS (8) A-D conversion timing chart Figure 27 shows the A-D conversion timing chart. ADST instruction 62 machine cycles A-D conversion completion flag (ADF) DAC operation signal Fig.
HARDWARE FUNCTION BLOCK OPERATIONS (10) Operation at comparator mode (12) Comparison result store flag (ADF) The A-D converter is set to comparator mode by setting bit 3 of the register Q2 to “1.” Below, the operation at comparator mode is described. In comparator mode, the ADF flag, which shows completion of A-D conversion, stores the results of comparing the analog input voltage with the comparison voltage. When the analog input voltage is lower than the comparison voltage, the ADF flag is set to “1.
HARDWARE FUNCTION BLOCK OPERATIONS (15) Notes for the use of A-D conversion 2 (16) Definition of A-D converter accuracy Do not change the operating mode (both A-D conversion mode and comparator mode) of A-D converter with bit 3 of register Q2 while A-D converter is operating.
HARDWARE FUNCTION BLOCK OPERATIONS VOLTAGE COMPARATOR The 4513/4514 Group has 2 voltage comparator circuits that perform comparison of voltage between 2 pins. Table 17 shows the characteristics of this voltage comparison.
HARDWARE FUNCTION BLOCK OPERATIONS Table 18 Voltage comparator control register Q3 Voltage comparator control register Q3 (Note 2) Q33 Voltage comparator (CMP1) control bit Q32 Voltage comparator (CMP0) control bit Q31 CMP1 comparison result store bit Q30 CMP0 comparison result store bit at reset : 00002 0 1 0 1 0 1 0 1 Voltage comparator Voltage comparator Voltage comparator Voltage comparator CMP1- > CMP1+ at RAM back-up : state retained (CMP1) (CMP1) (CMP0) (CMP0) R/W invalid valid invalid v
HARDWARE FUNCTION BLOCK OPERATIONS RESET FUNCTION System reset is performed by applying “L” level to RESET pin for 1 machine cycle or more when the following condition is satisfied; the value of supply voltage is the minimum value or more of the recommended operating conditions. Then when “H” level is applied to RESET pin, software starts from address 0 in page 0. f(XIN) (Note) f(XIN) is counted 16892 to RESET Software starts (address 0 in page 0) 16895 times.
HARDWARE FUNCTION BLOCK OPERATIONS (1) Power-on reset Reset can be performed automatically at power on (power-on reset) by connecting resistors, a diode, and a capacitor to RESET pin. Connect RESET pin and the external circuit at the shortest distance. VDD VD D RESET pin voltage Internal reset signal RESET pin (Note) Reset state Voltage drop detection circuit Watchdog timer output Internal reset signal WEF Reset released Power-on Note: This symbol represents a parasitic diode.
HARDWARE FUNCTION BLOCK OPERATIONS • Program counter (PC) .......................................................................................................... 0 0 0 0 0 0 Address 0 in page 0 is set to program counter. • Interrupt enable flag (INTE) .................................................................................................. 0 • Power down flag (P) .............................................................................................................
HARDWARE FUNCTION BLOCK OPERATIONS VOLTAGE DROP DETECTION CIRCUIT The built-in voltage drop detection circuit is designed to detect a drop in voltage and to reset the microcomputer if the supply voltage drops below a set value. RESET pin Internal reset signal Voltage drop detection circuit Watchdog timer output WEF Note: The output structure of RESET pin is N-channel open-drain. Fig.
HARDWARE FUNCTION BLOCK OPERATIONS RAM BACK-UP MODE Table 20 Functions and states retained at RAM back-up The 4513/4514 Group has the RAM back-up mode. When the EPOF and POF instructions are executed continuously, system enters the RAM back-up state. The POF instruction is equal to the NOP instruction when the EPOF instruction is not executed before the POF instruction.
HARDWARE FUNCTION BLOCK OPERATIONS (4) Return signal An external wakeup signal is used to return from the RAM back-up mode because the oscillation is stopped. Table 21 shows the return condition for each return source. (5) Ports P0 and P1 control registers • Key-on wakeup control register K0 Register K0 controls the ports P0 and P1 key-on wakeup function. Set the contents of this register through register A with the TK0A instruction.
HARDWARE FUNCTION BLOCK OPERATIONS A (Stabilizing time a ) Reset B POF instruction is executed f(XIN) stop f(XIN) oscillation Return input (Stabilizing time a ) (RAM back-up mode) Stabilizing time a : Time required to stabilize the f(XIN) oscillation is automatically generated by hardware. Fig.
HARDWARE FUNCTION BLOCK OPERATIONS Table 22 Key-on wakeup control register, pull-up control register, and interrupt control register Key-on wakeup control register K0 K03 K02 K01 K00 at reset : 00002 Pins P12 and P13 key-on wakeup control bit Pins P10 and P11 key-on wakeup control bit Pins P02 and P03 key-on wakeup 0 1 0 1 0 control bit Pins P00 and P01 key-on wakeup control bit 1 0 1 Pull-up control register PU0 PU0 3 PU0 2 PU0 1 PU0 0 0 1 0 1 0 1 0 1 control bit Pins P00 and P01 pull-up transisto
HARDWARE FUNCTION BLOCK OPERATIONS CLOCK CONTROL • Control circuit to switch the middle-speed mode and high-speed mode • Control circuit to return from the RAM back-up state The clock control circuit consists of the following circuits.
HARDWARE FUNCTION BLOCK OPERATIONS/ROM ORDERING METHOD Clock signal f(X IN) is obtained by externally connecting a ceramic resonator. Connect this external circuit to pins XIN and X OUT at the shortest distance. A feedback resistor is built in between pins XIN and XOUT . When an external clock signal is input, connect the clock source to XIN and leave XOUT open. When using an external clock, the maximum value of external clock oscillating frequency is shown in Table 24.
HARDWARE LIST OF PRECAUTIONS LIST OF PRECAUTIONS ➀Noise and latch-up prevention Connect a capacitor on the following condition to prevent noise and latch-up; • connect a bypass capacitor (approx. 0.1 µ F) between pins VDD and V SS at the shortest distance, • equalize its wiring in width and length, and • use relatively thick wire. In the One Time PROM version, CNVSS pin is also used as VPP pin.
HARDWARE LIST OF PRECAUTIONS ➉ A-D converter-1 When the operating mode of the A-D converter is changed from the comparator mode to the A-D conversion mode with the bit 3 of register Q2 in a program, be careful about the following notes. • Clear the bit 2 of register V2 to “0” to change the operating mode of the A-D converter from the comparator mode to the A-D conversion mode with the bit 3 of register Q2 (refer to Figure 46➄).
HARDWARE LIST OF PRECAUTIONS 16 Voltage comparator function When the voltage comparator function is valid with the voltage comparator control register Q3, it is operating even in the RAM back-up mode. Accordingly, be careful about such state because it causes the increase of the operation current in the RAM backup mode.
HARDWARE SYMBOL SYMBOL The symbols shown below are used in the following instruction function table and instruction list.
HARDWARE LIST OF INSTRUCTION FUNCTION LIST OF INSTRUCTION FUNCTION TBA (B) ← (A) TAY (A) ← (Y) TYA (Y) ← (A) TEAB (E7 –E4 ) ← (B) (E3 –E0 ) ← (A) XAMI j TMA j LA n (A) ← → (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (Y) ← (Y) + 1 (M(DP)) ← (A) (X) ← (X)EXOR(j) j = 0 to 15 (A) ← n n = 0 to 15 TABE TDA (B) ← (E7 –E4 ) (A) ← (E3 –E0 ) TABP p (DR2–DR 0) ← (A2–A0 ) (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH) ← p TAD (A2 –A0 ) ← (DR2 –DR0 ) (A3 ) ← 0 TAZ (A1, A0 ) ← (Z1 , Z0) (PCL) ← (DR2–DR 0, A3–A0)
HARDWARE LIST OF INSTRUCTION FUNCTION LIST OF INSTRUCTION FUNCTION (continued) GroupMnemonic ing Function DI (INTE) ← 0 TAW4 (A) ← (W4) EI (INTE) ← 1 TW4A (W4) ← (A) SNZ0 (EXF0) = 1 ? TAW6 (A) ← (W6) After skipping (EXF0) ← 0 TW6A (W6) ← (A) TAB1 (B) ← (T1 7–T14) (A) ← (T1 3–T10) T1AB (R17 –R14 ) ← (B) (T1 7–T14) ← (B) (R13 –R10 ) ← (A) (T1 3–T10) ← (A) SNZ1 (EXF1) = 1 ? After skipping SNZI0 I1 2 = 1 : (INT0) = “H” ? I1 2 = 0 : (INT0) = “L” ? SNZI1 I2 2 = 1 : (INT1) = “H” ? I2 2 =
HARDWARE LIST OF INSTRUCTION FUNCTION LIST OF INSTRUCTION FUNCTION (continued) TK0A (K0) ← (A) TAK0 (A) ← (K0) TPU0A (PU0) ← (A) TAPU0 (A) ← (PU0) TFR0A* TABSI TSIAB Grouping Mnemonic (A) ← (SI 3–SI0 ) (B) ← (SI 7–SI4 ) (SI3–SI0 ) ← (A) (SI7–SI4 ) ← (B) TAJ1 (A) ← (J1) TJ1A (J1) ← (A) Function TABAD (A) ← (AD 5–AD 2) (B) ← (AD 9–AD 6) However, in the comparator mode, (A) ← (AD 3–AD 0) (B) ← (AD 7–AD 4) TALA (A) ← (AD1 , AD0, 0, 0) TADAB (AD3–AD 0) ← (A) (AD7–AD 4) ← (B) TAQ1 (A) ← (
HARDWARE INSTRUCTION CODE TABLE INSTRUCTION CODE TABLE (for 4513 Group) D9–D4 000000 000001000010 000011 000100 000101 000110 000111 001000 001001001010 001011 001100 001101 001110 001111 010000 011000 010111 011111 Hex.
HARDWARE INSTRUCTION CODE TABLE INSTRUCTION CODE TABLE (continued) (for 4513 Group) D9–D4 100000 100001 100010 100011 100100 100101 100110 100111 101000 101001101010 101011 101100 101101 101110 101111 110000 111111 Hex.
HARDWARE INSTRUCTION CODE TABLE INSTRUCTION CODE TABLE (for 4514 Group) D9 –D4 000000 000001 000010 000011 000100 000101 000110 000111 001000 001001001010 001011 001100 001101 001110 001111 010000 011000 010111 011111 Hex.
HARDWARE INSTRUCTION CODE TABLE INSTRUCTION CODE TABLE (continued) (for 4514 Group) D9–D4 100000 100001100010 100011 100100 100101 100110 100111 101000 101001101010 101011 101100 101101 101110 101111 Hex.
HARDWARE MACHINE INSTRUCTIONS MACHINE INSTRUCTIONS Number of words Number of cycles Instruction code TAB 0 0 0 0 0 1 1 1 1 0 0 1 E 1 1 (A) ← (B) TBA 0 0 0 0 0 0 1 1 1 0 0 0 E 1 1 (B) ← (A) TAY 0 0 0 0 0 1 1 1 1 1 0 1 F 1 1 (A) ← (Y) TYA 0 0 0 0 0 0 1 1 0 0 0 0 C 1 1 (Y) ← (A) TEAB 0 0 0 0 0 1 1 0 1 0 0 1 A 1 1 (E 7–E4) ← (B) (E 3–E0) ← (A) TABE 0 0 0 0 1 0 1 0 1 0 0 2 A 1 1 (B) ← (E7–E4) (A) ← (E3–E0) TDA 0 0 0
HARDWARE Skip condition Carry flag CY MACHINE INSTRUCTIONS – – Transfers the contents of register B to register A. – – Transfers the contents of register A to register B. – – Transfers the contents of register Y to register A. – – Transfers the contents of register A to register Y. – – Transfers the contents of registers A and B to register E. – – Transfers the contents of register E to registers A and B. – – Transfers the contents of register A to register D.
HARDWARE MACHINE INSTRUCTIONS MACHINE INSTRUCTIONS (continued) Arithmetic operation Bit operation Comparison operation D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 1 n n n n notation Number of cycles Mnemonic Type of instructions Number of words Instruction code Parameter 0 7 n 1 1 (A) ← n n = 0 to 15 Hexadecimal Function LA n 0 0 0 1 1 TABP p 0 0 1 0 p5 p 4 p 3 p 2 p 1 p 0 0 8 p +p 1 3 (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH) ← p (PCL) ← (DR2–DR 0, A3–A0) (B) ← (ROM(PC))7–4 (A) ← (ROM(PC))
HARDWARE Skip condition Carry flag CY MACHINE INSTRUCTIONS Datailed description Continuous description – Loads the value n in the immediate field to register A. When the LA instructions are continuously coded and executed, only the first LA instruction is executed and other LA instructions coded continuously are skipped. – – Transfers bits 7 to 4 to register B and bits 3 to 0 to register A.
HARDWARE MACHINE INSTRUCTIONS MACHINE INSTRUCTIONS (continued) Number of words Number of cycles Instruction code Ba 0 1 1 a6 a5 a4 a 3 a2 a1 a0 1 8 a +a 1 1 (PCL) ← a6–a0 BL p, a 0 0 1 1 p4 p 3 p 2 p 1 p 0 0 E p +p 2 2 (PCH) ← p (PCL) ← a6–a0 (Note) 1 0 p5 a6 a5 a4 a 3 a2 a1 a0 2 p a +a 0 0 0 0 1 0 0 1 0 2 2 1 0 p5 p4 0 0 p 3 p2 p1 p0 2 p p (PCH) ← p (PCL) ← (DR2–DR 0, A3–A0) (Note) BM a 0 1 0 a6 a5 a4 a 3 a2 a1 a0 1 a a 1 1 (SP) ← (SP) + 1 (SK(SP)) ← (PC)
HARDWARE Skip condition Carry flag CY MACHINE INSTRUCTIONS – – Branch within a page : Branches to address a in the identical page. – – Branch out of a page : Branches to address a in page p. – – Branch out of a page : Branches to address (DR2 DR 1 DR0 A3 A2 A1 A0) 2 specified by registers D and A in page p. – – Call the subroutine in page 2 : Calls the subroutine at address a in page 2. – – Call the subroutine : Calls the subroutine at address a in page p.
HARDWARE MACHINE INSTRUCTIONS MACHINE INSTRUCTIONS (continued) D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 SNZI0 0 0 0 0 1 1 1 0 1 0 notation Number of cycles Mnemonic Type of instructions Number of words Instruction code Parameter 0 3 A 1 1 Hexadecimal Function I12 = 1 : (INT0) = “H” ? I12 = 0 : (INT0) = “L” ? SNZI1 0 0 0 0 1 1 1 0 1 1 0 3 B 1 1 I22 = 1 : (INT1) = “H” ? Timer operation Interrupt operation I22 = 0 : (INT1) = “L” ? 1-76 TAV1 0 0 0 1 0 1 0 1 0 0 0 5 4
HARDWARE Skip condition Carry flag CY MACHINE INSTRUCTIONS Datailed description (INT0) = “H” However, I12 = 1 – When bit 2 (I12) of register I1 is “1” : Skips the next instruction when the level of INT0 pin is “H.” (INT0) = “L” However, I12 = 0 – When bit 2 (I12) of register I1 is “0” : Skips the next instruction when the level of INT0 pin is “L.” (INT1) = “H” However, I22 = 1 – When bit 2 (I22) of register I2 is “1” : Skips the next instruction when the level of INT1 pin is “H.
HARDWARE MACHINE INSTRUCTIONS MACHINE INSTRUCTIONS (continued) Number of words Number of cycles Instruction code TAB1 1 0 0 1 1 1 0 0 0 0 2 7 0 1 1 (B) ← (T17–T14 ) (A) ← (T13–T10 ) T1AB 1 0 0 0 1 1 0 0 0 0 2 3 0 1 1 (R17–R14) ← (B) (T17–T14 ) ← (B) (R13–R10) ← (A) (T13–T10 ) ← (A) TAB2 1 0 0 1 1 1 0 0 0 1 2 7 1 1 1 (B) ← (T27–T24 ) (A) ← (T23–T20 ) T2AB 1 0 0 0 1 1 0 0 0 1 2 3 1 1 1 (R27–R24) ← (B) (T27–T24 ) ← (B) (R23–R20) ← (A) (T23–T20 ) ←
HARDWARE Skip condition Carry flag CY MACHINE INSTRUCTIONS – – Transfers the contents of timer 1 to registers A and B. – – Transfers the contents of registers A and B to timer 1 and timer 1 reload register. – – Transfers the contents of timer 2 to registers A and B. – – Transfers the contents of registers A and B to timer 2 and timer 2 reload register. – – Transfers the contents of timer 3 to registers A and B.
HARDWARE MACHINE INSTRUCTIONS MACHINE INSTRUCTIONS (continued) Number of words Number of cycles Instruction code IAP0 1 0 0 1 1 0 0 0 0 0 2 6 0 1 1 (A) ← (P0) OP0A 1 0 0 0 1 0 0 0 0 0 2 2 0 1 1 (P0) ← (A) IAP1 1 0 0 1 1 0 0 0 0 1 2 6 1 1 1 (A) ← (P1) OP1A 1 0 0 0 1 0 0 0 0 1 2 2 1 1 1 (P1) ← (A) IAP2 1 0 0 1 1 0 0 0 1 0 2 6 2 1 1 (A2–A0) ← (P22–P20) (A3) ← 0 IAP3 1 0 0 1 1 0 0 0 1 1 2 6 3 1 1 (A) ← (P3) OP3A 1 0
HARDWARE Skip condition Carry flag CY MACHINE INSTRUCTIONS – – Transfers the input of port P0 to register A. – – Outputs the contents of register A to port P0. – – Transfers the input of port P1 to register A. – – Outputs the contents of register A to port P1. – – Transfers the input of port P2 to register A. – – Transfers the input of port P3 to register A. – – Outputs the contents of register A to port P3. – – Transfers the input of port P4 to register A.
HARDWARE MACHINE INSTRUCTIONS MACHINE INSTRUCTIONS (continued) Number of words Number of cycles Instruction code TABSI 1 0 0 1 1 1 1 0 0 0 2 7 8 1 1 (A) ← (SI 3–SI0 ) (B) ← (SI 7–SI4 ) TSIAB 1 0 0 0 1 1 1 0 0 0 2 3 8 1 1 (SI3–SI0 ) ← (A) (SI7–SI4 ) ← (B) TAJ1 1 0 0 1 0 0 0 0 1 0 2 4 2 1 1 (A) ← (J1) TJ1A 1 0 0 0 0 0 0 0 1 0 2 0 2 1 1 (J1) ← (A) SST 1 0 1 0 0 1 1 1 1 0 2 9 E 1 1 (SIOF) ← 0 Serial I/O starting SNZSI 1 0 1 0 0
HARDWARE Skip condition Carry flag CY MACHINE INSTRUCTIONS – – Transfers the contents of serial I/O register SI to registers A and B. – – Transfers the contents of registers A and B to serial I/O register SI. – – Transfers the contents of serial I/O mode register J1 to register A. – – Transfers the contents of register A to serial I/O mode register J1. – – Clears (0) to SIOF flag and starts serial I/O. (SIOF) = 1 – Skips the next instruction when the contents of SIOF flag is “1.
HARDWARE CONTROL REGISTERS CONTROL REGISTERS Interrupt control register V1 V13 Timer 2 interrupt enable bit V12 Timer 1 interrupt enable bit V11 External 1 interrupt enable bit V10 External 0 interrupt enable bit at reset : 00002 0 1 0 1 0 1 0 1 Interrupt control register V2 V23 Serial I/O interrupt enable bit V22 A-D interrupt enable bit V21 Timer 4 interrupt enable bit V20 Timer 3 interrupt enable bit Interrupt control register I1 I13 Not used I12 Interrupt valid waveform for INT0 pin
HARDWARE CONTROL REGISTERS Timer control register W1 W1 3 Prescaler control bit W1 2 Prescaler dividing ratio selection bit W11 Timer 1 control bit W1 0 Timer 1 count start synchronous circuit control bit Timer 2 control bit W2 2 Not used at reset : 00002 0 1 0 1 W21 W20 0 0 0 1 1 0 1 1 W2 1 Timer 2 count source selection bits W2 0 Timer control register W3 Timer 3 control bit W3 2 Timer 3 count start synchronous circuit control bit W3 1 Timer 3 count source selection bits W3 0 Timer 4 con
HARDWARE CONTROL REGISTERS Serial I/O mode register J1 at reset : 00002 J13 Not used J12 Serial I/O internal clock dividing ratio selection bit J11 Serial I/O port selection bit J10 Serial I/O synchronous clock selection bit 0 1 0 1 0 1 0 1 A-D control register Q1 Q13 Q12 Q11 Analog input pin selection bits (Note 2) Q10 Q23 Q22 Q21 Q20 P43 /A IN7 and P42/A IN6 pin function selection bit (Not used for the 4513 Group) P41/A IN5 pin function selection bit (Not used for the 4513 Group) P40/A I
HARDWARE CONTROL REGISTERS Key-on wakeup control register K0 K03 K02 K01 K00 Pins P12 and P13 key-on wakeup control bit Pins P10 and P1 1 key-on wakeup control bit Pins P02 and P03 key-on wakeup control bit Pins P00 and P01 key-on wakeup control bit at reset : 00002 0 1 0 1 0 1 0 1 Pull-up control register PU0 PU0 3 PU0 2 PU0 1 PU0 0 Pins P1 2 and P13 pull-up transistor control bit Pins P10 and P11 pull-up transistor control bit Pins P0 2 and P03 pull-up transistor control bit Pins P0 0 and P01 pull-up
HARDWARE BUILT-IN PROM VERSION BUILT-IN PROM VERSION In addition to the mask ROM versions, the 4513/4514 Group has programmable ROM version software compatible with mask ROM. The built-in PROM of One Time PROM version can be written to and not be erased. The built-in PROM versions have functions similar to those of the mask ROM versions, but they have PROM mode that enables writing to built-in PROM. Table 25 shows the product of built-in PROM version.
HARDWARE BUILT-IN PROM VERSIONS (1) PROM mode Table 26 Programming adapters The built-in PROM version has a PROM mode in addition to a normal operation mode. The PROM mode is used to write to and read from the built-in PROM. In the PROM mode, the programming adapter can be used with a general-purpose PROM programmer to write to or read from the built-in PROM as if it were M5M27C256K. Programming adapters are listed in Table 26.
HARDWARE BUILT-IN PROM VERSION 1-90 4513/4514 Group User’s Manual
CHAPTER 2 APPLICATION 2.1 I/O pins 2.2 Interrupts 2.3 Timers 2.4 Serial I/O 2.5 A-D converter 2.6 Voltage comparator 2.7 Reset 2.8 Voltage drop detection circuit 2.9 RAM back-up 2.
APPLICATION 2.1 I/O pins 2.1 I/O pins The 4513/4514 Group has the twenty-eight I/O pins (eighteen I/O pins for 4513 Group), three input pins. (Ports P2 0–P2 2 , P3 0, P3 1 , D 6 and D 7 are also used as serial I/O pins S CK, S OUT , S IN, and INT0, INT1, CNTR0 and CNTR1 pins, respectively). This section describes each port I/O function, related registers, application example using each port function and notes. 2.1.1 I/O ports (1) Port P0 Port P0 is a 4-bit I/O port.
APPLICATION 2.1 I/O pins (4) Port P3 Port P3 is a 4-bit I/O port for the 4514 Group, and a 2-bit I/O port for the 4513 Group. ■ Input/output of port P3 ● Data input to port P3 Set the output latch of specified port P3i (i=0 to 3) to “1” with the OP3A instruction. If the output latch is set to “0,” “L” level is input. The state of port P3 is transferred to register A when the IAP3 instruction is executed. However, A2 and A 3 are undefined in the 4513 Group.
APPLICATION 2.1 I/O pins (7) Port D D0–D 7 are eight independent I/O ports. ■ Input/output of port D Each pin of port D has an independent 1-bit wide I/O function. For I/O of ports D0–D 7, select one of port D with the register Y of the data pointer first. ● Data input to port D Set the output latch of specified port Di (i = 0 to 7) to “1” with the SD instruction. When the output latch is set to “0,” “L” level is input.
APPLICATION 2.1 I/O pins (2) Key-on wakeup control register K0 Register K0 controls the ON/OFF of the key-on wakeup function of ports P00–P0 3 and P1 0–P1 3. Set the contents of this register through register A with the TK0A instruction. The contents of register K0 is transferred to register A with the TAK0 instruction. Table 2.1.2 shows the key-on wakeup control register K0. Table 2.1.
APPLICATION 2.1 I/O pins (4) Direction register FR0 (The 4513 Group does not have this register.) Register FR0 is used to switch to input/output of P50–P5 3. Set the contents of this register through register A with the TFR0A instruction. Table 2.1.4 shows the direction register FR0. Table 2.1.
APPLICATION 2.1 I/O pins 2.1.3 Port application examples (1) Key input by key scan Key matrix can be set up by connecting keys externally because port D output structure is an Nchannel open-drain and port P0 has the pull-up resistor. Outline: The connecting required external part is just keys. Specifications: Port D is used to output “L” level and port P0 is used to input 16 keys. Multiple key inputs are not detected. Figure 2.1.1 shows the key input and Figure 2.1.2 shows the key input timing.
APPLICATION 2.1 I/O pins Switching key input selection port (D 0 →D 1) Stabilizing wait time for input Reading port (key input) Key input period D0 D1 D2 “H” “L” “H” “L” “H” “L” D3 “H” “L” IAP0 IAP0 IAP0 IAP0 Input to SW1–SW4 Input to SW5–SW8 Input to SW9–SW12 Input to SW13–SW16 Note: “H” output of port D becomes high-impedance state. Fig. 2.1.
APPLICATION 2.1 I/O pins 2.1.4 Notes on use (1) Note when an I/O port except port P5 is used as an input port Set the output latch to “1” and input the port value before input. If the output latch is set to “0,” “L” level can be input. (2) Noise and latch-up prevention Connect an approximate 0.1 µF bypass capacitor directly to the VSS line and the V DD line with the thickest possible wire at the shortest distance, and equalize its wiring in width and length.
APPLICATION 2.1 I/O pins Table 2.1.6 connections of unused pins Connection Pin Open (when using an external clock). X OUT VDCE D0 –D 5 D6 /CNTR0 D7 /CNTR1 P2 0/SCK P2 1/SOUT P2 2/SIN P3 0/INT0 P3 1/INT1 P3 2 , P33 P4 0/AIN4 –P43/AIN7 P5 0 –P53 (Note 1) A IN0 /CMP0A IN1 /CMP0+ A IN2 /CMP1A IN3 /CMP1+ P0 0–P0 3 P1 0–P1 3 Connect to V SS. Connect to V SS, or set the output latch to “0” and open. Connect to V SS. Connect to V SS, or set the output latch to “0” and open.
APPLICATION 2.2 Interrupts 2.2 Interrupts The 4513/4514 Group has eight interrupt sources : external (INT0, INT1), timer 1, timer 2, timer 3, timer 4, A-D, and serial I/O. This section describes individual types of interrupts, related registers, application examples using interrupts and notes. 2.2.1 Interrupt functions (1) External 0 interrupt (INT0) The interrupt request occurs by the change of input level of INT0 pin.
APPLICATION 2.2 Interrupts (4) Timer 2 interrupt The interrupt request occurs by the timer 2 underflow. ■ Timer 2 interrupt processing ● When the interrupt is used The interrupt occurrence is enabled when the bit 3 of the interrupt control register V1 and the interrupt enable flag INTE are set to “1.” When the timer 2 interrupt occurs, the interrupt processing is executed from address 6 in page 1.
APPLICATION 2.2 Interrupts (7) A-D interrupt The interrupt request occurs by the end of the A-D conversion. ■ A-D interrupt processing ● When the interrupt is used The interrupt occurrence is enabled when the bit 2 of the interrupt control register V2 and the interrupt enable flag INTE are set to “1.” When the A-D interrupt occurs, the interrupt processing is executed from address C in page 1.
APPLICATION 2.2 Interrupts (2) Interrupt control register V1 Interrupt enable bits of external 0, external 1, timer 1 and timer 2 are assigned to register V1. Set the contents of this register through register A with the TV1A instruction. In addition, the TAV1 instruction can be used to transfer the contents of register V1 to register A. Table 2.2.1 shows the interrupt control register V1. Table 2.2.
APPLICATION 2.2 Interrupts (5) Interrupt control register I1 The INT0 pin timer 1 control enable bit is assigned to bit 0, INT0 pin edge detection circuit control bit is assigned to bit 1, and interrupt valid waveform for INT0 pin/return level selection bit is assigned to bit 2. Set the contents of this register through register A with the TI1A instruction. In addition, the TAI1 instruction can be used to transfer the contents of register I1 to register A. Table 2.2.
APPLICATION 2.2 Interrupts 2.2.3 Interrupt application examples (1) External 0 interrupt The INT0 pin is used for external 0 interrupt, of which valid waveforms can be chosen, which can recognize the change of both edges (“H”→“L” or “L”→“H”). Outline: An external 0 interrupt can be used by dealing with the change of edge (“H”→“L” or “L”→“H”) in both directions as a trigger. Specifications: An interrupt occurs by the change of an external signals edge (“H”→“L” or “L”→“H”). Figure 2.2.
APPLICATION 2.2 Interrupts (6) Timer 4 interrupt Constant period interrupts by a setting value to timer 4 can be used. Outline: The constant period interrupts by the timer 4 underflow signal can be used. Specifications: Prescaler, timer 3 and timer 4 divide the system clock frequency f(XIN) = 4.0 MHz, and the timer 4 interrupt occurs every 250 ms. Figure 2.2.8 shows a setting example of the timer 4 constant period interrupt.
APPLICATION 2.2 Interrupts ➀ Disable Interrupts INT0 interrupt is temporarily disabled. Interrupt enable flag INTE “0” All interrupts disabled (DI instruction) INT0 interrupt occurrence disabled ✕ ✕ ✕ 0 (TV1A instruction) b3 Interrupt control register V1 b0 ➁ Set Port Port used for INT0 interrupt is set to input port. b3 Port P30 output latch b0 ✕ ✕ ✕ 1 Set to input (OP3A instruction) ➂ Set Valid Waveform Valid waveform of INT pin is selected.
APPLICATION 2.2 Interrupts P31/INT1 P31/INT1 “H” “L” “H” An interrupt occurs after the valid waveform “falling” is detected. An interrupt occurs after the valid waveform “rising” is detected. “L” Fig. 2.2.
APPLICATION 2.2 Interrupts ➀ Disable Interrupts INT1 interrupt is temporarily disabled. Interrupt enable flag INTE “0” All interrupts disabled (DI instruction) INT1 interrupt occurrence disabled ✕ ✕ 0 ✕ (TV1A instruction) b3 Interrupt control register V1 b0 ➁ Set Port Port used for INT1 interrupt is set to input port. b3 Port P31 output latch b0 ✕ ✕ 1 ✕ Set to input (OP3A instruction) ➂ Set Valid Waveform Valid waveform of INT pin is selected.
APPLICATION 2.2 Interrupts ➀ Disable Interrupts Timer 1 interrupt is temporarily disabled. Interrupt enable flag INTE “0” All interrupts disabled (DI instruction) Timer 1 interrupt occurrence disabled ✕0 ✕✕ (TV1A instruction) b3 Interrupt control register V1 b0 ➁ Stop Timer Operation Timer 1 and prescaler are temporarily stopped. Dividing ratio of prescaler is selected.
APPLICATION 2.2 Interrupts ➀ Disable Interrupts Timer 2 interrupt is temporarily disabled. Interrupt enable flag INTE “0” All interrupts disabled (DI instruction) Interrupt control register V1 0 ✕ ✕ ✕ Timer 2 interrupt occurrence disabled (TV1A instruction) b3 b0 ➁ Stop Timer Operation Timer is temporarily stopped. Timer 2 count source is selected.
APPLICATION 2.2 Interrupts ➀ Disable Interrupts Timer 3 interrupt is temporarily disabled. Interrupt enable flag INTE “0” All interrupts disabled (DI instruction) Timer 3 interrupt occurrence disabled ✕✕✕ 0 (TV2A instruction) b3 Interrupt control register V2 b0 ➁ Stop Timer 3 Operation Timer 3 and prescaler are temporarily stopped. Dividing ratio of prescaler is selected.
APPLICATION 2.2 Interrupts ➀ Disable Interrupts Timer 4 interrupt is temporarily disabled. Interrupt enable flag INTE “0” All interrupts disabled (DI instruction) Timer 4 interrupt occurrence disabled ✕ ✕ 0 ✕ (TV2A instruction) b3 Interrupt control register V2 b0 ➁ Stop Timer Operation Timer 4, timer 3 and prescaler are temporarily stopped. Dividing ratio of prescaler is selected.
APPLICATION 2.2 Interrupts 2.2.4 Notes on use (1) Setting of INT0 interrupt valid waveform Depending on the input state of P30 /INT0 pin, the external interrupt request flag (EXF0) may be set to “1” when the interrupt valid waveform is changed. Accordingly, set a value to the bit 2 of register I1, and execute the SNZ0 instruction to clear the EXF0 flag to “0” after executing at least one instruction.
APPLICATION 2.3 Timers 2.3 Timers The 4513/4514 Group has four 8-bit timers (each has a reload register) and a 16-bit fixed dividing frequency timer which has the watchdog timer function. This section describes individual types of timers, related registers, application examples using timers and notes. 2.3.
APPLICATION 2.3 Timers 2.3.2 Related registers (1) Interrupt control register V1 The timer 1 interrupt enable bit is assigned to bit 2, and the timer 2 interrupt enable bit is assigned to bit 3. Set the contents of this register through register A with the TV1A instruction. The TAV1 instruction can be used to transfer the contents of register V1 to register A. Table 2.3.1 shows the interrupt control register V1. Table 2.3.
APPLICATION 2.3 Timers (3) Timer control register W1 The timer 1 count start synchronous circuit control bit is assigned to bit 0, the timer 1 control bit is assigned to bit 1, the prescaler dividing ratio selection bit is assigned to bit 2, and the prescaler control bit is assigned to bit 3. Set the contents of this register through register A with the TW1A instruction. The TAW1 instruction can be used to transfer the contents of register W1 to register A. Table 2.3.3 shows the timer control register W1.
APPLICATION 2.3 Timers (5) Timer control register W3 The timer 3 count source selection bits are assigned to bits 0 and 1, the timer 3 count start synchronous circuit control bit is assigned to bit 2 and the timer 3 control bit is assigned to bit 3. Set the contents of this register through register A with the TW3A instruction. The TAW3 instruction can be used to transfer the contents of register W3 to register A. Table 2.3.5 shows the timer control register W3. Table 2.3.
APPLICATION 2.3 Timers 2.3.3 Timer application examples (1) Timer operation: measurement of constant period The constant period by the setting timer count value can be measured. Outline: The constant period by the timer 1 underflow signal can be measured. Specifications: Timer 1 and prescaler divides the system clock frequency f(X IN) = 4.0 MHz, and the timer 1 interrupt request occurs every 3 ms. Figure 2.3.3 shows the setting example of the constant period measurement.
APPLICATION 2.3 Timers (4) CNTR1 output control: square wave output control Outline: The output/stop of square wave from timer 3 every timer 4 underflow can be controlled. Specifications: 4 kHz square wave is output from timer 3 at system clock frequency f(XIN) = 4.0 MHz. Also, timer 4 controls ON/OFF of square wave every constant period. Figure 2.3.6 shows the setting example of CNTR1 output.
APPLICATION 2.3 Timers ➀ Disable Interrupts Timer 1 interrupt is temporarily disabled. Interrupt enable flag INTE “0” All interrupts disabled (DI instruction) Timer 1 interrupt occurrence disabled ✕ 0 ✕ ✕ (TV1A instruction) b3 Interrupt control register V1 b0 ➁ Stop Timer Operation Timer 1 and prescaler are temporarily stopped. Dividing ratio of prescaler is selected.
APPLICATION 2.3 Timers ➀ Disable Interrupts Timer 1 interrupt is temporarily disabled. Interrupt enable flag INTE “0” All interrupts disabled (DI instruction) b3 Interrupt control register V1 b0 ✕ 0 ✕✕ Timer 1 interrupt occurrence disabled (TV1A instruction) ➁ Stop Timer Operation Timer 1 and prescaler are temporarily stopped. Dividing ratio of prescaler is selected.
APPLICATION 2.3 Timers ➀ Disable Interrupts Timer 2 interrupt is temporarily disabled. Interrupt enable flag INTE “0” All interrupts disabled (DI instruction) b3 Interrupt control register V1 b0 0 ✕ ✕ ✕ Timer 2 interrupt occurrence disabled (TV1A instruction) ➁ Stop Timer Operation Timer 1 operation is temporarily stopped. Timer 2 count source is selected.
APPLICATION 2.3 Timers ➀ Disable Interrupts Timer 3 and timer 4 interrupt are temporarily disabled. Interrupt enable flag INTE “0” All interrupts disabled (DI instruction) Timer 3 and timer 4 interrupt occurrence disabled ✕ ✕ 0 0 (TV2A instruction) b3 Interrupt control register V2 b0 ➁ Stop Timer Operation Timer is temporarily stopped. Dividing ratio of prescaler is selected. Timer 3 count source is selected. Timer 4 count source is selected.
APPLICATION 2.3 Timers ➀ Disable Interrupts Timer 1 interrupt is temporarily disabled. Interrupt enable flag INTE “0” b3 Interrupt control register V1 All interrupts disabled (DI instruction) b0 ✕ 0 ✕ 0 Timer 1 interrupt occurrence disabled (TV1A instruction) INT0 interrupt occurrence disabled ➁ Stop Timer Operation Timer 1 and prescaler are temporarily stopped. Dividing ratio of prescaler is selected.
APPLICATION 2.3 Timers Processing in interrupt service routine ➇ Stop Timer Timer 1 control disabled b3 Interrupt control register I1 ➈ Reset Timer (TI1A instruction) (TI1A instruction) Timer count value 82 set (T1AB instruction) Timer 1 reload register R1 “5216” b3 Timer 1 control enabled b0 ✕ 1 0 0 Interrupt control register I1 b0 ✕ 1 0 1 “✕”: it can be “0” or “1.” Fig. 2.3.
APPLICATION 2.3 Timers ➀ Activate Watchdog Timer Watchdog timer is activated. Watchdog timer enable flag WEF “1” Watchdog timer enable flag WEF set (WRST instruction) Main routine (every 20 ms) Reset Flag WDF Watchdog timer flag WDF1 is reset. “0” g0 h Watchdog timer flag WDF1 cleared (WRST instruction) Main routine execution Repeat Do not clear watchdog timer WDF flag in interrupt service routine. Interrupt may be executed even if program run-away occurs.
APPLICATION 2.3 Timers 2.3.4 Notes on use (1) Prescaler Stop the prescaler operation to change its frequency dividing ratio. (2) Count source Stop timer 1, 2, 3, or 4 counting to change its count source. (3) Reading the count values Stop timer 1, 2, 3, or 4 counting and then execute the TAB1, TAB2, TAB3, or TAB4 instruction to read its data.
APPLICATION 2.4 Serial I/O 2.4 Serial I/O The 4513/4514 Group has a clock-synchronous serial I/O which can be used to transmit and receive 8-bit data. This section describes serial I/O functions, related registers, application examples using serial I/O and notes. 2.4.1 Carrier functions Serial I/O consists of the serial I/O register SI, serial I/O mode register J1, serial I/O transmit/receive completion flag SIOF and serial I/O counter.
APPLICATION 2.4 Serial I/O 2.4.2 Related registers (1) Serial I/O register SI Serial I/O register SI is the 8-bit data transfer serial/parallel conversion register. Data can be set to register SI through registers A and B with the TSIAB instruction. (2) Serial I/O mode register J1 Serial I/O synchronous clock selection bit is assigned to bit 0, serial I/O port selection bit is assigned to bit 1 and serial I/O internal clock dividing ratio selection bit is assigned to bit 2.
APPLICATION 2.4 Serial I/O 2.4.3 Operation description Figure 2.4.2 shows the serial I/O connection example, Figure 2.4.3 shows the serial I/O register state, and Figure 2.4.4 shows the serial I/O transfer timing. Master (internal clock selected) Slave (external clock selected) 4513/4514 4513/4514 Control signal D5 D5 SCK SCK SOUT SIN SIN SOUT Note: The control signal is used to inform the master by the pin level that the slave is in a ready state to receive.
APPLICATION 2.4 Serial I/O Master SOUT M7’ S7 ’ SIN M2 M1 M0 S0 S1 M3 S2 M4 S3 M5 S4 M6 S5 M7 S6 S7 SST instruction SCK Slave SST instruction Control signal SOUT SIN S0 S7’ M7’ S2 S1 M0 M1 S3 M2 S4 M3 S5 M4 S6 M5 S7 M6 M7 M0–M7: the contents of master serial I/O register S0–S7: the contents of slave serial I/O register Rising of SCK: serial input Falling of SCK: serial output M0’–M7’: previous MSB contents of master and slave Fig. 2.4.
APPLICATION 2.4 Serial I/O The full duplex communication of master and slave is described using the connection example shown in Figure 2.4.2. (1) Transmit/receive operation of master ➀ The transmit data is written into the serial I/O register SI with the TSIAB instruction. When the TSIAB instruction is executed, the contents of register A are transferred to the low-order 4 bits of register SI and the contents of register B are transferred to the high-order 4 bits of register SI.
APPLICATION 2.4 Serial I/O (2) Transmit/receive operation of slave ➀ The transmit data is written into the serial I/O register SI with the TSIAB instruction. When the TSIAB instruction is executed, the contents of register A are transferred to the low-order bits of register SI and the contents of register B are transferred to the high-order bits of register SI. At this time, the SCK pin must be at the “H” level. ➁ Serial transfer is started with the SST instruction. However, in Figure 2.4.
APPLICATION 2.4 Serial I/O ➀ Disable Interrupts Serial I/O interrupt is temporarily disabled. Interrupt enable flag INTE “0” b3 Interrupt control register V2 All interrupts disabled (DI instruction) b0 0✕ ✕✕ Serial I/O interrupt occurrence disabled (TV2A instruction) ➁ Set Serial I/O b3 b0 Internal clock selected (TJ1A instruction) Serial I/O mode register J1 ✕ 1 1 1 Serial I/O port selected Dividing ratio = 4 selected ➂ Clear Interrupt Request Serial I/O interrupt activated condition is cleared.
APPLICATION 2.4 Serial I/O ➀ Disable Interrupts Serial I/O interrupt is temporarily disabled. Interrupt enable flag INTE “0” All interrupts disabled (DI instruction) Serial I/O interrupt occurrence disabled 0✕ ✕✕ (TV2A instruction) b3 Interrupt control register V2 b0 ➁ Set Serial I/O b3 b0 Exernal clock selected (TJ1A instruction) Serial I/O mode register J1 ✕ ✕ 1 0 Serial I/O port selected ➂ Clear Interrupt Request Serial I/O interrupt activated condition is cleared.
APPLICATION 2.4 Serial I/O 2.4.5 Notes on use (1) Note when an external clock is used as a synchronous clock: • An external clock is selected as the synchronous clock, the clock is not controlled internally. • Serial transfer is continued as long as an external clock is input. If an external clock is input 9 times or more and serial transfer is continued, the receive data is transferred directly as transmit data, so that be sure to control the clock externally.
APPLICATION 2.5 A-D converter 2.5 A-D converter The 4513/4514 Group has an A-D converter with the 10-bit successive comparison method: 4 channels for the 4513 Group, 8 channels for the 4514 Group. This A-D converter can also be used as a comparator to compare analog voltages input from the analog input pin with preset values. This section describes the related registers, application examples using the A-D converter and notes. Figure 2.5.1 shows the A-D converter block diagram.
APPLICATION 2.5 A-D converter 2.5.1 Related registers (1) A-D control register Q1 Analog input pin selection bits are assigned to register Q1. Set the contents of this register through register A with the TQ1A instruction. The TAQ1 instruction can be used to transfer the contents of register Q1 to register A. Table 2.5.1 shows the A-D control register Q1. Table 2.5.
APPLICATION 2.5 A-D converter 2.5.2 A-D converter application examples (1) A-D conversion mode Outline: Analog input signal from a sensor can be converted into digital values. Specifications: Analog voltage values from a sensor is converted into digital values by using a 10bit successive comparison method. Use the AIN0 pin for this analog input. Figure 2.5.2 shows the A-D conversion mode setting example. ➀ Disable Interrupts A-D interrupt is temporarily disabled.
APPLICATION 2.5 A-D converter 2.5.3 Notes on use (1) Note when the A-D conversion starts again When the A-D conversion starts again with the ADST instruction during A-D conversion, the previous input data is invalidated and the A-D conversion starts again. (2) A-D control register Q2 Select A IN4–A IN7 with register Q1 after setting register Q2. (3) A-D converter-1 Each analog input pin is equipped with a capacitor which is used to compare the analog voltage.
APPLICATION 2.5 A-D converter (5) A-D converter is used at the comparator mode The analog input voltage is higher than the comparison voltage as a result of comparison, the contents of ADF flag retains “0,” not set to “1.” In this case, the A-D interrupt does not occur even when the usage of the A-D interrupt is enabled. Accordingly, consider the time until the comparator operation is completed, and examine the state of ADF flag by software. The comparator operation is completed after 8 machine cycles.
APPLICATION 2.6 Voltage comparator 2.6 Voltage comparator The 4513/4514 Group has two voltage comparators; CMP0-, CMP0+, CMP1-, CMP1+. This section describes the voltage comparator function, related registers, and notes. 2.6.1 Voltage comparator function (1) CMP0 ■ Voltage comparison The voltage of CMP0- is compared with that of CMP0+, and the result is stored into bit 0 of the voltage comparator control register Q3.
APPLICATION 2.6 Voltage comparator 2.6.3 Notes on use ● Voltage comparator function When the voltage comparator function is valid with the voltage comparator control register Q3, it is operating even in the RAM back-up mode. Accordingly, be careful about such state because it causes the increase of the operation current in the RAM back-up mode.
APPLICATION 2.7 Reset 2.7 Reset System reset is performed by applying “L” level to the RESET pin for 1 machine cycle or more when the following conditions are satisfied: ● the value of supply voltage is the minimum value or more of the recommended operating conditions ● oscillation is stabilized. Then when “H” level is applied to RESET pin, the software starts from address 0 in page 0 after elapsing of the internal oscillation stabilizing time (f(XIN ) is counted for 16892 to 16895 machine cycles).
APPLICATION 2.7 Reset 2.7.2 Internal state at reset Figure 2.7.3 shows the internal state at reset. The contents of timers, registers, flags and RAM other than shown in Figure 2.7.3 are undefined, so that set them to initial values. • Program counter (PC) ............................................................................................ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Address 0 in page 0 is set to program counter. • Interrupt enable flag (INTE) ................................................
APPLICATION 2.8 Voltage drop detection circuit 2.8 Voltage drop detection circuit The built-in voltage drop detection circuit is designed to detect a drop in voltage and to reset the microcomputer if the supply voltage drops below a set value. Figure 2.8.1 shows the voltage drop detection reset circuit, and Figure 2.8.2 shows the operation waveform example of the voltage drop detection circuit.
APPLICATION 2.9 RAM back-up 2.9 RAM back-up 2.9.1 RAM back-up mode The system enters RAM back-up mode when the POF instruction is executed after the EPOF instruction is executed. Table 2.9.1 shows the function and state retained at RAM back-up mode. Also, Table 2.9.2 shows the return source from this state. (1) RAM back-up mode As oscillation stops with RAM, the state of reset circuit retained, current dissipation can be reduced without losing the contents of RAM. Table 2.9.
APPLICATION 2.9 RAM back-up Table 2.9.2 Return source and return condition Return source External wakeup signal Ports P0, P1 Port P3 0/INT0 Port P3 1/INT1 Return condition Remarks Return by an external falling Set the port using the key-on wakeup function selected edge input (“H”→“L”). with register K0 to “H” level before going into the RAM back-up state because the port P0 shares the falling edge detection circuit with port P1. Return by an external “H” level or “L” level input.
APPLICATION 2.9 RAM back-up (2) Pull-up control register PU0 Pull-up control register PU0 controls the pull-up functions of ports P0 0–P03 , P10 –P13. Set the contents of this register through register A with the TPU0A instruction. The TAPU0 instruction can be used to transfer the contents of register PU0 to register A. Table 2.9.5 shows the pull-up control register PU0. Table 2.9.
APPLICATION 2.9 RAM back-up (4) Interrupt control register I2 The interrupt valid waveform for INT1 pin/return level selection bit is assigned to bit 2, the INT1 pin edge detection circuit control bit is assigned to bit 1, and the INT1 pin timer 1 control enable bit is assigned to bit 1. Set the contents of this register through register A with the TI2A instruction. In addition, the TAI2 instruction can be used to transfer the contents of register I2 to register A. Table 2.9.
APPLICATION 2.10 Oscillation circuit 2.10 Oscillation circuit The 4513/4514 Group has an internal oscillation circuit to produce the clock required for microcomputer operation. The clock signal f(XIN) is obtained by connecting a ceramic resonator to X IN pin and X OUT pin. 2.10.1 Oscillation circuit (1) f(XIN) clock generating circuit The clock signal f(X IN) is obtained by connecting a ceramic resonator externally. Connect this external circuit to pins XIN and XOUT at the shortest distance.
APPLICATION 2.10 Oscillation circuit 2.10.2 Oscillation operation System clock is supplied to CPU and peripheral device as the standard clock for the microcomputer operation. For the 4513/4514 Group, the clock (f(XIN)), (f(X IN)/2) which is supplied from the oscillation circuit is selected with the register MR. Figure 2.10.2 shows the structure of the clock control circuit.
CHAPTER 3 APPENDIX 3.1 Electrical characteristics 3.2 Typical characteristics 3.3 List of precautions 3.4 Notes on noise 3.5 Mask ROM confirmation form 3.6 Mark specification form 3.
APPENDIX 3.1 Electrical characteristics 3.1 Electrical characteristics 3.1.1 Absolute maximum ratings Table 3.1.
APPENDIX 3.1 Electrical characteristics 3.1.2 Recommended operating conditions Table 3.1.2 Recommended operating conditions 1 (Mask ROM version:Ta = –20 °C to 85 °C, VDD = 2.0 V to 5.5 V, unless otherwise noted) (One Time PROM version:Ta = –20 °C to 85 °C, VDD = 2.5 V to 5.5 V, unless otherwise noted) Symbol Parameter Mask ROM version Middle-speed mode VDD Supply voltage Limits Conditions Mask ROM version High-speed mode f(XIN) ≤ 4.2 MHz f(XIN) ≤ 3.0 MHz f(XIN) ≤ 4.2 MHz f(XIN) ≤ 2.0 MHz f(XIN) ≤ 1.
APPENDIX 3.1 Electrical characteristics Table 3.1.3 Recommended operating conditions 2 (Mask ROM version:Ta = –20 °C to 85 °C, VDD = 2.0 V to 5.5 V, unless otherwise noted) (One Time PROM version:Ta = –20 °C to 85 °C, VDD = 2.5 V to 5.5 V, unless otherwise noted) Symbol f(XIN) Parameter Oscillation frequency (with a ceramic resonator) Conditions Mask ROM version VDD = 2.5 V to 5.5 V Middle-speed mode One Time PROM version Middle-speed mode VDD = 2.0 V to 5.5 V VDD = 2.5 V to 5.5 V 4.2 VDD = 4.
APPENDIX 3.1 Electrical characteristics 3.1.3 Electrical characteristics Table 3.1.4 Electrical characteristics (Mask ROM version:Ta = –20 °C to 85 °C, VDD = 2.0 V to 5.5 V, unless otherwise noted) (One Time PROM version:Ta = –20 °C to 85 °C, VDD = 2.5 V to 5.
APPENDIX 3.1 Electrical characteristics 3.1.4 A-D converter recommended operating conditions Table 3.1.5 A-D converter recommended operating conditions (Comparator mode included, Ta = –20 °C to 85 °C, unless otherwise noted) Symbol Parameter VDD Supply voltage VIA Analog input voltage f(XIN) Oscillation frequency Conditions Middle-speed mode, V DD ≥ 2.7 V High-speed mode, VDD ≥ 2.7 V Min. Limits Typ. 2.7 0 0.8 0.4 Max. 5.5 VDD Unit V V MHz MHz Table 3.1.
APPENDIX 3.1 Electrical characteristics 3.1.6 Voltage comparator characteristics Table 3.1.8 Voltage comparator recommended operating conditions (Ta = –20 °C to 85 °C, unless otherwise noted) Symbol VDD Conditions Parameter Supply voltage Voltage comparator input voltage Voltage comparator response time VINCMP t CMP VDD = 3.0 V to 5.5 V VDD = 3.0 V to 5.5 V Min. 3.0 0.3VDD Limits Typ. Max. 5.5 0.7VDD 20 Unit V V µs Table 3.1.9 Voltage comparator characteristics (Ta = –20 °C to 85 °C, VDD = 3.
APPENDIX 3.2 Typical characteristics 3.2 Typical characteristics 3.2.1 V DD–I DD characteristics (1) CPU operating, middle-speed mode 2.5 Ta = 25 °C 2.4 2.3 2.2 2.1 2 1.9 Supply current I DD (mA) 1.8 1.7 1.6 1.5 1.4 f(X IN) = 4 MHz 1.3 1.2 1.1 1 f(XIN ) = 1 MHz 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 2 2.5 3 3.5 4 4.5 5 5.5 Supply voltage V DD (V) (2) CPU operating, high-speed mode 2.5 Ta = 25 °C 2.4 2.3 2.2 2.1 2 f(X IN) = 4 MHz 1.9 Supply current I DD (mA) 1.8 1.7 1.6 1.5 1.4 1.3 1.
APPENDIX 3.2 Typical characteristics (3) A-D operating, middle-speed mode Ta = 25 °C 2.5 2.4 2.3 2.2 2.1 2 1.9 f(X IN) = 4 MHz Supply current IDD (mA) 1.8 1.7 1.6 1.5 1.4 f(XIN ) = 1 MHz 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 2 (4) 2.5 3 3.5 4 4.5 5 5.5 Supply voltage VDD (V) A-D operating, high-speed mode Ta = 25 °C 2.5 2.4 f(X IN) = 4 MHz 2.3 2.2 2.1 2 1.9 1.8 Supply current I DD (mA) 1.7 1.6 1.5 f(X IN) = 1 MHz 1.4 1.3 1.2 1.1 1 0.9 0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.
APPENDIX 3.2 Typical characteristics (5) RAM back-up Ta = 25 °C 5 4.5 4 3.5 Supply current I DD (nA) 3 2.5 2 1.5 1 0.5 0 2 2.5 3 3.5 4 Supply voltage V DD (V) 3-10 4513/4514 Group User’s Manual 4.5 5 5.
APPENDIX 3.2 Typical characteristics 3.2.2 V OL–I OL characteristics (1) Ports P0, P1, P4, P5, SCK , SOUT Ta = 25 °C 100 90 V DD = 6 V 80 V DD = 5 V Output current IOL (mA) 70 60 V DD = 4 V 50 40 V DD = 3 V 30 20 V DD = 2 V 10 0 0 0.5 1 1.5 2 Output voltage VOL (V) (2) Port P3, RESET pin Ta = 25 °C 100 90 Output current I OL (mA) 80 70 60 50 V DD = 6 V 40 V DD = 5 V 30 V DD = 4 V V DD = 3 V 20 10 V DD = 2 V 0 0 0.5 1 1.
APPENDIX 3.2 Typical characteristics (3) Pins D0–D 5 Ta = 25 °C 100 90 Output current IOL (mA) 80 70 60 V DD = 6 V V DD = 5 V 50 V DD = 4 V 40 V DD = 3 V 30 20 V DD = 2 V 10 0 0 0.5 1 1.5 2 Output voltage V OL (V) (4) Pins D6/CNTR0, D 7/CNTR1 Ta = 25 °C 100 90 80 Output current I OL (mA) V DD = 6 V 70 V DD = 5 V V DD = 4 V 60 50 V DD = 3 V 40 30 V DD = 2 V 20 10 0 0 0.5 1 Output voltage V OL (V) 3-12 4513/4514 Group User’s Manual 1.
APPENDIX 3.2 Typical characteristics 3.2.3 V OH–I OH characteristics (Port P5) V DD = 2 V 0 V DD = 3 V V DD = 4 V V DD = 5 V V DD = 6 V Ta = 25 °C -10 -20 Output current IOH (mA) -30 -40 -50 -60 -70 -80 -90 -100 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 Output voltage V OH (V) 3.2.4 V DD–R PU characteristics (Ports P0, P1) 350 Ta = 25 °C Pull-up resistor R PU (kΩ) 300 250 200 150 100 50 0 2 2.5 3 3.5 4 4.5 5 5.
APPENDIX 3.2 Typical characteristics 3.2.5 A-D converter typical characteristics 30 1LSB WIDTH +1LSB ➀ 0 ➂ ➃ 0 ➄ ERROR 1LSB WIDTH [ mV] ERROR [mV] ➁ -1LSB -30 0 1 1022 1023 Fig. 3.2.1 A-D conversion characteristics data Figure 3.2.1 shows the A-D accuracy measurement data. (1) Non-linearity error ......................... This means a deviation from the ideal characteristics between V0 to V 1022 of actual A-D conversion characteristics. In Figure 3.2.1, it is (➃–➀)/1LSB.
APPENDIX 3.2 Typical characteristics (1) V DD = 3.072 V, f(XIN) = 2 MHz, high-speed mode Ta = 25 °C ERROR / 1LSB WIDTH(mV) 4.5 1LSB WIDTH 3 1.5 ERRO R 0 -1.5 -3 -4.5 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 400 416 432 448 464 480 496 512 656 672 688 704 720 736 752 768 912 928 944 960 976 992 1008 1024 STEP No. ERROR / 1LSB WIDTH(mV) 4.5 3 1.5 0 -1.5 -3 -4.5 256 272 288 304 320 336 352 368 384 STEP No. ERROR / 1LSB WIDTH(mV) 4.
APPENDIX 3.2 Typical characteristics (2) V DD = 5.12 V, f(XIN ) = 4 MHz, high-speed mode Ta = 25 °C ERROR / 1LSB WIDTH(mV) 7.5 1LSB WIDTH 5 2.5 ERRO R 0 -2.5 -5 -7.5 0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 256 400 416 432 448 464 480 496 512 656 672 688 704 720 736 752 768 912 928 944 960 976 992 1008 1024 STEP No. ERROR / 1LSB WIDTH(mV) 7.5 5 2.5 0 -2.5 -5 -7.5 256 272 288 304 320 336 352 368 384 STEP No. ERROR / 1LSB WIDTH(mV) 7.
APPENDIX 3.2 Typical characteristics 3.2.6 Analog input current characteristics pins A IN0–A IN7 (1) V DD = 3.0 V, f(XIN ) = 2 MHz, middle-speed mode Ta = 25 °C 25 Analog input current IAIN (nA) 20 15 10 5 0 -5 -10 -15 -20 -25 0 0.5 1 1.5 2 2.5 3 Analog input voltage VAIN (V) (2) V DD = 3.0 V, f(XIN ) = 4 MHz, middle-speed mode Ta = 25 °C 100 80 Analog input current IAIN (nA) 60 40 20 0 -20 -40 -60 -80 -100 0 0.5 1 1.5 2 2.5 3 3.5 4 4.
APPENDIX 3.2 Typical characteristics (3) V DD = 3.0 V, f(X IN) = 2 MHz, high-speed mode Ta = 25 °C 50 40 Analog input current IAIN (nA) 30 20 10 0 -10 -20 -30 -40 -50 0 0.5 1 1.5 2 2.5 3 Analog input voltage VAIN (V) (4) V DD = 5.0 V, f(X IN) = 4 MHz, high-speed mode Ta = 25 °C 200 160 120 Analog input current IAIN (nA) 80 40 0 -40 -80 -120 -160 -200 0 0.5 1 1.5 2 2.5 3 3.5 Analog input voltage VAIN (V) 3-18 4513/4514 Group User’s Manual 4 4.
APPENDIX 3.2 Typical characteristics 3.2.7 V DD–V IH/VIL characteristics (1) RESET pin Ta = 25 °C 5.5 V IH (rating value) 5 4.5 V IH 4 3.5 V IH/VIL (V) 3 V IL 2.5 2 V IL (rating value) 1.5 1 0.5 0 2 2.5 3 3.5 4 4.5 5 5.5 6 Supply voltage V DD (V) (2) Ports P0, P1, P2, P3, P4, P5, D, X IN pin, VDCE pin Ta = 25 °C 5.5 5 V IH (rating value) 4.5 4 V IH/VIL (V) 3.5 3 V IH, V IL 2.5 2 1.5 V IL (rating value) 1 0.5 0 2 2.5 3 3.5 4 4.5 5 5.
APPENDIX 3.2 Typical characteristics (3) Pins INT0, INT1, CNTR0, CNTR1, S CK, SIN Ta = 25 °C 5.5 V IL (rating value) 5 4.5 4 V IH/VIL (V) 3.5 V IH V IL 3 2.5 2 1.5 1 V IH (rating value) 0.5 0 2 2.5 3 3.5 4 4.5 5 5.5 6 Supply voltage V DD (V) 3.2.8 Detection voltage temperature characteristics of voltage drop detection circuit 4.5 4.4 4.3 4.2 4.1 Detection voltage VRST (V) 4 3.9 3.8 3.7 3.6 3.5 3.4 3.3 3.2 3.1 3 2.9 2.8 2.7 2.6 2.
APPENDIX 3.3 List of precautions 3.3 List of precautions ➀Noise and latch-up prevention Connect a capacitor on the following condition to prevent noise and latch-up; • connect a bypass capacitor (approx. 0.1 µF) between pins V DD and VSS at the shortest distance, • equalize its wiring in width and length, and • use relatively thick wire. In the One Time PROM version, CNV SS pin is also used as VPP pin.
APPENDIX 3.3 List of precautions ➉ A-D converter-1 When the operating mode of the A-D converter is changed from the comparator mode to the A-D conversion mode with the bit 3 of register Q2 in a program, be careful about the following notes. • Clear the bit 2 of register V2 to “0” to change the operating mode of the A-D converter from the comparator mode to the A-D conversion mode with the bit 3 of register Q2 (refer to Figure 46➄).
APPENDIX 3.3 List of precautions 16 Voltage comparator function When the voltage comparator function is valid with the voltage comparator control register Q3, it is operating even in the RAM back-up mode. Accordingly, be careful about such state because it causes the increase of the operation current in the RAM backup mode.
APPENDIX 3.4 Notes on noise 3.4 Notes on noise Countermeasures against noise are described below. The following countermeasures are effective against noise in theory, however, it is necessary not only to take measures as follows but to evaluate before actual use. 3.4.1 Shortest wiring length The wiring on a printed circuit board can function as an antenna which feeds noise into the microcomputer.
APPENDIX 3.4 Notes on noise (3) Wiring for clock input/output pins • Make the length of wiring which is connected to clock I/O pins as short as possible. • Make the length of wiring across the grounding lead of a capacitor which is connected to an oscillator and the VSS pin of a microcomputer as short as possible. • Separate the VSS pattern only for oscillation from other V SS patterns. Noise (4) Wiring to CNVSS pin Connect the CNVSS pin to the V SS pin with the shortest possible wiring.
APPENDIX 3.4 Notes on noise (5) Wiring to VPP pin of One Time PROM version In the built-in PROM version of the 4513/4514 Group, the CNV SS pin is also used as the built-in PROM power supply input pin V PP. ● When the V PP pin is also used as the CNVSS pin Connect an approximately 5 kΩ resistor to the V PP pin the shortest possible in series and also to the VSS pin. When not connecting the resistor, make the length of wiring between the V PP pin and the V SS pin the shortest possible (refer to Figure 3.4.
APPENDIX 3.4 Notes on noise 3.4.3 Wiring to analog input pins • Connect an approximately 100 Ω to 1 kΩ resistor to an analog signal line which is connected to an analog input pin in series. Besides, connect the resistor to the microcomputer as close as possible. • Connect an approximately 1000 pF capacitor across the V SS pin and the analog input pin. Besides, connect the capacitor to the V SS pin as close as possible. Also, connect the capacitor across the analog input pin and the VSS pin at equal length.
APPENDIX 3.4 Notes on noise N.G. Do not cross 3.4.5 Setup for I/O ports Setup I/O ports using hardware and software as follows: • Connect a resistor of 100 Ω or more to an I/O port in series. CNTR XIN XOUT VSS Fig. 3.4.
APPENDIX 3.4 Notes on noise • Assigns a single word of RAM to a software watchdog timer (SWDT) and writes the initial value N in the SWDT once at each execution of the main routine. The initial value N should satisfy the following condition: N+1≥ (Counts of interrupt processing executed in each main routine) As the main routine execution cycle may change because of an interrupt processing or others, the initial value N should have a margin.
APPENDIX 3.5 Mask ROM order confirmation form 3.5 Mask ROM order confirmation form GZZ-SH52-45B <81A0> Mask ROM number 4500 SERIES MASK ROM ORDER CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M34513M2-XXXSP/FP MITSUBISHI ELECTRIC Receipt Date: Please fill in all items marked ✽ . ✽ Customer TEL ( Date issued Issuance signature Company name ) Date: Section head S u p e r v i s o r signature signature Responsible Supervisor officer ✽ 1. Confirmation Specify the type of EPROMs submitted.
APPENDIX 3.5 Mask ROM order confirmation form GZZ-SH52-44B <81A0> Mask ROM number 4500 SERIES MASK ROM ORDER CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M34513M4-XXXSP/FP MITSUBISHI ELECTRIC Receipt Date: Please fill in all items marked ✽ . ✽ Customer TEL ( Date issued Issuance signature Company name ) Date: Section head S u p e r v i s o r signature signature Responsible Supervisor officer ✽ 1. Confirmation Specify the type of EPROMs submitted.
APPENDIX 3.5 Mask ROM order confirmation form GZZ-SH53-01B <85A0> Mask ROM number 4500 SERIES MASK ROM ORDER CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M34513M6-XXXFP MITSUBISHI ELECTRIC Receipt Date: Please fill in all items marked ✽ . ✽ Customer TEL ( Date issued Issuance signature Company name ) Date: Section head S u p e r v i s o r signature signature Responsible Supervisor officer ✽ 1. Confirmation Specify the type of EPROMs submitted.
APPENDIX 3.5 Mask ROM order confirmation form GZZ-SH52-99B <85A0> Mask ROM number 4500 SERIES MASK ROM ORDER CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M34513M8-XXXFP MITSUBISHI ELECTRIC Receipt Date: Please fill in all items marked ✽ . ✽ Customer TEL ( Date issued Issuance signature Company name ) Date: Section head S u p e r v i s o r signature signature Responsible Supervisor officer ✽ 1. Confirmation Specify the type of EPROMs submitted.
APPENDIX 3.5 Mask ROM order confirmation form GZZ-SH52-41B <81A0> Mask ROM number 4500 SERIES MASK ROM ORDER CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M34514M6-XXXFP MITSUBISHI ELECTRIC Receipt Date: Please fill in all items marked ✽ . ✽ Customer TEL ( Date issued Issuance signature Company name ) Date: Section head S u p e r v i s o r signature signature Responsible Supervisor officer ✽ 1. Confirmation Specify the type of EPROMs submitted.
APPENDIX 3.5 Mask ROM order confirmation form GZZ-SH52-40B <81A0> Mask ROM number 4500 SERIES MASK ROM ORDER CONFIRMATION FORM SINGLE-CHIP MICROCOMPUTER M34514M8-XXXFP MITSUBISHI ELECTRIC Receipt Date: Please fill in all items marked ✽ . ✽ Customer TEL ( Date issued Issuance signature Company name ) Date: Section head S u p e r v i s o r signature signature Responsible Supervisor officer ✽ 1. Confirmation Specify the type of EPROMs submitted.
APPENDIX 3.6 Mark specification form 3.6 Mark specification form 32P4B (32-PIN SHRINK DIP) MARK SPECIFICATION FORM Mitsubishi IC catalog name Please choose one of the marking types below (A, B, C), and enter the Mitsubishi IC catalog name and the special mark (if needed). A. Standard Mitsubishi Mark 17 32 Mitsubishi lot number (6-digit or 7-digit) Mitsubishi IC catalog name 1 16 B.
APPENDIX 3.6 Mark specification form 32P6B (32-PIN LQFP) MARK SPECIFICATION FORM Mitsubishi IC catalog name Please choose one of the marking types below (A, B), and enter the Mitsubishi catalog name and the special mark (if needed). A. Standard Mitsubishi Mark 17 24 16 25 Mitsubishi IC catalog name Mitsubishi IC catalog name Mitsubishi lot number (4-digit or 5-digit) 32 9 1 8 B.
APPENDIX 3.6 Mark specification form 42P2R-A (42-PIN SHRINK SOP) MARK SPECIFICATION FORM Mitsubishi IC catalog name Please choose one of the marking types below (A, B, C), and enter the Mitsubishi catalog name and the special mark (if needed). A. Standard Mitsubishi Mark 42 22 Mitsubishi IC catalog name Mitsubishi IC catalog name Mitsubishi lot number (6-digit or 7-digit) 21 1 B.
APPENDIX 3.7 Package outline 3.7 Package outline 32P4B Plastic 32pin 400mil SDIP EIAJ Package Code SDIP32-P-400-1.78 Weight(g) 2.2 Lead Material Alloy 42/Cu Alloy 17 1 16 E 32 e1 c JEDEC Code – D Symbol L A1 A A2 A A1 A2 b b1 b2 c D E e e1 L e b1 b b2 SEATING PLANE 32P6B-A Dimension in Millimeters Min Nom Max – – 5.08 0.51 – – – 3.8 – 0.35 0.45 0.55 0.9 1.0 1.3 0.63 0.73 1.03 0.22 0.27 0.34 27.8 28.0 28.2 8.75 8.9 9.05 – 1.778 – – 10.16 – 3.
APPENDIX 3.7 Package outline 42P2R-A Plastic 42pin 450mil SSOP EIAJ Package Code SSOP42-P-450-0.80 JEDEC Code – Weight(g) 0.63 Lead Material Alloy 42/Cu Alloy e 42 b2 E HE e1 I2 22 F Recommended Mount Pad Symbol 1 21 A D b L y A1 L1 e A2 c Detail F 3-40 4513/4514 Group User’s Manual A A1 A2 b c D E e HE L L1 y b2 e1 I2 Dimension in Millimeters Min Nom Max 2.4 – – – – 0.05 – 2.0 – 0.5 0.4 0.35 0.2 0.15 0.13 17.7 17.5 17.3 8.6 8.4 8.2 – 0.8 – 12.23 11.93 11.63 0.7 0.5 0.3 – 1.
MITSUBISHI SEMICONDUCTORS USER’S MANUAL 4513/4514 Group Dec. First Edition 1998 Editioned by Committee of editing of Mitsubishi Semiconductor USER’S MANUAL Published by Mitsubishi Electric Corp., Semiconductor Marketing Division This book, or parts thereof, may not be reproduced in any form without permission of Mitsubishi Electric Corporation.
REVISION DESCRIPTION LIST Rev. No. 1.0 4513/4514 GROUP USER'S MANUAL Revision Description First Edition Rev.
User’s Manual 4513/4514 Group © 1998 MITSUBISHI ELECTRIC CORPORATION. New publication, effective Dec. 1998. Specifications subject to change without notice.