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To our customers,

Old Company Name in Catalogs and Other Documents

On April 1

, 2010, NEC Electronics Corporation merged with Renesas Technology

Corporation, and Renesas Electronics Corporation took over all the business of both

companies. Therefore, although the old company name remains in this document, it is a valid

Renesas Electronics document. We appreciate your understanding.

Renesas Electronics website: http://www.renesas.com

April 1

, 2010

Renesas Electronics Corporation

Issued by: Renesas Electronics Corporation (http://www.renesas.com)

Send any inquiries to http://www.renesas.com/inquiry.

Summary of content (49 pages)

PAGE 1
To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.
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Notice 1. 2. 3. 4. 5. 6. 7. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office.
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DATA SHEET MOS INTEGRATED CIRCUIT µPD70F3003A, 70F3025A, 70F3003A(A) V853 32-BIT SINGLE-CHIP MICROCONTROLLERS DESCRIPTION The µPD70F3003A, µPD70F3025A, and µPD70F3003A(A) have a flash memory instead of the internal mask ROM of the µPD703003A/703004A, µPD703025A, and µPD703003A(A), respectively. This model is useful for small-scale production of a variety of application sets or early start of production since the program can be written and erased by the user even with the µPD70F3003 mounted on the board.
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µPD70F3003A, 70F3025A, 70F3003A(A) APPLICATIONS µ PD70F3003A, 70F3025A: Camcorders, VCRs, PPCs, LBPs, printers, motor controllers, NC machine tools, mobile telephones, etc. µ PD70F3003A(A): Medical equipment, automotive appliances, etc.
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µPD70F3003A, 70F3025A, 70F3003A(A) PIN NAMES A16 to A19: Address bus P40 to P47: Port 4 AD0 to AD15: Address/data bus P50 to P57: Port 5 ADTRG: A/D Trigger input P60 to P63: Port 6 ANI0 to ANI7: Analog input P70 to P77: Port 7 ANO0, ANO1: Analog output P90 to P96: Port 9 ASTB: Address strobe P110 to P117: Port 11 AV DD : Analog V DD PWM0, PWM1: Pulse width modulation AV REF1 to AV REF3: Analog reference voltage RESET: Reset AV SS : Analog V SS R/W: Read/write status CV DD
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µPD70F3003A, 70F3025A, 70F3003A(A) INTERNAL BLOCK DIAGRAM Flash memory CPU NMI INTP110 to INTP113 INTP120 to INTP123 INTP130 to INTP133 INTP140 to INTP143 Note 1 TO110, TO111 TO120, TO121 TO130, TO131 TO140, TO141 Instruction queue PC INTC 32-bit barrel shifter Multiplier 16 × 16 → 32 System register RPU RAM TCLR11 to TCLR14 TI11 to TI14 Note 2 BCU ASTB DSTB R/W UBEN LBEN WAIT A16 to A19 AD0 to AD15 HLDRQ HLDAK Generalpurpose register 32 bits × 32 ALU SIO SO0/TXD0 SI0/RXD0 SCK0 UART0/CSI
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µPD70F3003A, 70F3025A, 70F3003A(A) CONTENTS 1. DIFFERENCES BETWEEN PRODUCTS ·························································································· 6 2. PIN FUNCTIONS ································································································································ 7 2.1 Port Pins ····················································································································································· 7 2.
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µPD70F3003A, 70F3025A, 70F3003A(A) 1. DIFFERENCES BETWEEN PRODUCTS Item Internal ROM µ PD703003A µ PD703004A µ PD703025A µ PD703003A(A) µ PD703025A(A) µ PD70F3003A µ PD70F3025A µ PD70F3003A(A) Mask ROM 128 KB Flash memory 96 KB 256 KB 128 KB 256 KB 8 KB 4 KB 8 KB 128 KB Internal RAM 4 KB Flash memory programming mode None Provided V PP pin None Provided Quality grade Standard Special 4 KB 256 KB 128 KB 8 KB Standard 4 KB Special Electrical specifications Current consumption, etc.
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µPD70F3003A, 70F3025A, 70F3003A(A) 2. PIN FUNCTIONS 2.1 Port Pins (1/2) Pin Name P00 I/O I/O Function Alternate Function Port 0 TO110 P01 8-bit I/O port. TO111 P02 Input/output can be specified in 1-bit units. TCLR11 P03 TI11 P04 INTP110 P05 INTP111 P06 INTP112 P07 INTP113/ADTRG P10 I/O Port 1 TO120 P11 8-bit I/O port. TO121 P12 Input/output can be specified in 1-bit units.
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µPD70F3003A, 70F3025A, 70F3003A(A) (2/2) Pin Name P60 to P63 I/O I/O Function Port 6 Alternate Function A16 to A19 4-bit I/O port. Input/output can be specified in 1-bit units. P70 to P77 Input Port 7 ANI0 to ANI7 8-bit input port. P90 Port 9 LBEN P91 7-bit I/O port. UBEN P92 Input/output can be specified in 1-bit units. R/W P93 DSTB P94 ASTB P95 HLDAK P96 HLDRQ P110 8 I/O I/O Port 11 TO140 P111 8-bit I/O port. TO141 P112 Input/output can be specified in 1-bit units.
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µPD70F3003A, 70F3025A, 70F3003A(A) 2.
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µPD70F3003A, 70F3025A, 70F3003A(A) (2/2) Pin Name SCK0 I/O I/O Function Serial clock I/O for CSI0 to CSI3 (3-wire) Alternate Function P24 SCK1 P27 SCK2 P17/INTP123 SCK3 P37/INTP133 TXD0 Output Serial transmit data output of UART0 to UART1 TXD1 RXD0 P25/SO1 Input Serial receive data input of UART0 to UART1 RXD1 PWM0 P23/SI0 P26/SI1 Output Pulse signal output of PWM PWM1 AD0 to AD7 P22/SO0 P20 P21 I/O 16-bit multiplexed address/data bus when external memory is connected AD8 to AD15 P
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µPD70F3003A, 70F3025A, 70F3003A(A) 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins Table 2-1 shows the I/O circuit type of each pin, and the recommended connections of the unused pins. Figure 2-1 shows a partially simplified diagram of each circuit. It is recommended that 1 to 10 kΩ resistors be used when connecting to V DD or V SS via a resistor. Table 2-1.
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µPD70F3003A, 70F3025A, 70F3003A(A) Table 2-1. Types of Pin I/O Circuits and Recommended Connection of Unused Pins (2/2) Pin Name I/O Circuit Type Recommended Connection of Unused Pins ANO0, ANO1 12 Leave open. NMI 2 Directly connect to VSS. CLKOUT 3 Leave open. WAIT 1 Directly connect to VDD. MODE 2 — RESET CVDD/CKSEL — AVREF1 to AVREF3, AVSS — Directly connect to VSS. AVDD — Directly connect to VDD. VPP — Connect to VSS.
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µPD70F3003A, 70F3025A, 70F3003A(A) Figure 2-1.
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µPD70F3003A, 70F3025A, 70F3003A(A) 3. ELECTRICAL SPECIFICATIONS 3.1 Normal Operation Mode Absolute Maximum Ratings (TA = 25°C) Parameter Supply voltage Symbol VDD Input voltage Conditions VDD pin Ratings Unit –0.5 to +7.0 CVDD CVDD pin –0.5 to VDD + 0.3 CVSS CVSS pin –0.5 to +0.5 V Note 1 V AVDD AVDD pin –0.5 to VDD + 0.3 AVSS AVSS pin –0.5 to +0.5 VI1 Note 2, VDD = 5.0 V ±10% VI2 VPP pin in flash memory programming mode, –0.5 to VDD + 0.3 V Note 1 V V Note 1 V –0.5 to +11.
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µPD70F3003A, 70F3025A, 70F3003A(A) Capacitance (TA = 25°C, VDD = VSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit Input capacitance CI fc = 1 MHz 15 pF I/O capacitance CIO Pins other than tested pin: 0 V 15 pF Output capacitance CO 15 pF Operating Conditions Operation Mode Internal System Clock Frequency (φ) Direct mode, PLL mode Operating Temperature (TA) Supply Voltage (VDD) 2 to 33 MHz Note 1 –40 to +85°C 5.0 V ±10% 5 to 33 MHz Note 2 –40 to +85°C 5.
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µPD70F3003A, 70F3025A, 70F3003A(A) (b) µPD70F3025A X1 X2 Rd C1 Manufacturer Part Number C2 Oscillation Recommended Frequency fXX (MHz) Circuit Constant Oscillation C1 (pF) C2 (pF) Rd (W) Oscillation Voltage Range Stabilization Time MIN. (V) MAX. (V) (MAX.) TOST (ms) Kyocera PBRC4.00HR 4.0 On-chip On-chip — 4.5 5.5 0.12 Corporation PBRC5.00HR 5.0 On-chip On-chip — 4.5 5.5 0.04 PBRC6.00HR 6.0 On-chip On-chip — 4.5 5.5 0.04 PBRC6.60HR 6.6 On-chip On-chip — 4.5 5.
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µPD70F3003A, 70F3025A, 70F3003A(A) DC Characteristics (TA = –40 to +85°C, VDD = 5.0 V ±10%, VSS = 0 V) (1/2) Parameter Input voltage, high Symbol VIH Conditions MIN. Except X1 and Note MAX. Unit 2.2 VDD + 0.3 V 0.8VDD VDD + 0.3 V Except X1 and Note –0.5 +0.8 V Note –0.5 0.2VDD V Note Input voltage, low VIL TYP. Clock input voltage, high VXH X1 0.8VDD VDD + 0.5 V Clock input voltage, low VXL X1 –0.5 0.
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µPD70F3003A, 70F3025A, 70F3003A(A) (2/2) Parameter Symbol Supply µPD70F3003A, Operating IDD1 current 70F3003A(A) In HALT mode In IDLE mode IDD2 IDD3 In STOP mode IDD4 Conditions MIN. TYP. MAX. Unit Direct mode 2.2 × φ + 7.5 2.5 × φ + 22 mA PLL mode 2.3 × φ + 9.5 2.6 × φ + 25 mA Direct mode 1.2 × φ + 7.5 1.3 × φ + 15 mA PLL mode 1.3 × φ + 9.5 1.4 × φ + 17 mA Direct mode 8 × φ + 300 10 × φ + 500 µA PLL mode 0.1 × φ + 2 0.
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µPD70F3003A, 70F3025A, 70F3003A(A) Data Retention Characteristics (TA = –40 to +85°C, VDD = VDDDR) Parameter Symbol Conditions MIN. TYP. 1.5 MAX. Unit 5.5 V Data hold voltage VDDDR STOP mode Data hold current IDDDR µPD70F3003A, CESEL = 0, Note 1 0.4VDDDR 50 µA 70F3003A(A) CESEL = 0, Note 2 0.4VDDDR 200 µA CESEL = 1, Note 1 6VDDDR 200 µA CESEL = 1, Note 2 6VDDDR 500 µA µPD70F3025A CESEL = 0, Note 1 0.4VDDDR 50 µA CESEL = 0, Note 2 0.
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µPD70F3003A, 70F3025A, 70F3003A(A) STOP mode is set (at fifth clock after PSC register has been set).
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µPD70F3003A, 70F3025A, 70F3003A(A) AC Characteristics (TA = –40 to +85°C, VDD = 5.0 V ±10%, VSS = 0 V) AC test input test points (a) P02 to P07, P12 to P17, P23, P24, P26, P27, P32 to P37, P112 to P117, RESET, NMI, MODE, X1, and their alternate-function pins VDD 0.8VDD 0.8VDD Test points 0V 0.2VDD 0.2VDD (b) Other than (a) 2.4 V 2.2 V 2.2 V Test points 0.4 V 0.8 V 0.8 V AC test output test points 2.2 V 2.2 V Test points 0.8 V 0.
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µPD70F3003A, 70F3025A, 70F3003A(A) (1) Clock timing Parameter X1 input cycle Symbol <1> Conditions tCYX Direct mode PLL mode (PLL lock status) X1 input width, high X1 input width, low X1 input rise time <2> <3> <4> tWXH tWXL tXR MIN. MAX.
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µPD70F3003A, 70F3025A, 70F3003A(A) (2) Input wave (a) P02 to P07, P12 to P17, P23, P24, P26, P27, P32 to P37, P112 to P117, RESET, NMI, MODE, and their alternate-function pins Parameter Symbol Conditions MIN. MAX. Unit Input rise time <12> tIR2 20 ns Input fall time <13> tIF2 20 ns VDD 0.8VDD 0.8VDD Input signal 0.2VDD 0V 0.2VDD < 13 > < 12 > (b) Other than (a) Parameter Symbol Conditions MIN. MAX.
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µPD70F3003A, 70F3025A, 70F3003A(A) (3) Output wave (other than CLKOUT) Parameter Symbol Conditions MIN. MAX. Unit Output rise time <16> tOR 10 ns Output fall time <17> tOF 10 ns 2.2 V 2.2 V Output signal 0.8 V 0.8 V < 16 > < 17 > (4) Reset timing Parameter Symbol Conditions RESET width, high <18> tWRSH RESET width, low <19> tWRSL On power application, or on releasing STOP mode Except on power application, or except on releasing STOP mode MIN.
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µPD70F3003A, 70F3025A, 70F3003A(A) (5) Read timing (1/2) Parameter Symbol Conditions MIN. MAX.
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µPD70F3003A, 70F3025A, 70F3003A(A) (5) Read Timing (2/2): 1 wait T1 T2 TW T3 CLKOUT (output) < 20 > < 28 > A16 to A19 (output) < 78 > R/W (output) UBEN (output) LBEN (output) < 32 > < 21 > AD0-AD15 (I/O) < 24 > A0 to A15 (output) D0 to D15 (input) < 22 > < 29 > < 25 > < 35 > < 30 > < 22 > ASTB (output) < 40> < 37 > < 23 >< 31 > < 34 > < 23 > < 33 > < 36 > DSTB (output) < 38 > < 39 > < 45 > < 26 > < 27 > < 26 > < 47 > < 46 > < 48 > WAIT (input) < 41 > < 43 > < 42 > < 44 > Rema
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µPD70F3003A, 70F3025A, 70F3003A(A) (6) Write timing (1/2) Parameter Symbol Conditions MIN. MAX.
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µPD70F3003A, 70F3025A, 70F3003A(A) (6) Write timing (2/2): 1 wait T1 T2 TW T3 CLKOUT (output) < 20 > < 28 > A16 to A19 (output) < 78 > R/W (output) UBEN (output) LBEN (output) < 49 > AD0-AD15 (I/O) < 51 > A0 to A15 (output) D0 to D15 (output) < 22 > < 29 > < 30 > < 22 > ASTB (output) < 23 > < 23 > < 40 > < 34 > < 53 > < 52 > < 50 > DSTB (output) < 39 > < 45 > < 26 > < 27 > < 26 > < 47 > < 46 > < 48 > WAIT (input) < 41 > < 43 > < 42 > < 44 > Remark Broken line indicates high-im
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µPD70F3003A, 70F3025A, 70F3003A(A) (7) Bus hold timing (1/2) Parameter HLDRQ setup time (to CLKOUT↓) Symbol Conditions MIN. MAX.
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µPD70F3003A, 70F3025A, 70F3003A(A) (7) Bus hold timing (2/2) TH TH TH TH TI CLKOUT (output) < 54 > < 54 > < 55 > < 57 > HLDRQ (input) < 56 > < 56 > < 61 > < 62 > HLDAK (output) < 58 > < 60 > < 59 > A16 to A19 (output) Note AD0 to AD15 (I/O) D0 to D15 (input or output) ASTB (output) DSTB (output) R/W (output) Note UBEN (output), LBEN (output) Remark Broken line indicates high-impedance.
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µPD70F3003A, 70F3025A, 70F3003A(A) (8) Interrupt timing Parameter Symbol Conditions MIN. MAX.
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µPD70F3003A, 70F3025A, 70F3003A(A) (9) CSI timing (1/2) (a) Master mode (i) CSI0 to CSI2 timing Parameter Symbol Conditions MIN. MAX. Unit SCKn cycle <67> tCYSK1 Output 120 ns SCKn high-level width <68> tWSKH1 Output 0.5 tCYSK1 – 20 ns SCKn low-level width <69> tWSKL1 Output 0.
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µPD70F3003A, 70F3025A, 70F3003A(A) (9) CSI timing (2/2) (ii) CSI3 timing Parameter Symbol Conditions MIN. MAX. Unit SCK3 cycle <67> tCYSK4 Input 500 ns SCK3 high-level width <68> tWSKH4 Input 180 ns SCK3 low-level width <69> tWSKL4 Input 180 ns SI3 setup time (to SCK3↑) <70> tSSISK4 100 ns SI3 hold time (from SCK3↑) <71> tHSKSI4 50 ns SO3 output delay time (from SCK3↓) <72> tDSKSO4 RL = 1.
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µPD70F3003A, 70F3025A, 70F3003A(A) (10) RPU timing Parameter Symbol Conditions MIN. MAX.
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µPD70F3003A, 70F3025A, 70F3003A(A) A/D Converter Characteristics (TA = –40 to +85°C, VDD = AVDD = 5 V ±10%, VSS = AVSS = 0 V) Parameter Symbol Resolution Overall error Conditions MIN. TYP. MAX. Unit 10 10 10 bit — Note 1 Quantization error 4.5 V ≤ AVREF1 ≤ AVDD ±0.4 %FSR — 3.5 V ≤ AVREF1 ≤ AVDD ±0.7 %FSR ±1/2 LSB — Conversion time tCONV Sampling time tSAMP Zero-scale error Full-scale error — Note 1 Note 1 Non-linearity error Note 1 4.5 V ≤ AVREF1 ≤ AVDD 60 tCYK 3.
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µPD70F3003A, 70F3025A, 70F3003A(A) D/A Converter Characteristics (TA = –40 to +85°C, VDD = AVDD = 5 V ±10%, VSS = AVSS = 0 V) Parameter Symbol Conditions MIN. TYP. MAX. Unit 8 8 8 bit Resolution — Overall error — Load conditions: 2 MΩ, 30 pF AVREF2 = VDD AVREF3 = 0 0.8 % — Load conditions: 2 MΩ, 30 pF AVREF2 = 0.75 VDD AVREF3 = 0.25 VDD 1.0 % — Load conditions: 4 MΩ, 30 pF AVREF2 = VDD AVREF3 = 0 0.6 % — Load conditions: 4 MΩ, 30 pF AVREF2 = 0.75 VDD AVREF3 = 0.25 VDD 0.
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µPD70F3003A, 70F3025A, 70F3003A(A) 3.2 Flash Memory Programming Mode Basic Characteristics (TA = 10 to 40°C (when rewriting), TA = –40 to +85°C (when not rewriting), VDD = AVDD = 5 V ±10%, VSS = AVSS = 0 V)) (1) µPD70F3003A (all ranks), 70F3025A (except K, E, P, X rank) Parameter Symbol Conditions MIN. TYP. MAX. Unit 33 MHz 10.6 V Operating frequency φ VPP supply voltage VPP1 During flash memory programming 9.7 VPPL VPP low-level detection –0.5 0.
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µPD70F3003A, 70F3025A, 70F3003A(A) Cautions 1. V PP pull-down resistance value (RV PP ) is recommended to be in the range 5 kΩ to 15 kΩ. 2. Set the transfer rate between programmer and device as follows. CSI0: 0.2 to 1 MHz UART0: 4,800 to 76,800 bps Remarks 1. When the PG-FP3 is used, a time parameter required for writing/erasing by downloading parameter files is automatically set. Do not change the settings unless otherwise specified. 2.
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µPD70F3003A, 70F3025A, 70F3003A(A) (2) µPD70F3025A (X rank) Parameter Symbol Conditions MIN. TYP. MAX. Unit 33 MHz 10.6 V Operating frequency φ Note 1 10 VPP supply voltage VPP1 During flash memory programming 9.7 VPPL VPP low-level detection –0.5 0.2VDD V VPPM VPP, VDD level detection 0.8VDD 1.2VDD V VPPH VPP high-voltage level detection 10.6 V VDD supply current IDD VPP= VPP1 3.
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µPD70F3003A, 70F3025A, 70F3003A(A) 4. PACKAGE DRAWING 100-PIN PLASTIC LQFP (FINE PITCH) (14x14) A B 75 76 51 50 detail of lead end S C D Q R 26 25 100 1 F G H I J M K P S N S L M NOTE Each lead centerline is located within 0.08 mm of its true position (T.P.) at maximum material condition. ITEM MILLIMETERS A 16.00±0.20 B 14.00±0.20 C 14.00±0.20 D 16.00±0.20 F 1.00 G 1.00 H 0.22 +0.05 −0.04 I J 0.08 0.50 (T.P.) K 1.00±0.20 L 0.50±0.20 M 0.17 +0.03 −0.07 N 0.08 P 1.
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µPD70F3003A, 70F3025A, 70F3003A(A) 5. RECOMMENDED SOLDERING CONDITIONS The µ PD70F3003A, 70F3025A, and 70F3003A(A) should be soldered and mounted under the following recommended conditions. For technical information, see the following website. Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html) Table 5-1.
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µPD70F3003A, 70F3025A, 70F3003A(A) (3) µPD70F3003AGC(A)-33-8EU: 100-pin plastic LQFP (fine pitch) (14 × 14) Soldering Method Infrared reflow Soldering Conditions Package peak temperature: 235°C, Time: 30 seconds max.
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µPD70F3003A, 70F3025A, 70F3003A(A) APPENDIX NOTES ON TARGET SYSTEM DESIGN The following shows a diagram of the connection conditions between the in-circuit emulator option board and conversion connector. Design your system making allowances for conditions such as the form of parts mounted on the target system as shown below. Side view In-circuit emulator IE-703002-MC In-circuit emulator option board IE-703003-MC-EM1 132.
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µPD70F3003A, 70F3025A, 70F3003A(A) NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction.
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µPD70F3003A, 70F3025A, 70F3003A(A) Related document: µ PD703003A, 703004A, 703025A, 703003A(A), 703025A(A) Data Sheet (U13188E) Reference Materials Electrical Characteristics for Microcomputer (U15170JNote) Note This document number is that of Japanese version. The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such.
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µPD70F3003A, 70F3025A, 70F3003A(A) Regional Information Some information contained in this document may vary from country to country. Before using any NEC Electronics product in your application, pIease contact the NEC Electronics office in your country to obtain a list of authorized representatives and distributors.
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µPD70F3003A, 70F3025A, 70F3003A(A) • The information in this document is current as of July, 2005. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information.