Datasheet

Section 3 MCU Operating Modes
Rev.6.00 Sep. 27, 2007 Page 83 of 1268
REJ09B0220-0600
Bit 3
FLSHE Description
0 Flash control registers are not selected for addresses H'FFFFC8 to H'FFFFCB
(Initial value)
1 Flash control registers are not selected for addresses H'FFFFC8 to H'FFFFCB
Bits 2 and 1—Reserved: These bits are always read as 0. Only 0 should be written to these bits.
Bit 0—Reserved: In the H8S/2328B F-ZTAT and H8S/2326 F-ZTAT, this bit is always read as 0
and should only be written with 0. In the H8S/2329B F-ZTAT, this bit is reserved and should only
be written with 0.
3.3 Operating Mode Descriptions
3.3.1 Mode 1
The H8S/2329 does not support mode 1. Do not select the mode 1 setting.
3.3.2 Mode 2 (H8S/2329B F-ZTAT Only)
This is a flash memory boot mode. See section 19, ROM, for details. This is the same as advanced
on-chip ROM enabled expansion mode, except when erasing and reprogramming flash memory.
3.3.3 Mode 3 (H8S/2329B F-ZTAT Only)
This is a flash memory boot mode. See section 19, ROM, for details. This is the same as advanced
single-chip ROM mode, except when erasing and reprogramming flash memory.
3.3.4 Mode 4 (Expanded Mode with On-Chip ROM Disabled)
The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled.
Ports A, B, and C function as an address bus, port D functions as a data bus, and part of port F
carries bus control signals.
The initial bus mode after a reset is 16 bits, with 16-bit access to all areas. However, note that if 8-
bit access is designated by the bus controller for all areas, the bus mode switches to 8 bits.