Datasheet

Section 22 Electrical Characteristics
Rev.6.00 Sep. 27, 2007 Page 959 of 1268
REJ09B0220-0600
(5) Timing of On-Chip Supporting Modules
Table 22.9 Timing of On-Chip Supporting Modules
Condition A: V
CC
= 2.7 V to 3.6 V, AV
CC
= 2.7 V to 3.6 V, V
ref
= 2.7 V to AV
CC
, V
SS
= AV
SS
=
0 V, φ = 2 MHz to 20 MHz, T
a
= –20°C to 75°C (regular specifications),
T
a
= –40°C to 85°C (wide-range specifications)
Condition B: V
CC
= 3.0 V to 3.6 V, AV
CC
= 3.0 V to 3.6 V, V
ref
= 3.0 V to AV
CC
, V
SS
= AV
SS
=
0 V, φ = 2 MHz to 25 MHz, T
a
= –20°C to 75°C (regular specifications),
T
a
= –40°C to 85°C (wide-range specifications)
Condition A Condition B
Test
Item Symbol Min Max Min Max Unit Conditions
I/O ports Output data delay time t
PWD
— 50 — 40 ns Figure 22.20
Input data setup time t
PRS
30 — 25 —
Input data hold time t
PRH
30 — 25 —
PPG Pulse output delay time t
POD
— 50 — 40 ns Figure 22.21
TPU Timer output delay time t
TOCD
— 50 — 40 ns Figure 22.22
Timer input setup time t
TICS
30 — 25 —
Timer clock input setup time t
TCKS
30 — 25 — ns Figure 22.23
Timer clock
pulse width
Single-edge
specification
t
TCKWH
1.5 — 1.5 — t
cyc
Both-edge
specification
t
TCKWL
2.5 — 2.5 —
8-bit timer Timer output delay time t
TMOD
— 50 — 40 ns Figure 22.24
Timer reset input setup time t
TMRS
30 — 25 — ns Figure 22.26
Timer clock input setup time t
TMCS
30 — 25 — ns Figure 22.25
Timer clock
pulse width
Single-edge
specification
t
TMCWH
1.5 — 1.5 — t
cyc
Both-edge
specification
t
TMCWL
2.5 — 2.5 —
WDT Overflow output delay time t
WOVD
— 50 — 40 ns Figure 22.27