To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.
Notice 1. 2. 3. 4. 5. 6. 7. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office.
User’s Manual The revision list can be viewed directly by clicking the title page. The revision list summarizes the locations of revisions and additions. Details should always be checked by referring to the relevant text.
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General Precautions in the Handling of MPU/MCU Products The following usage notes are applicable to all MPU/MCU products from Renesas. For detailed usage notes on the products covered by this manual, refer to the relevant sections of the manual. If the descriptions under General Precautions in the Handling of MPU/MCU Products and in the body of the manual differ from each other, the description in the body of the manual takes precedence. 1.
Rev.6.00 Sep.
Preface This LSI is a single-chip microcomputer made up of the H8S/2000 CPU with an internal 32-bit architecture as its core, and the peripheral functions required to configure a system. This LSI is equipped with ROM, RAM, a bus controller, data transfer controller (DTC), a 16-bit timer pulse unit (TPU), a watchdog timer (WDT), a serial communication interface (SCI), DMA controller (DMAC), a D/A converter, an A/D converter, and I/O ports as on-chip supporting modules.
H8S/2329 Group, H8S/2328 Group Manuals: Document Title Document No. H8S/2329 Group, H8S/2328 Group Hardware Manual This manual H8S/2600 Series, H8S/2000 Series Software Manual REJ09B0139 User’s Manuals for Development Tools: Document Title Document No. H8S, H8S/300 Series C/C++ Compiler, Assembler, Optimized Linkage Editor Compiler Package Ver.6.
Main Revisions for This Edition Item Page 1.3.1 Pin Arrangement 10 Revision (See Manual for Details) Figure amended 73 72 71 RES WDTOVF (FWE P20 / PO0 / TIOCA3 )* Figure 1.3 Mask ROM Versions, F-ZTAT Versions, H8S/2324S, H8S/2322R, H8S/2320 Pin Arrangement (TFP120: Top View) Note amended Note: * The FWE pin applies to the H8S/2328B F-ZTAT and H8S/2326 F-ZTAT only. The WDTOVF pin function is not available in the FZTAT versions.
Item Page 1.3.1 Pin Arrangement 15 Revision (See Manual for Details) Figure added Figure 1.8 HD64F2329B Pin Arrangement (FP128B: Top View) 1.3.3 Pin Functions 26 Table amended Table 1.3 Pin Functions MD0 MD1 0 0 1 — 1 0 Mode 2* 1 Mode 3* 1 1 0 1 6.3.
Item Page Revision (See Manual for Details) 14.2.8 Bit Rate Register (BRR) 618 Table amended φ = 25 MHz Table 14.3 BRR Settings for Various Bit Rates (Asynchronous Mode) 19.4.1 Features 740 Bit Rate (bits/s) n N Error (%) 110 3 110 –0.02 150 3 80 300 2 162 600 2 80 1200 1 162 2400 1 80 4800 0 162 9600 0 80 19200 0 40 –0.76 31250 0 24 1.00 38400 0 19 1.73 0.47 –0.15 0.47 –0.15 0.47 –0.15 0.
Item Page Revision (See Manual for Details) 22.2.6 Flash Memory Characteristics 978 Notes added 7. The minimum number of rewrites after which all characteristics are guaranteed. (The guaranteed range is one to min. rewrites.) Table 22.22 Flash Memory Characteristics 8. Reference value at 25°C. (This is a general indication of the number of rewrites possible under normal conditions.) 9. The data retention characteristics within the specified range, including min. rewrites.
Contents Section 1 Overview............................................................................................1 1.1 1.2 1.3 Overview........................................................................................................................... 1 Block Diagram .................................................................................................................. 8 Pin Description..................................................................................................
2.8.5 Bus-Released State............................................................................................... 72 2.8.6 Power-Down State ............................................................................................... 73 2.9 Basic Timing ..................................................................................................................... 73 2.9.1 Overview..............................................................................................................
4.2 4.3 4.4 4.5 4.6 4.7 4.1.2 Exception Handling Operation............................................................................. 102 4.1.3 Exception Vector Table ....................................................................................... 102 Reset.................................................................................................................................. 104 4.2.1 Overview...............................................................................................
5.6 DTC and DMAC Activation by Interrupt ......................................................................... 139 5.6.1 Overview.............................................................................................................. 139 5.6.2 Block Diagram ..................................................................................................... 140 5.6.3 Operation .............................................................................................................
6.5.7 Precharge State Control ....................................................................................... 187 6.5.8 Wait Control ........................................................................................................ 188 6.5.9 Byte Access Control ............................................................................................ 190 6.5.10 Burst Operation.................................................................................................... 192 6.5.
7.3 7.4 7.5 7.6 7.7 7.2.4 DMA Control Register (DMACR) ...................................................................... 227 7.2.5 DMA Band Control Register (DMABCR) .......................................................... 231 Register Descriptions (2) (Full Address Mode) ................................................................ 237 7.3.1 Memory Address Register (MAR)....................................................................... 237 7.3.2 I/O Address Register (IOAR) ..............
8.3 8.4 8.5 8.2.1 DTC Mode Register A (MRA) ............................................................................ 314 8.2.2 DTC Mode Register B (MRB)............................................................................. 315 8.2.3 DTC Source Address Register (SAR).................................................................. 317 8.2.4 DTC Destination Address Register (DAR).......................................................... 317 8.2.5 DTC Transfer Count Register A (CRA) .............
9.6 9.7 9.8 9.9 9.10 9.11 9.12 9.13 9.5.1 Overview.............................................................................................................. 379 9.5.2 Register Configuration......................................................................................... 380 9.5.3 Pin Functions ....................................................................................................... 380 Port 5...................................................................................
9.14 Port G................................................................................................................................ 435 9.14.1 Overview.............................................................................................................. 435 9.14.2 Register Configuration......................................................................................... 436 9.14.3 Pin Functions ..............................................................................................
10.7 Usage Notes ...................................................................................................................... 521 Section 11 Programmable Pulse Generator (PPG) ............................................531 11.1 Overview........................................................................................................................... 531 11.1.1 Features................................................................................................................ 531 11.
12.3 12.4 12.5 12.6 12.2.5 Timer Control/Status Registers 0 and 1 (TCSR0, TCSR1).................................. 563 12.2.6 Module Stop Control Register (MSTPCR) .......................................................... 566 Operation........................................................................................................................... 567 12.3.1 TCNT Incrementation Timing ............................................................................. 567 12.3.2 Compare Match Timing .
13.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode................ 595 13.5.4 System Reset by WDTOVF Signal...................................................................... 595 13.5.5 Internal Reset in Watchdog Timer Mode............................................................. 596 Section 14 Serial Communication Interface (SCI) ............................................597 14.1 Overview............................................................................................
15.3 Operation........................................................................................................................... 678 15.3.1 Overview.............................................................................................................. 678 15.3.2 Pin Connections ................................................................................................... 678 15.3.3 Data Format ..............................................................................................
17.2.3 Module Stop Control Register (MSTPCR) .......................................................... 728 17.3 Operation........................................................................................................................... 728 Section 18 RAM ................................................................................................731 18.1 Overview........................................................................................................................... 731 18.1.
19.7 Programming/Erasing Flash Memory ............................................................................... 765 19.7.1 Program Mode ..................................................................................................... 765 19.7.2 Program-Verify Mode.......................................................................................... 766 19.7.3 Erase Mode .......................................................................................................... 768 19.7.
19.15 19.16 19.17 19.18 19.19 19.20 19.21 19.22 19.14.5 System Control Register 2 (SYSCR2) ................................................................. 806 19.14.6 RAM Emulation Register (RAMER)................................................................... 807 On-Board Programming Modes........................................................................................ 809 19.15.1 Boot Mode ..................................................................................................
19.23 Register Descriptions ........................................................................................................ 859 19.23.1 Flash Memory Control Register 1 (FLMCR1)..................................................... 859 19.23.2 Flash Memory Control Register 2 (FLMCR2)..................................................... 862 19.23.3 Erase Block Register 1 (EBR1) ........................................................................... 865 19.23.4 Erase Block Registers 2 (EBR2) ......
Section 20 Clock Pulse Generator .....................................................................911 20.1 Overview........................................................................................................................... 911 20.1.1 Block Diagram ..................................................................................................... 911 20.1.2 Register Configuration......................................................................................... 912 20.
22.1.2 DC Characteristics ............................................................................................... 936 22.1.3 AC Characteristics ............................................................................................... 940 22.1.4 A/D Conversion Characteristics........................................................................... 964 22.1.5 D/A Conversion Characteristics........................................................................... 965 22.
C.13 Port G................................................................................................................................ 1255 Appendix D Pin States.......................................................................................1259 D.1 Port States in Each Mode .................................................................................................. 1259 Appendix E Product Lineup ..............................................................................
Section 1 Overview Section 1 Overview 1.1 Overview The H8S/2329 Group and H8S/2328 Group are series of microcomputers (MCUs: microcomputer units), built around the H8S/2000 CPU, employing Renesas’ proprietary architecture, and equipped with supporting functions on-chip. The H8S/2000 CPU has an internal 32-bit architecture, is provided with sixteen 16-bit general registers and a concise, optimized instruction set designed for high-speed operation, and can address a 16-Mbyte linear address space.
Section 1 Overview Table 1.
Section 1 Overview Item Specification Data transfer controller (DTC) • Can be activated by internal interrupt or software • Multiple transfers or multiple types of transfer possible for one activation source • Transfer possible in repeat mode, block transfer mode, etc.
Section 1 Overview Item Specification Memory • Flash memory, mask ROM • High-speed static RAM Product Code ROM RAM H8S/2329B, H8S/2329E 2 H8S/2328* , H8S/2328B 384 kbytes 32 kbytes 256 kbytes 8 kbytes H8S/2327 128 kbytes 8 kbytes H8S/2326 512 kbytes 8 kbytes *1 H8S/2324S — 32 kbytes H8S/2323 32 kbytes 8 kbytes H8S/2322R — 8 kbytes H8S/2321 — 4 kbytes H8S/2320 — 4 kbytes Notes: 1. The on-chip debug function can be used with the E10A emulator (E10A compatible version).
Section 1 Overview Item Specification Operating modes • Eight MCU operating modes (H8S/2328B F-ZTAT, H8S/2326 F-ZTAT) External Data Bus CPU Operating Description Mode Mode On-Chip Initial ROM Value Maximum Value 1 — — — — — 2 3 4 5 Advanced On-chip ROM disabled expansion mode 6 On-chip ROM enabled expansion mode 7 Single-chip mode 8 — — Disabled 16 bits 16 bits 8 bits 16 bits 8 bits 16 bits — — — — — Enabled 8 bits 16 bits — — — — Enabled 9 10 Advanced Boot mode 1
Section 1 Overview Item Specification Operating modes • Four MCU operating modes (ROMless, mask ROM versions, H8S/2329B F-ZTAT) CPU Operating Description Mode Mode 1 1 2* 1 3* 2 4* — — External Data Bus On-Chip Initial ROM Value Maximum Value — — — Advanced On-chip ROM disabled Disabled 16 bits 16 bits expansion mode 2 5* On-chip ROM disabled Disabled 8 bits 16 bits expansion mode 6 On-chip ROM enabled Enabled 8 bits 16 bits expansion mode 7 Single-chip mode Enabled — — Notes: 1.
Section 1 Overview Item Specification Product lineup Condition A Condition B Operating power supply voltage 2.7 to 3.6 V 3.0 to 3.6 V Operating frequency 2 to 20 MHz 2 to 25 MHz Model HD64F2329B — O HD64F2329E* — O HD6432328 O — O O — O HD64F2326 HD6412324S O O HD6432323 O O HD6412322R O O HD6412321 O O HD64F2328B HD6432327 O O HD6412320 O O O: Products in the current lineup Note: * The on-chip debug function can be used with the E10A emulator (E10A compatible version).
Section 1 Overview Port C PC7 /A7 PC6 /A6 PC5 /A5 PC4 /A4 PC3 /A3 PC2 /A2 PC1 /A1 PC0 /A0 Port 3 P35 /SCK1 P34 /SCK0 P33 /RxD1 P32 /RxD0 P31 /TxD1 P30 /TxD0 Port 5 P53 /ADTRG/IRQ7/WAIT/BREQO P52 /SCK2/IRQ6 P51 /RxD2/IRQ5 P50 /TxD2/IRQ4 WDT Port G 8-bit timer SCI TPU D/A converter PPG A/D converter Port 1 Port 2 Port 4 P47 /AN7 /DA1 P46 /AN6 /DA0 P45 /AN5 P44 /AN4 P43 /AN3 P42 /AN2 P41 /AN1 P40 /AN0 Port 6 Vref AVCC AVSS P67 /CS7 /IRQ3 P66 /CS6 /IRQ2 P65 /IRQ1 P64 /IRQ0 P63 /TEND1 P62 /DREQ
Port C PC7 /A7 PC6 /A6 PC5 /A5 PC4 /A4 PC3 /A3 PC2 /A2 PC1 /A1 PC0 /A0 Port 3 P35 /SCK1 P34 /SCK0 P33 /RxD1 P32 /RxD0 P31 /TxD1 P30 /TxD0 Port 5 P53 /ADTRG/IRQ7/WAIT/BREQO P52 /SCK2/IRQ6 P51 /RxD2/IRQ5 P50 /TxD2/IRQ4 WDT Port G 8-bit timer SCI TPU D/A converter PPG A/D converter Port 1 Port 2 Port 4 P47 / AN7 / DA1 P46 / AN6 / DA0 P45 / AN5 P44 / AN4 P43 / AN3 P42 / AN2 P41 / AN1 P40 / AN0 Port 6 Vref AVCC AVSS P67 /CS7 /IRQ3 P66 /CS6 /IRQ2 P65 /IRQ1 P64 /IRQ0 P63 P62 P61 /CS5 P60 /CS4 Por
Pin Description 1.3.1 Pin Arrangement 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 P51 / RxD2/IRQ5 P50 /TxD2/IRQ4 PF0 / BREQ PF1 / BACK PF2 / LCAS/WAIT / BREQO PF3 / LWR PF4 / HWR PF5 / RD PF6 / AS VCC PF7 / φ VSS EXTAL XTAL VCC STBY NMI RES WDTOVF (FWE)* 1.
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 P35 /SCK1 P34 /SCK0 P33 / RxD1 P32 / RxD0 P31 /TxD1 P30 /TxD0 VCC PD7 /D15 PD6 /D14 PD5 /D13 PD4 /D12 VSS PD3 /D11 PD2 /D10 PD1 /D9 PD0 /D8 PE7 /D7 PE6 /D6 PE5 /D5 PE4 /D4 VSS PE3 /D3 PE2 /D2 PE1 /D1 PE0 /D0 VCC PG3 /CS1
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 VCC PC0 /A0 PC1 /A1 PC2 /A2 PC3 /A3 VSS PC4 /A4 PC5 /A5 PC6 /A6 PC7 /A7 PB0 /A8 PB1 /A9 PB2 /A10 PB3 /A11 VSS PB4 /A12 PB5 /A13 PB6 /A14 PB7 /A15 PA0 /A16 PA1 /A17 PA2 /A18 PA3 /A19 VSS PA4 /A20 /IRQ4 PA5 /A21 /IRQ5 PA6 /A22 /I
PG3 /CS1 PG4 /CS0 VSS VSSNC VCC PC0 /A0 PC1 /A1 PC2 /A2 PC3 /A3 VSS PC4 /A4 PC5 /A5 PC6 /A6 PC7 /A7 PB0 /A8 PB1 /A9 PB2 /A10 PB3 /A11 VSS PB4 /A12 PB5 /A13 PB6 /A14 PB7 /A15 PA0 /A16 PA1 /A17 PA2 /A18 PA3 /A19 VSS PA4 /A20 /IRQ4 PA5 /A21 /IRQ5 PA6 /A22 /IRQ6 PA7 /A23 /IRQ7 P67 /CS7/IRQ3 P66 /CS6/IRQ2 VSS VSS P65 /IRQ1 P64 /IRQ0 AVCC Vref P40 / AN0 P41 / AN1 P42 / AN2 P43 / AN3 P44 / AN4 P45 / AN5 P46 / AN6 / DA0 P47 / AN7 / DA1 AVSS VSS P17 / PO15 / TIOCB2 / TCLKD P16 / PO14 / TIOCA2 P15 / PO13 / TIOCB1 /
90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 P51 / RxD2/IRQ5 P50 /TxD2/IRQ4 PF0 / BREQ PF1 / BACK PF2 / LCAS/WAIT / BREQO PF3 / LWR PF4 / HWR PF5 / RD PF6 / AS VCC PF7 / φ VSS EXTAL XTAL VCC STBY NMI RES EMLE P20 /PO0 /TIOCA3 P21 /PO1 /TIOCB3 P22 /PO2 /TIOCC3 / TMRI0 P23 /PO3 /TIOCD3 / TMCI0 P24 /PO4 /TIOCA4 / TMRI1 P25 /PO5 /TIOCB4 / TMCI1 P26 /PO6 /TIOCA5 /TMO0 P27 /PO7 /TIOCB5 /TMO1 P63 / TEND1 P62 / DREQ1 P61 / TEND0 / CS5 Section 1 Overview 60 59 58 57 56
PG3 /CS1 PG4 /CS0 VSS VSSNC VCC PC0 /A0 PC1 /A1 PC2 /A2 PC3 /A3 VSS PC4 /A4 PC5 /A5 PC6 /A6 PC7 /A7 PB0 /A8 PB1 /A9 PB2 /A10 PB3 /A11 VSS PB4 /A12 PB5 /A13 PB6 /A14 PB7 /A15 PA0 /A16 PA1 /A17 PA2 /A18 PA3 /A19 VSS PA4 /A20 /IRQ4 PA5 /A21 /IRQ5 PA6 /A22 /IRQ6 PA7 /A23 /IRQ7 P67 /CS7/IRQ3 P66 /CS6/IRQ2 VSS VSS P65 /IRQ1 P64 /IRQ0 AVCC Vref P40 /AN0 P41 /AN1 P42 /AN2 P43 /AN3 P44 /AN4 P45 /AN5 P46 /AN6 /DA0 P47 /AN7 /DA1 AVSS VSS P17 /PO15 /TIOCB2 / TCLKD P16 /PO14 /TIOCA2 P15 /PO13 /TIOCB1 / TCLKC P14 /PO12
Section 1 Overview P20 /PO0 /TIOCA3 P21 /PO1 /TIOCB3 P22 /PO2 /TIOCC3 / TMRI0 P23 /PO3 /TIOCD3 / TMCI0 P24 /PO4 /TIOCA4 / TMRI1 P25 /PO5 /TIOCB4 / TMCI1 P26 /PO6 /TIOCA5 /TMO0 P27 /PO7 /TIOCB5 /TMO1 P63 /TEND1/TDO * P62 /DREQ1/TDI * P61 /TEND0 /CS5/TCK * 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113
Section 1 Overview 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 P35 /SCK1 P34 /SCK0*/TRST* P33 /RxD1 P32 /RxD0* P31 /TxD1 P30 /TxD0* VCC PD7 /D15 PD6 /D14 PD5 /D13 PD4 /D12 VSS PD3 /D11 PD2 /D10 PD1 /D9 PD0 /D8 PE7 /D7 PE6 /D6 PE5 /D5 PE4 /D4 VSS PE3 /D3 PE2 /D2 PE1
Section 1 Overview 1.3.2 Pin Functions in Each Operating Mode Table 1.2 Pin Functions in Each Operating Mode Pin No.
Section 1 Overview Pin No.
Section 1 Overview Pin No.
Section 1 Overview Pin No.
Section 1 Overview Pin No.
Section 1 Overview Pin No. Pin Name TFP-120 FP-128B Mode 4* Mode 5* Mode 6 Mode 7 Flash Memory Programmer Mode — 3 VSS VSS VSS VSS VSS — 4 1 VSSNC *7 1 VSSNC *7 VSSNC *7 VSSNC *7 NC Notes: 1. Only modes 4 and 5 are provided in the ROMless version. 2. The DREQ0, TEND0, DREQ1, and TEND1 pin functions are not supported in the H8S/2321. 3. The FWE pin applies to the H8S/2328B F-ZTAT and H8S/2326 F-ZTAT only. The EMLE pin applies to the H8S/2329B F-ZTAT only.
Section 1 Overview 1.3.3 Table 1.3 Pin Functions Pin Functions Pin No. Type Symbol TFP-120 FP-128B I/O Name and Function Power VCC 1, 33, 52, 76, 81 5, 39, 58, 84, 89 Input Power supply: For connection to the power supply. All VCC pins should be connected to the system power supply. VSS 6, 15, 24, 38, 47, 59, 79, 104 3, 10, 19, 28, 35, 36, 44, 53, 65, 67, 68, 87, 99, 100, 114 Input Ground: For connection to ground (0 V). All VSS pins should be connected to the system power supply (0 V).
Section 1 Overview Pin No. Type Symbol Operating mode MD2 to control MD0 TFP-120 FP-128B I/O Name and Function 115 to 113 125 to 123 Input Mode pins: These pins set the operating mode. The relation between the settings of pins MD2 to MD0 and the operating mode is shown below. These pins should not be changed while the chip is operating.
Section 1 Overview Pin No. Type Symbol Operating mode MD2 to control MD0 TFP-120 FP-128B I/O Name and Function 115 to 113 125 to 123 Input Mask ROM and ROMless versions, H8S/2329B F-ZTAT: MD2 MD1 MD0 Operating Mode 0 0 1 — 1 0 Mode 2* 1 Mode 3* 1 1 0 1 1 2 1 Mode 4* 2 Mode 5* 0 Mode 6 1 Mode 7 0 Notes: 1. Applies to the H8S/2329B F-ZTAT only. 2. The ROMless versions can use only modes 4 and 5.
Section 1 Overview Pin No. Type Symbol TFP-120 FP-128B I/O Name and Function System control 1 FWE* 72 80 Input Flash write enable: Enables/ disables flash memory programming. EMLE* 72 80 Input Emulator enable: For connection to the power supply (0 V) NMI 74 82 Input Nonmaskable interrupt: Requests a nonmaskable interrupt. When this pin is not used, it should be fixed high.
Section 1 Overview Pin No. Type Symbol TFP-120 FP-128B I/O Bus control 4 CAS* 116 126 Output Upper column address strobe/ column address strobe: The 2-CAS type DRAM upper column address strobe signal. LCAS* 86 94 Output Lower column address strobe: The 2-CAS type DRAM lower column address strobe signal. WAIT 86, 92 94, 102 Input Wait: Requests insertion of a wait state in the bus cycle when accessing external 3-state access space.
Section 1 Overview Pin No. Type Symbol TFP-120 FP-128B I/O Name and Function 16-bit timer pulse unit (TPU) TIOCA4, TIOCB4 67, 66 75, 74 I/O Input capture/output compare match A4 and B4: The TGR4A and TGR4B input capture input or output compare output, or PWM output pins. TIOCA5, TIOCB5 65, 64 73, 72 I/O Input capture/output compare match A5 and B5: The TGR5A and TGR5B input capture input or output compare output, or PWM output pins.
Section 1 Overview Pin No. Type Symbol TFP-120 FP-128B I/O Name and Function A/D converter and D/A converter AVCC 93 103 Input This is the power supply pin for the A/D converter and D/A converter. When the A/D converter and D/A converter are not used, this pin should be connected to the system power supply (+3 V). AVSS 103 113 Input This is the ground pin for the A/D converter and D/A converter. This pin should be connected to the system power supply (0 V).
Section 1 Overview Pin No. Type Symbol TFP-120 FP-128B I/O Name and Function I/O ports P67 to P60 29 to 32, 63 to 60 33, 34, 37, 38, 71 to 69, 66 I/O Port 6: An 8-bit I/O port. Input or output can be designated for each bit by means of the port 6 data direction register (P6DDR).
Section 1 Overview Rev.6.00 Sep.
Section 2 CPU Section 2 CPU 2.1 Overview The H8S/2000 CPU is a high-speed central processing unit with an internal 32-bit architecture that is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2000 CPU has sixteen 16-bit general registers, can address a 16-Mbyte (architecturally 4-Gbyte) linear address space, and is ideal for realtime control. 2.1.1 Features The H8S/2000 CPU has the following features.
Section 2 CPU • High-speed operation ⎯ All frequently-used instructions execute in one or two states ⎯ Maximum clock rate: 25 MHz ⎯ 8/16/32-bit register-register add/subtract: 40 ns ⎯ 8 × 8-bit register-register multiply: 480 ns ⎯ 16 ÷ 8-bit register-register divide: 480 ns ⎯ 16 × 16-bit register-register multiply: 800 ns ⎯ 32 ÷ 16-bit register-register divide: 800 ns • CPU operating mode ⎯ Advanced mode • Power-down state ⎯ Transition to power-down state by SLEEP instruction ⎯ CPU clock speed se
Section 2 CPU 2.1.3 Differences from H8/300 CPU In comparison to the H8/300 CPU, the H8S/2000 CPU has the following enhancements. • More general registers and control registers ⎯ Eight 16-bit expanded registers, and one 8-bit control register, have been added. • Expanded address space ⎯ Advanced mode supports a maximum 16-Mbyte address space. • Enhanced addressing ⎯ The addressing modes have been enhanced to make effective use of the 16-Mbyte address space.
Section 2 CPU 2.2 CPU Operating Modes The H8S/2329 and H8S/2328 Group CPU has advanced operating mode. Advanced mode supports a maximum 16-Mbyte total address space (architecturally a maximum 16-Mbyte program area and a maximum of 4 Gbytes for program and data areas combined). The mode is selected by the mode pins of the microcontroller.
Section 2 CPU Exception Vector Table and Memory Indirect Branch Addresses: In advanced mode the top area starting at H'00000000 is allocated to the exception vector table in units of 32 bits. In each 32 bits, the upper 8 bits are ignored and a branch address is stored in the lower 24 bits (figure 2.1). For details of the exception vector table, see section 4, Exception Handling.
Section 2 CPU Stack Structure: In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine call, and the PC, condition-code register (CCR), and extended control register (EXR) are pushed onto the stack in exception handling, they are stored as shown in figure 2.2. When EXR is invalid, it is not pushed onto the stack. For details, see section 4, Exception Handling.
Section 2 CPU 2.3 Address Space Figure 2.3 shows a memory map of the H8S/2000 CPU. The H8S/2000 CPU provides linear access to a maximum 16-Mbyte (architecturally 4-Gbyte) address space in advanced mode. H'00000000 Program area H'00FFFFFF Data area Cannot be used by the H8S/2329 and H8S/2328 Group H'FFFFFFFF Advanced Mode Figure 2.3 Memory Map Rev.6.00 Sep.
Section 2 CPU 2.4 Register Configuration 2.4.1 Overview The CPU has the internal registers shown in figure 2.4. There are two types of registers: general registers and control registers.
Section 2 CPU 2.4.2 General Registers The CPU has eight 32-bit general registers. These general registers are all functionally alike and can be used as both address registers and data registers. When a general register is used as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. When the general registers are used as 32-bit registers or address registers, they are designated by the letters ER (ER0 to ER7).
Section 2 CPU Free area SP (ER7) Stack area Figure 2.6 Stack 2.4.3 Control Registers The control registers are the 24-bit program counter (PC), 8-bit extended control register (EXR), and 8-bit condition-code register (CCR). (1) Program Counter (PC) This 24-bit counter indicates the address of the next instruction the CPU will execute. The length of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored.
Section 2 CPU (3) Condition-Code Register (CCR) This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags. Bit 7—Interrupt Mask Bit (I): Masks interrupts other than NMI when set to 1. (NMI is accepted regardless of the I bit setting.) The I bit is set to 1 by hardware at the start of an exceptionhandling sequence. For details, refer to section 5, Interrupt Controller.
Section 2 CPU Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch (Bcc) instructions. 2.4.4 Initial Register Values Reset exception handling loads the CPU's program counter (PC) from the vector table, clears the trace bit in EXR to 0, and sets the interrupt mask bits in CCR and EXR to 1. The other CCR bits and the general registers are not initialized.
Section 2 CPU 2.5.1 General Register Data Formats Figure 2.7 shows the data formats in general registers. Data Type Register Number Data Format 1-bit data RnH 7 0 7 6 5 4 3 2 1 0 Don’t care Don’t care 7 0 7 6 5 4 3 2 1 0 1-bit data 4-bit BCD data RnL RnH 4 3 7 Upper 4-bit BCD data 0 Lower Don’t care RnL Byte data RnH 4 3 7 Upper Don’t care 7 0 Lower 0 Don’t care MSB Byte data LSB RnL 7 0 Don’t care MSB LSB Figure 2.7 General Register Data Formats Rev.6.00 Sep.
Section 2 CPU Data Type Register Number Word data Rn Word data En Data Format 15 0 MSB 15 LSB 0 MSB LSB Longword data ERn 31 16 15 En MSB 0 Rn Legend: ERn: En: Rn: RnH: RnL: MSB: LSB: General register ER General register E General register R General register RH General register RL Most significant bit Least significant bit Figure 2.7 General Register Data Formats (cont) Rev.6.00 Sep.
Section 2 CPU 2.5.2 Memory Data Formats Figure 2.8 shows the data formats in memory. The CPU can access word data and longword data in memory, but word or longword data must begin at an even address. If an attempt is made to access word or longword data at an odd address, no address error occurs but the least significant bit of the address is regarded as 0, so the access starts at the preceding address. This also applies to instruction fetches.
Section 2 CPU 2.6 Instruction Set 2.6.1 Overview The H8S/2000 CPU has 65 types of instructions. The instructions are classified by function in table 2.1. Table 2.
Section 2 CPU 2.6.2 Instructions and Addressing Modes Table 2.2 indicates the combinations of instructions and addressing modes that the H8S/2600 CPU can use. Table 2.
Section 2 CPU 2.6.3 Table of Instructions Classified by Function Table 2.3 summarizes the instructions in each functional category. The notation used in table 2.3 is defined below.
Section 2 CPU Table 2.3 Instructions Classified by Function 1 Type Instruction Size* Function Data transfer MOV B/W/L (EAs) → Rd, Rs → (Ead) Moves data between two general registers or between a general register and memory, or moves immediate data to a general register. MOVFPE B Cannot be used in the H8S/2329 Group and H8S/2328 Group. MOVTPE B Cannot be used in the H8S/2329 Group and H8S/2328 Group. POP W/L @SP+ → Rn Pops a register from the stack. POP.W Rn is identical to MOV.W @SP+, Rn.
Section 2 CPU 1 Type Instruction Size* Function Arithmetic operations ADD SUB B/W/L Rd ± Rs → Rd, Rd ± #IMM → Rd Performs addition or subtraction on data in two general registers, or on immediate data and data in a general register. (Immediate byte data cannot be subtracted from byte data in a general register. Use the SUBX or ADD instruction.
Section 2 CPU 1 Type Instruction Size* Function Arithmetic operations DIVXS B/W Rd ÷ Rs → Rd Performs signed division on data in two general registers: either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or 32 bits ÷ 16 bits → 16-bit quotient and 16bit remainder. CMP B/W/L Rd – Rs, Rd – #IMM Compares data in a general register with data in another general register or with immediate data, and sets CCR bits according to the result.
Section 2 CPU 1 Type Instruction Size* Function Logic operations AND B/W/L Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd Performs a logical AND operation on a general register and another general register or immediate data. OR B/W/L Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd Performs a logical OR operation on a general register and another general register or immediate data. XOR B/W/L Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd Performs a logical exclusive OR operation on a general register and another general register or immediate data.
Section 2 CPU 1 Type Instruction Size* Function Bitmanipulation instructions BSET B 1 → ( of ) Sets a specified bit in a general register or memory operand to 1. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BCLR B 0 → ( of ) Clears a specified bit in a general register or memory operand to 0. The bit number is specified by 3-bit immediate data or the lower three bits of a general register. BNOT B ¬ (
Section 2 CPU 1 Type Instruction Size* Function Bitmanipulation instructions BXOR B C ⊕ ( of ) → C Exclusive-ORs the carry flag with a specified bit in a general register or memory operand and stores the result in the carry flag. BIXOR B C ⊕ ¬ ( of ) → C Exclusive-ORs the carry flag with the inverse of a specified bit in a general register or memory operand and stores the result in the carry flag. The bit number is specified by 3-bit immediate data. BLD B (
Section 2 CPU 1 Type Instruction Size* Function Branch instructions Bcc — Branches to a specified address if a specified condition is true. The branching conditions are listed below.
Section 2 CPU Type Instruction System control TRAPA instructions RTE 1 Size* Function — Starts trap-instruction exception handling. — Returns from an exception-handling routine. SLEEP — Causes a transition to a power-down state. LDC B/W (EAs) → CCR, (EAs) → EXR Moves the source operand contents or immediate data to CCR or EXR. Although CCR and EXR are 8-bit registers, word-size transfers are performed between them and memory. The upper 8 bits are valid.
Section 2 CPU 1 Type Instruction Size* Function Block data transfer instruction EEPMOV.B — if R4L ≠ 0 then Repeat @ER5+ → @ER6+ R4L–1 → R4L Until R4L = 0 else next; EEPMOV.W — if R4 ≠ 0 then Repeat @ER5+ → @ER6+ R4–1 → R4 Until R4 = 0 else next; Transfers a data block according to parameters set in general registers R4L or R4, ER5, and ER6.
Section 2 CPU 2.6.4 Basic Instruction Formats The CPU instructions consist of 2-byte (1-word) units. An instruction consists of an operation field (op field), a register field (r field), an effective address extension (EA field), and a condition field (cc). Figure 2.9 shows examples of instruction formats. (1) Operation field only op NOP, RTS, etc. (2) Operation field and register fields op rm rn ADD.B Rn, Rm, etc.
Section 2 CPU 2.7 Addressing Modes and Effective Address Calculation 2.7.1 Addressing Mode The CPU supports the eight addressing modes listed in table 2.4. Each instruction uses a subset of these addressing modes. Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer instructions can use all addressing modes except program-counter relative and memory indirect.
Section 2 CPU (4) Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn: • Register indirect with post-increment—@ERn+ The register field of the instruction code specifies an address register (ERn) which contains the address of a memory operand. After the operand is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the address register. The value added is 1 for byte access, 2 for word transfer instruction, or 4 for longword transfer instruction.
Section 2 CPU (6) Immediate—#xx:8, #xx:16, or #xx:32: The instruction contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as an operand. The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a vector address.
Section 2 CPU If an odd address is specified in word or longword memory access, or as a branch address, the least significant bit is regarded as 0, causing data to be accessed or instruction code to be fetched at the address preceding the specified address. (For further information, see section 2.5.2, Memory Data Formats.) 2.7.2 Effective Address Calculation Table 2.6 indicates how effective addresses are calculated in each addressing mode. Rev.6.00 Sep.
4 3 rm rn r r disp • r op r Register indirect with pre-decrement @-DERn op Register indirect with post-increment or pre-decrement • Register indirect with post-increment @ERn+ op Register indirect with displacement @(d:16, ERn) or @(d:32, ERn) op Register indirect (@ERn) op Register direct (Rn) Addressing Mode and Instruction Format disp 1 2 4 0 1, 2, or 4 General register contents Byte Word Longword 0 0 0 0 1, 2, or 4 General register contents Sign extension General registe
Rev.6.00 Sep. 27, 2007 Page 66 of 1268 REJ09B0220-0600 6 op op abs abs abs op IMM Immediate #xx:8/#xx:16/#xx:32 @aa:32 op @aa:24 @aa:16 op abs Absolute address 5 @aa:8 Addressing Mode and Instruction Format No. Effective Address Calculation 24 23 24 23 24 23 24 23 87 16 15 Sign extension H'FFFF Operand is immediate data.
8 7 No. op abs • Advanced mode Memory indirect @@aa:8 op @(d:8, PC)/@(d:16, PC) Program-counter relative disp Addressing Mode and Instruction Format 31 31 Memory contents H'000000 87 disp PC contents Sign extension 23 23 abs Effective Address Calculation 0 0 0 0 24 23 24 23 Don’t care 31 Don’t care 31 Effective Address (EA) 0 0 Section 2 CPU Rev.6.00 Sep.
Section 2 CPU 2.8 Processing States 2.8.1 Overview The CPU has five main processing states: the reset state, exception handling state, program execution state, bus-released state, and power-down state. Figure 2.11 shows a diagram of the processing states. Figure 2.12 indicates the state transitions. Reset state The CPU and all on-chip supporting modules have been initialized and are stopped.
Section 2 CPU End of bus request Bus request Program execution state End of bus request Bus request SLEEP instruction with SSBY = 1 Bus-released state End of exception handling SLEEP instruction with SSBY = 0 Request for exception handling Sleep mode Interrupt request Exception-handling state External interrupt Software standby mode RES = high Reset state*1 STBY = high, RES = low Hardware standby mode*2 Power-down state Notes: 1.
Section 2 CPU 2.8.3 Exception-Handling State The exception-handling state is a transient state that occurs when the CPU alters the normal processing flow due to a reset, interrupt, or trap instruction. The CPU fetches a start address (vector) from the exception vector table and branches to that address. (1) Types of Exception Handling and Their Priority Exception handling is performed for traces, resets, interrupts, and trap instructions. Table 2.
Section 2 CPU (2) Reset Exception Handling After the RES pin has gone low and the reset state has been entered, when RES goes high again, reset exception handling starts. When reset exception handling starts the CPU fetches a start address (vector) from the exception vector table and starts program execution from that address. All interrupts, including NMI, are disabled during reset exception handling and after it ends. (3) Traces Traces are enabled only in interrupt control mode 2.
Section 2 CPU Advanced mode SP SP EXR Reserved* CCR CCR PC (24 bits) PC (24 bits) (c) Interrupt control mode 0 (d) Interrupt control mode 2 Note: * Ignored when returning. Figure 2.13 Stack Structure after Exception Handling (Examples) 2.8.4 Program Execution State In this state the CPU executes program instructions in sequence. 2.8.5 Bus-Released State This is a state in which the bus has been released in response to a bus request from a bus master other than the CPU.
Section 2 CPU 2.8.6 Power-Down State The power-down state includes both modes in which the CPU stops operating and modes in which the CPU does not stop. There are three modes in which the CPU stops operating: sleep mode, software standby mode, and hardware standby mode. There are also two other power-down modes: medium-speed mode, and module stop mode. In medium-speed mode the CPU and other bus masters operate on a medium-speed clock.
Section 2 CPU Bus cycle T1 φ Internal address bus Address Internal read signal Read access Internal data bus Read data Internal write signal Write access Internal data bus Write data Figure 2.14 On-Chip Memory Access Cycle Bus cycle T1 φ Address bus Unchanged AS High RD High HWR, LWR High Data bus High-impedance state Figure 2.15 Pin States during On-Chip Memory Access Rev.6.00 Sep.
Section 2 CPU 2.9.3 On-Chip Supporting Module Access Timing The on-chip supporting modules are accessed in two states. The data bus is either 8 bits or 16 bits wide, depending on the particular internal I/O register being accessed. Figure 2.16 shows the access timing for the on-chip supporting modules. Figure 2.17 shows the pin states.
Section 2 CPU Bus cycle T1 T2 φ Address bus Unchanged AS High RD High HWR, LWR High Data bus High-impedance state Figure 2.17 Pin States during On-Chip Supporting Module Access 2.9.4 External Address Space Access Timing The external address space is accessed with an 8-bit or 16-bit data bus width in a two-state or three-state bus cycle. In three-state access, wait states can be inserted. For further details, refer to section 6, Bus Controller. 2.10 Usage Note 2.10.
Section 3 MCU Operating Modes Section 3 MCU Operating Modes 3.1 Overview 3.1.1 Operating Mode Selection (H8S/2328B F-ZTAT, H8S/2326 F-ZTAT) The H8S/2328B F-ZTAT and H8S/2326 F-ZTAT have eight operating modes (modes 4 to 7, 10, 11, 14 and 15). These modes are determined by the mode pin (MD2 to MD0) and flash write enable pin (FWE) settings. The CPU operating mode and initial bus width can be selected as shown in table 3.1. Table 3.1 lists the MCU operating modes. Table 3.
Section 3 MCU Operating Modes The CPU's architecture allows for 4 Gbytes of address space, but the H8S/2328B F-ZTAT and H8S/2326 F-ZTAT actually accesses a maximum of 16 Mbytes. Modes 4 to 6 are externally expanded modes that allow access to external memory and peripheral devices. The external expansion modes allow switching between 8-bit and 16-bit bus modes. After program execution starts, an 8-bit or 16-bit address space can be set for each area, depending on the bus controller setting.
Section 3 MCU Operating Modes Table 3.2 MCU Operating Mode Selection (Mask ROM and ROMless Versions, H8S/2329B F-ZTAT) External Data Bus MCU CPU Operating Operating MD2 MD1 MD0 Mode Description Mode On-Chip Initial ROM Value Max.
Section 3 MCU Operating Modes 3.1.3 Register Configuration The H8S/2329 Group and H8S/2328 Group have a mode control register (MDCR) that indicates the inputs at the mode pins (MD2 to MD0), and a system control register (SYSCR) and a system control register 2 (SYSCR2)*2 that control the operation of the chip. Table 3.3 summarizes these registers. Table 3.
Section 3 MCU Operating Modes 3.2.2 System Control Register (SYSCR) Bit : 7 6 5 4 3 — — INTM1 INTM0 NMIEG 0 0 0 0 0 0 0 1 R/W — R/W R/W R/W R/W R/W R/W Initial value : R/W : 2 1 0 LWROD IRQPAS RAME Bit 7—Reserved: Only 0 should be written to this bit. Bit 6—Reserved: This bit is always read as 0, and cannot be modified. Bits 5 and 4—Interrupt Control Mode 1 and 0 (INTM1, INTM0): These bits select the control mode of the interrupt controller.
Section 3 MCU Operating Modes Bit 1—IRQ Port Switching Select (IRQPAS): Selects switching of input pins for IRQ4 to IRQ7. IRQ4 to IRQ7 input is always performed from one of the ports. Bit 1 IRQPAS Description 0 PA4 to PA7 are used for IRQ4 to IRQ7 input 1 P50 to P53 are used for IRQ4 to IRQ7 input (Initial value) Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is initialized when the reset state is released. It is not initialized in software standby mode.
Section 3 MCU Operating Modes Bit 3 FLSHE Description 0 Flash control registers are not selected for addresses H'FFFFC8 to H'FFFFCB (Initial value) 1 Flash control registers are not selected for addresses H'FFFFC8 to H'FFFFCB Bits 2 and 1—Reserved: These bits are always read as 0. Only 0 should be written to these bits. Bit 0—Reserved: In the H8S/2328B F-ZTAT and H8S/2326 F-ZTAT, this bit is always read as 0 and should only be written with 0.
Section 3 MCU Operating Modes 3.3.5 Mode 5 (Expanded Mode with On-Chip ROM Disabled) The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled. Ports A, B, and C function as an address bus, port D functions as a data bus, and part of port F carries bus control signals. The initial bus mode after a reset is 8 bits, with 8-bit access to all areas.
Section 3 MCU Operating Modes 3.3.10 Mode 11 (H8S/2328B F-ZTAT and H8S/2326 F-ZTAT Only) This is a flash memory boot mode. For details, see section 19, ROM. Except for the fact that flash memory programming and erasing can be performed, operation in this mode is the same as in advanced single-chip mode. 3.3.11 Modes 12 and 13 Modes 12 and 13 are not supported and must not be set. 3.3.12 Mode 14 (H8S/2328B F-ZTAT and H8S/2326 F-ZTAT Only) This is a flash memory user program mode.
Section 3 MCU Operating Modes Table 3.
Section 3 MCU Operating Modes Mode 2 Boot Mode (advanced expanded mode with on-chip ROM enabled) H'000000 Mode 3 Boot Mode (advanced single-chip mode) H'000000 On-chip ROM H'010000 On-chip ROM H'010000 On-chip ROM/ external address space*1 H'060000 Reseved area*4 H'080000 External address space H'FF7400 Reseved area*4 H'FF7C00 On-chip ROM/ reserved area*2 *5 H'060000 H'07FFFF Reseved area*4 H'FF7400 Reseved area*4 H'FF7C00 On-chip RAM*3 On-chip RAM H'FFFBFF H'FFFC00 H'FFFE50 H'FFFF08 H
Section 3 MCU Operating Modes Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 Mode 6 (advanced expanded mode with on-chip ROM enabled) H'000000 Mode 7 (advanced single-chip mode) H'000000 On-chip ROM H'010000 H'080000 H'FF7400 Reseved area*4 H'010000 On-chip ROM/ external address space*1 External address space H'060000 H'060000 Reseved area*4 External address space H'080000 External address space Reseved area*4 H'FF7400 Reseved area*4 H'FF7C00 On-chip ROM H'F
Section 3 MCU Operating Modes Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 Mode 6 (advanced expanded mode with on-chip ROM enabled) H'000000 Mode 7 (advanced single-chip mode) H'000000 On-chip ROM External address space H'010000 On-chip ROM H'010000 On-chip ROM/ external address space*1 On-chip ROM/ reserved area*2 *4 H'03FFFF H'040000 H'FFDC00 External address space H'FFDC00 On-chip RAM*3 H'FFDC00 On-chip RAM*3 On-chip RAM H'FFFBFF H'FFFC00 External address s
Section 3 MCU Operating Modes Mode 10 Boot Mode (advanced expanded mode with on-chip ROM enabled) H'000000 Mode 11 Boot Mode (advanced single-chip mode) H'000000 On-chip ROM On-chip ROM H'010000 H'010000 On-chip ROM/ external address space*1 On-chip ROM/ reserved area*2 *4 H'03FFFF H'040000 External address space H'FFDC00 H'FFDC00 On-chip RAM*3 On-chip RAM*3 H'FFFBFF H'FFFC00 External address space H'FFFE50 Internal I/O registers H'FFFF08 External address space H'FFFF28 Internal I/O registers
Section 3 MCU Operating Modes Mode 14 User Program Mode (advanced expanded mode with on-chip ROM enabled) Mode 15 User Program Mode (advanced single-chip mode) H'000000 H'000000 On-chip ROM On-chip ROM H'010000 H'010000 On-chip ROM/ external address space*1 On-chip ROM/ reserved area*2 *4 H'03FFFF H'040000 External address space H'FFDC00 H'FFDC00 On-chip RAM*3 On-chip RAM*3 H'FFFBFF H'FFFC00 External address space H'FFFE50 Internal I/O registers H'FFFF08 External address space H'FFFF28 Inter
Section 3 MCU Operating Modes Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 Mode 6 (advanced expanded mode with on-chip ROM enabled) H'000000 Mode 7 (advanced single-chip mode) H'000000 On-chip ROM External address space H'010000 On-chip ROM H'010000 Reserved area*5/ on-chip ROM*3 External address space/on-chip ROM*1 H'020000 H'020000 External address space/reserved area*2 *5 Reserved area*5 H'03FFFF H'040000 H'FFDC00 External address space H'FFDC00 On-chip RAM*4
Section 3 MCU Operating Modes Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 Mode 6 (advanced expanded mode with on-chip ROM enabled) H'000000 Mode 7 (advanced single-chip mode) H'000000 On-chip ROM External address space H'010000 On-chip ROM H'010000 On-chip ROM/ external address space*1 On-chip ROM/ reserved area*2 *4 H'07FFFF H'080000 H'FFDC00 External address space H'FFDC00 On-chip RAM*3 H'FFDC00 On-chip RAM*3 On-chip RAM H'FFFBFF H'FFFC00 External address s
Section 3 MCU Operating Modes Mode 10 Boot Mode (advanced expanded mode with on-chip ROM enabled) H'000000 Mode 11 Boot Mode (advanced single-chip mode) H'000000 On-chip ROM On-chip ROM H'010000 H'010000 On-chip ROM/ external address space*1 On-chip ROM/ reserved area*2 *4 H'07FFFF H'080000 External address space H'FFDC00 H'FFDC00 On-chip RAM*3 On-chip RAM*3 H'FFFBFF H'FFFC00 External address space H'FFFE50 Internal I/O registers H'FFFF08 External address space H'FFFF28 Internal I/O registers
Section 3 MCU Operating Modes Mode 14 User Program Mode (advanced expanded mode with on-chip ROM enabled) Mode 15 User Program Mode (advanced single-chip mode) H'000000 H'000000 On-chip ROM On-chip ROM H'010000 H'010000 On-chip ROM/ external address space*1 On-chip ROM/ reserved area*2 *4 H'07FFFF H'080000 External address space H'FFDC00 H'FFDC00 On-chip RAM*3 On-chip RAM*3 H'FFFBFF H'FFFC00 External address space H'FFFE50 Internal I/O registers H'FFFF08 External address space H'FFFF28 Inter
Section 3 MCU Operating Modes Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 External address space H'FF7C00 On-chip RAM* H'FFFC00 External address space H'FFFE50 Internal I/O registers H'FFFF08 External address space H'FFFF28 Internal I/O registers H'FFFFFF Note: * External addresses can be accessed by clearing the RAME bit in SYSCR to 0. Figure 3.5 H8S/2324S Memory Map in Each Operating Mode Rev.6.00 Sep.
Section 3 MCU Operating Modes Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 Mode 6 (advanced expanded mode with on-chip ROM enabled) H'000000 Mode 7 (advanced single-chip mode) H'000000 On-chip ROM H'008000 On-chip ROM H'008000 Reserved area*3 External address space H'010000 Reserved area*3 H'010000 External address space/reserved area*1 *3 Reserved area*3 H'03FFFF H'040000 H'FFDC00 External address space H'FFDC00 On-chip RAM*2 H'FFDC00 On-chip RAM*2 On-chip
Section 3 MCU Operating Modes Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 External address space H'FFDC00 On-chip RAM* H'FFFC00 External address space H'FFFE50 Internal I/O registers H'FFFF08 External address space H'FFFF28 Internal I/O registers H'FFFFFF Note: * External addresses can be accessed by clearing the RAME bit in SYSCR to 0. Figure 3.7 H8S/2322R Memory Map in Each Operating Mode Rev.6.00 Sep.
Section 3 MCU Operating Modes Modes 4 and 5 (advanced expanded modes with on-chip ROM disabled) H'000000 External address space H'FFDC00 H'FFEC00 Reserved area On-chip RAM* H'FFFC00 External address space H'FFFE50 Internal I/O registers H'FFFF08 External address space H'FFFF28 Internal I/O registers H'FFFFFF Note: * External addresses can be accessed by clearing the RAME bit in SYSCR to 0. Figure 3.8 H8S/2320 and H8S/2321 Memory Map in Each Operating Mode Rev.6.00 Sep.
Section 3 MCU Operating Modes Rev.6.00 Sep.
Section 4 Exception Handling Section 4 Exception Handling 4.1 Overview 4.1.1 Exception Handling Types and Priority As table 4.1 indicates, exception handling may be caused by a reset, trap instruction, or interrupt. Exception handling is prioritized as shown in table 4.1. If two or more exceptions occur simultaneously, they are accepted and processed in order of priority. Trap instruction exceptions are accepted at all times in the program execution state.
Section 4 Exception Handling 4.1.2 Exception Handling Operation Exceptions originate from various sources. Trap instructions and interrupts are handled as follows: 1. The program counter (PC), condition code register (CCR), and extend register (EXR) are pushed onto the stack. 2. The interrupt mask bits are updated. The T bit is cleared to 0. 3. A vector address corresponding to the exception source is generated, and program execution starts from that address.
Section 4 Exception Handling Table 4.
Section 4 Exception Handling 4.2 Reset 4.2.1 Overview A reset has the highest exception priority. When the RES pin goes low, all processing halts and the chip enters the reset state. A reset initializes the internal state of the CPU and the registers of on-chip supporting modules. Immediately after a reset, interrupt control mode 0 is set. Reset exception handling begins when the RES pin changes from low to high. A reset can also be caused by watchdog timer overflow.
Section 4 Exception Handling Vector fetch φ Internal Prefetch of first processing program instruction * * * (1) (3) (5) RES Address bus RD High HWR, LWR (2) D15 to D0 (1), (3) (2), (4) (5) (6) (4) (6) Reset exception handling vector address ((1) = H'000000, (3) = H'000002) Start address (contents of reset exception vector address) Start address ((5) = (2), (4)) First program instruction Note: * 3 program wait states are inserted. Figure 4.2 Reset Sequence (Mode 4) 4.2.
Section 4 Exception Handling 4.3 Traces Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control mode 0, irrespective of the state of the T bit. For details of interrupt control modes, see section 5, Interrupt Controller. If the T bit in EXR is set to 1, trace mode is activated. In trace mode, a trace exception occurs on completion of each instruction. Trace mode is canceled by clearing the T bit in EXR to 0. It is not affected by interrupt masking. Table 4.
Section 4 Exception Handling 4.4 Interrupts Interrupt exception handling can be requested by nine external sources (NMI, IRQ7 to IRQ0) and 52 internal sources in the on-chip supporting modules. Figure 4.3 classifies the interrupt sources and the number of interrupts of each type.
Section 4 Exception Handling 4.5 Trap Instruction Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction exception handling can be executed at all times in the program execution state. The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector number from 0 to 3, as specified in the instruction code. Table 4.4 shows the status of CCR and EXR after execution of trap instruction exception handling. Table 4.
Section 4 Exception Handling 4.7 Notes on Use of the Stack When accessing word data or longword data, the chip assumes that the lowest address bit is 0. The stack should always be accessed by word transfer instruction or longword transfer instruction, and the value of the stack pointer (SP, ER7) should always be kept even. Use the following instructions to save registers: PUSH.W Rn (or MOV.W Rn, @-SP) PUSH.L ERn (or MOV.L ERn, @-SP) Use the following instructions to restore registers: POP.
Section 4 Exception Handling Rev.6.00 Sep.
Section 5 Interrupt Controller Section 5 Interrupt Controller 5.1 Overview 5.1.1 Features The chip controls interrupts by means of an interrupt controller. The interrupt controller has the following features. This chapter assumes the maximum number of interrupt sources available in these series—nine external interrupts and 52 internal interrupts.
Section 5 Interrupt Controller 5.1.2 Block Diagram A block diagram of the interrupt controller is shown in figure 5.1.
Section 5 Interrupt Controller 5.1.3 Pin Configuration Table 5.1 summarizes the pins of the interrupt controller. Table 5.1 Interrupt Controller Pins Name Symbol I/O Function Nonmaskable interrupt NMI Input Nonmaskable external interrupt; rising or falling edge can be selected External interrupt requests 7 to 0 IRQ7 to IRQ0 Input 5.1.4 Maskable external interrupts; rising, falling, or both edges, or level sensing, can be selected Register Configuration Table 5.
Section 5 Interrupt Controller 5.2 Register Descriptions 5.2.1 System Control Register (SYSCR) Bit : Initial value : R/W : 7 6 5 4 3 — — INTM1 INTM0 NMIEG 2 1 0 LWROD IRQPAS RAME 0 0 0 0 0 0 0 1 R/W — R/W R/W R/W R/W R/W R/W SYSCR is an 8-bit readable/writable register that selects the interrupt control mode, and the detected edge for NMI. Only bits 5 to 3 are described here; for details of the other bits, see section 3, MCU Operating Modes.
Section 5 Interrupt Controller 5.2.2 Bit Interrupt Priority Registers A to K (IPRA to IPRK) : 7 6 5 4 3 2 1 0 — IPR6 IPR5 IPR4 — IPR2 IPR1 IPR0 Initial value : 0 1 1 1 0 1 1 1 R/W — R/W R/W R/W — R/W R/W R/W : The IPR registers are eleven 8-bit readable/writable registers that set priorities (levels 7 to 0) for interrupts other than NMI. The correspondence between IPR settings and interrupt sources is shown in table 5.3.
Section 5 Interrupt Controller As shown in table 5.3, multiple interrupts are assigned to one IPR. Setting a value in the range from H'0 to H'7 in the 3-bit groups of bits 6 to 4 and 2 to 0 sets the priority of the corresponding interrupt. The lowest priority level, level 0, is assigned by setting H'0, and the highest priority level, level 7, by setting H'7. When interrupt requests are generated, the highest-priority interrupt according to the priority levels set in the IPR registers is selected.
Section 5 Interrupt Controller 5.2.
Section 5 Interrupt Controller 5.2.5 IRQ Status Register (ISR) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 IRQ7F IRQ6F IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F 0 0 0 0 0 0 0 0 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Note: * Only 0 can be written, to clear the flag. ISR is an 8-bit readable/writable register that indicates the status of IRQ7 to IRQ0 interrupt requests. ISR is initialized to H'00 by a reset and in hardware standby mode.
Section 5 Interrupt Controller 5.3 Interrupt Sources Interrupt sources comprise external interrupts (NMI and IRQ7 to IRQ0) and internal interrupts (52 sources). 5.3.1 External Interrupts There are nine external interrupts: NMI and IRQ7 to IRQ0. NMI and IRQ7 to IRQ0 can be used to restore the chip from software standby mode. (IRQ7 to IRQ3 can be designated for use as software standby mode clearing sources by setting the IRQ37S bit in SBYCR to 1.
Section 5 Interrupt Controller IRQnE IRQnSCA, IRQnSCB IRQnF Edge/level detection circuit IRQn interrupt S Q request R IRQn input Clear signal Note: n = 7 to 0 Figure 5.2 Block Diagram of Interrupts IRQ7 to IRQ0 Figure 5.3 shows the timing of setting IRQnF. φ IRQn input pin IRQnF Figure 5.3 Timing of Setting IRQnF The vector numbers for IRQ7 to IRQ0 interrupt exception handling are 23 to 16.
Section 5 Interrupt Controller 5.3.2 Internal Interrupts There are 52 sources for internal interrupts from on-chip supporting modules. • For each on-chip supporting module there are flags that indicate the interrupt request status, and enable bits that select enabling or disabling of these interrupts. If both of these are set to 1 for a particular interrupt source, an interrupt request is issued to the interrupt controller. • The interrupt priority level can be set by means of IPR.
Section 5 Interrupt Controller Table 5.
Section 5 Interrupt Controller 2 DMAC* DTC Activa- ActivaPriority tion tion Origin of Interrupt Source Vector Vector 1 Number Address* IPR SWDTEND (softwareactivated data transfer end) DTC 24 H'0060 IPRC2 to High IPRC0 WOVI (interval timer) Watchdog 25 timer H'0064 IPRD6 to IPRD4 — — CMI (compare match)* Refresh controller 26 H'0068 IPRD2 to IPRD0 — — Reserved — 27 H'006C IPRE6 to IPRE4 — — ADI (A/D conversion end) A/D 28 H'0070 IPRE2 to IPRE0 Reserved — 29 H'0074 — —
Section 5 Interrupt Controller 2 Vector Vector 1 Number Address* IPR DMAC* DTC Activa- ActivaPriority tion tion 40 H'00A0 High TGI1B (TGR1B input capture/compare match) 41 H'00A4 TCI1V (overflow 1) 42 H'00A8 — — TCI1U (underflow 1) 43 H'00AC — — 44 H'00B0 TGI2B (TGR2B input capture/compare match) 45 H'00B4 TCI2V (overflow 2) 46 H'00B8 — — TCI2U (underflow 2) 47 H'00BC — — 48 H'00C0 TGI3B (TGR3B input capture/compare match) 49 H'00C4 — TGI3C (TGR3C input capture/compar
Section 5 Interrupt Controller Interrupt Source TGI4A (TGR4A input capture/compare match) Origin of Interrupt Source Vector Vector 1 Number Address* IPR 56 H'00E0 TGI4B (TGR4B input capture/compare match) 57 H'00E4 TCI4V (overflow 4) 58 H'00E8 — — TCI4U (underflow 4) 59 H'00EC — — 60 H'00F0 TGI5B (TGR5B input capture/compare match) 61 H'00F4 TCI5V (overflow 5) 62 H'00F8 — — TCI5U (underflow 5) 63 H'00FC — — 64 H'0100 CMIB0 (compare match B) 65 H'0104 OVI0 (overflow 0)
Section 5 Interrupt Controller 2 Origin of Interrupt Source Vector Vector 1 Number Address* IPR DMAC* DTC Activa- ActivaPriority tion tion DMAC 72 H'0120 High DEND0B (channel 0B 3 transfer end) * 73 H'0124 — DEND1A (channel 1/channel 1A transfer 3 end) * 74 H'0128 — DEND1B (channel 1B 3 transfer end) * 75 H'012C — 76 H'0130 77 H'0134 78 H'0138 79 H'013C 80 H'0140 81 H'0144 TXI0 (transmit data empty 0) 82 H'0148 TEI0 (transmit end 0) 83 H'014C 84 H'0150 85 H'0154 TXI
Section 5 Interrupt Controller 5.4 Interrupt Operation 5.4.1 Interrupt Control Modes and Interrupt Operation Interrupt operations in the chip differ depending on the interrupt control mode. NMI interrupts are accepted at all times except in the reset state and the hardware standby state. In the case of IRQ interrupts and on-chip supporting module interrupts, an enable bit is provided for each interrupt. Clearing an enable bit to 0 disables the corresponding interrupt request.
Section 5 Interrupt Controller Figure 5.4 shows a block diagram of the priority decision circuit. Interrupt control mode 0 I Interrupt acceptance control Default priority determination Interrupt source Vector number 8-level mask control IPR I2 to I0 Interrupt control mode 2 Figure 5.4 Block Diagram of Interrupt Control Operation Interrupt Acceptance Control: In interrupt control mode 0, interrupt acceptance is controlled by the I bit in CCR. Table 5.
Section 5 Interrupt Controller 8-Level Control: In interrupt control mode 2, 8-level mask level determination is performed for the selected interrupts in interrupt acceptance control according to the interrupt priority level (IPR). The interrupt source selected is the interrupt with the highest priority level, and whose priority level set in IPR is higher than the mask level. Table 5.
Section 5 Interrupt Controller 5.4.2 Interrupt Control Mode 0 Enabling and disabling of IRQ interrupts and on-chip supporting module interrupts can be set by means of the I bit in the CPU’s CCR. Interrupts are enabled when the I bit is cleared to 0, and disabled when set to 1. Figure 5.5 shows a flowchart of the interrupt acceptance operation in this case. [1] If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller.
Section 5 Interrupt Controller Program execution state No Interrupt generated? Yes Yes NMI? No No I = 0? Hold pending Yes No IRQ0? Yes No IRQ1? Yes TEI2? Yes Save PC and CCR I←1 Read vector address Branch to interrupt handling routine Figure 5.5 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 0 Rev.6.00 Sep.
Section 5 Interrupt Controller 5.4.3 Interrupt Control Mode 2 Eight-level masking is implemented for IRQ interrupts and on-chip supporting module interrupts by comparing the interrupt mask level set by bits I2 to I0 of EXR in the CPU with IPR. Figure 5.6 shows a flowchart of the interrupt acceptance operation in this case. [1] If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an interrupt request is sent to the interrupt controller.
Section 5 Interrupt Controller Program execution state Interrupt generated? No Yes Yes NMI? No Level 7 interrupt? No Yes Mask level 6 or below? Yes Level 6 interrupt? No No Yes Level 1 interrupt? No Mask level 5 or below? No Yes Yes Mask level 0? No Yes Save PC, CCR, and EXR Hold pending Clear T bit to 0 Update mask level Read vector address Branch to interrupt handling routine Figure 5.6 Flowchart of Procedure Up to Interrupt Acceptance in Interrupt Control Mode 2 Rev.6.00 Sep.
Section 5 Interrupt Controller 5.4.4 Interrupt Exception Handling Sequence Figure 5.7 shows the interrupt exception handling sequence. The example shown is for the case where interrupt control mode 0 is set in advanced mode, and the program area and stack area are in on-chip memory. Rev.6.00 Sep.
(1) (2) (4) (3) Instruction prefetch Internal operation Instruction prefetch address (Not executed. This is the contents of the saved PC, the return address.) (2), (4) Instruction code (Not executed.) (3) Instruction prefetch address (Not executed.
Section 5 Interrupt Controller 5.4.5 Interrupt Response Times The chip is capable of fast word transfer instruction to on-chip memory, and the program area is provided in on-chip ROM and the stack area in on-chip RAM, enabling high-speed processing. Table 5.9 shows interrupt response times—the interval between generation of an interrupt request and execution of the first instruction in the interrupt handling routine. The execution status symbols used in table 5.9 are explained in table 5.10. Table 5.
Section 5 Interrupt Controller 5.5 Usage Notes 5.5.1 Contention between Interrupt Generation and Disabling When an interrupt enable bit is cleared to 0 to disable interrupts, the disabling becomes effective after execution of the instruction.
Section 5 Interrupt Controller 5.5.2 Instructions that Disable Interrupts Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these instructions is executed, all interrupts including NMI are disabled and the next instruction is always executed. When the I bit is set by one of these instructions, the new value becomes valid two states after execution of the instruction ends. 5.5.
Section 5 Interrupt Controller 5.6 DTC and DMAC Activation by Interrupt 5.6.1 Overview The DTC and DMAC* can be activated by an interrupt. In this case, the following options are available. 1. Interrupt request to CPU 2. Activation request to DTC 3. Activation request to DMAC* 4. Selection of a number of the above For details of interrupt requests that can be used with to activate the DTC or DMAC*, see section 8, Data Transfer Controller, and section 7, DMA Controller.
Section 5 Interrupt Controller 5.6.2 Block Diagram Figure 5.9 shows a block diagram of the DTC, DMAC*, and interrupt controller. Note: * The DMAC is not supported in the H8S/2321.
Section 5 Interrupt Controller 5.6.3 Operation The interrupt controller has three main functions in DTC and DMAC* control. Selection of Interrupt Source: With the DMAC*, the activation source is input directly to each channel. The activation source for each DMAC* channel is selected with bits DTF3 to DTF0 in DMACR. Whether the selected activation source is to be managed by the DMAC* can be selected with the DTA bit of DMABCR.
Section 5 Interrupt Controller Table 5.11 Interrupt Source Selection and Clearing Control Settings DMAC DTC DTA DTCE DISEL 0 0 * 1 0 * 1 * 1 Interrupt Source Selection/Clearing Control 1 DMAC* DTC CPU X X X X Legend: : The relevant interrupt is used. Interrupt source clearing is performed. (The CPU should clear the source flag in the interrupt handling routine.) : The relevant interrupt is used. The interrupt source is not cleared. X: The relevant interrupt cannot be used.
Section 6 Bus Controller Section 6 Bus Controller 6.1 Overview The chip has an on-chip bus controller (BSC) that manages the external address space divided into eight areas. The bus specifications, such as bus width and number of access states, can be set independently for each area, enabling multiple memories to be connected easily.
Section 6 Bus Controller • Idle cycle insertion ⎯ An idle cycle can be inserted in case of an external read cycle between different areas ⎯ An idle cycle can be inserted when an external read cycle is immediately followed by an external write cycle • Write buffer functions ⎯ External write cycle and internal access can be executed in parallel ⎯ DMAC* single address mode and internal access can be executed in parallel • Bus arbitration function ⎯ Includes a bus arbiter that arbitrates bus mastership among t
Section 6 Bus Controller 6.1.2 Block Diagram Figure 6.1 shows a block diagram of the bus controller.
Section 6 Bus Controller 6.1.3 Pin Configuration Table 6.1 summarizes the pins of the bus controller. Table 6.1 Bus Controller Pins Name Symbol I/O Function Address strobe AS Output Strobe signal indicating that address output on address bus is enabled. Read RD Output Strobe signal indicating that external space is being read. High write/write enable HWR Output Strobe signal indicating that external space is to be written, and upper half (D15 to D8) of data bus is enabled.
Section 6 Bus Controller Name Symbol I/O Function Chip select 6 CS6 Output Strobe signal indicating that area 6 is selected. Chip select 7 CS7 Output Strobe signal indicating that area 7 is selected. Upper column address strobe CAS* Output 2-CAS DRAM upper column address strobe signal. Lower column strobe LCAS* Output DRAM lower column address strobe signal. Wait WAIT Input Wait request signal when accessing external 3-state access space.
Section 6 Bus Controller 6.1.4 Register Configuration Table 6.2 summarizes the registers of the bus controller. Table 6.
Section 6 Bus Controller 6.2 Register Descriptions 6.2.1 Bus Width Control Register (ABWCR) Bit : 7 6 5 4 3 2 1 0 ABW7 ABW6 ABW5 ABW4 ABW3 ABW2 ABW1 ABW0 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Modes 5 to 7 Initial value : R/W : Mode 4 Initial value : R/W : ABWCR is an 8-bit readable/writable register that designates each area for either 8-bit access or 16-bit access.
Section 6 Bus Controller 6.2.2 Bit Access State Control Register (ASTCR) : Initial value : R/W : 7 6 5 4 3 2 1 0 AST7 AST6 AST5 AST4 AST3 AST2 AST1 AST0 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W ASTCR is an 8-bit readable/writable register that designates each area as either a 2-state access space or a 3-state access space. ASTCR sets the number of access states for the external memory space.
Section 6 Bus Controller 6.2.3 Wait Control Registers H and L (WCRH, WCRL) WCRH and WCRL are 8-bit readable/writable registers that select the number of program wait states for each area. Program waits are not inserted in the case of on-chip memory or internal I/O registers. WCRH and WCRL are initialized to H'FF by a reset and in hardware standby mode. They are not initialized in software standby mode.
Section 6 Bus Controller Bits 5 and 4—Area 6 Wait Control 1 and 0 (W61, W60): These bits select the number of program wait states when area 6 in external space is accessed while the AST6 bit in ASTCR is set to 1.
Section 6 Bus Controller WCRL Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 W31 W30 W21 W20 W11 W10 W01 W00 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W Bits 7 and 6—Area 3 Wait Control 1 and 0 (W31, W30): These bits select the number of program wait states when area 3 in external space is accessed while the AST3 bit in ASTCR is set to 1.
Section 6 Bus Controller Bits 3 and 2—Area 1 Wait Control 1 and 0 (W11, W10): These bits select the number of program wait states when area 1 in external space is accessed while the AST1 bit in ASTCR is set to 1.
Section 6 Bus Controller Bit 7—Idle Cycle Insert 1 (ICIS1): Selects whether or not one idle cycle state is to be inserted between bus cycles when successive external read cycles are performed in different areas.
Section 6 Bus Controller Bit 3 BRSTS0 Description 0 Max. 4 words in burst access 1 Max. 8 words in burst access (Initial value) Bits 2 to 0—RAM Type Select (RMTS2 to RMTS0): These bits select the memory interface for areas 2 to 5 in advanced mode. When DRAM space is selected, the relevant area is designated as a DRAM interface area. In the H8S/2321 these bits are reserved and should only be written with 0.
Section 6 Bus Controller 6.2.5 Bit Bus Control Register L (BCRL) : Initial value : R/W : 7 6 5 4 3 2 1 0 BRLE BREQOE EAE — DDS* — WDBE* WAITE 0 0 1 1 1 1 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Note: * This bit is reserved in the H8S/2321.
Section 6 Bus Controller Bit 5—External Address Enable (EAE): Selects whether addresses H'010000 to H'03FFFF*2 are to be internal addresses or external addresses.
Section 6 Bus Controller Bit 1—Write Data Buffer Enable (WDBE): Selects whether or not the write buffer function is used for an external write cycle or DMAC single address cycle. In the H8S/2321 this bit is reserved and should only be written with 0. Bit 1 WDBE Description 0 Write data buffer function not used 1 Write data buffer function used (Initial value) Bit 0—WAIT Pin Enable (WAITE): Selects enabling or disabling of wait input by the WAIT pin.
Section 6 Bus Controller Bit 7—TP Cycle Control (TPC): Selects whether a 1-state or 2-state precharge cycle (TP) is to be used when areas 2 to 5 designated as DRAM space are accessed. Bit 7 TPC Description 0 1 1-state precharge cycle is inserted 2-state precharge cycle is inserted (Initial value) Bit 6—Burst Access Enable (BE): Selects enabling or disabling of burst access to areas 2 to 5 designated as DRAM space. DRAM space burst access is performed in fast page mode.
Section 6 Bus Controller Bit 3 MXC1 Bit 2 MXC0 Description 0 0 8-bit shift 1 1 0 1 (Initial value) • When 8-bit access space is designated: Row address A23 to A8 used for comparison • When 16-bit access space is designated: Row address A23 to A9 used for comparison 9-bit shift • When 8-bit access space is designated: Row address A23 to A9 used for comparison • When 16-bit access space is designated: Row address A23 to A10 used for comparison 10-bit shift • When 8-bit access space is desi
Section 6 Bus Controller 6.2.7 Bit DRAM Control Register (DRAMCR) : Initial value : R/W : 7 6 5 4 3 2 1 0 RFSHE RCW RMODE CMF CMIE CKS2 CKS1 CKS0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W DRAMCR is an 8-bit readable/writable register that selects the DRAM refresh mode and refresh counter clock, and controls the refresh timer. DRAMCR is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in software standby mode.
Section 6 Bus Controller Bit 4—Compare Match Flag (CMF): Status flag that indicates a match between the values of RTCNT and RTCOR. When refresh control is performed (RFSHE = 1), 1 should be written to the CMF bit when writing to DRAMCR.
Section 6 Bus Controller 6.2.8 Bit Refresh Timer Counter (RTCNT) : 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W : RTCNT is an 8-bit readable/writable up-counter. RTCNT counts up using the internal clock selected by bits CKS2 to CKS0 in DRAMCR. When RTCNT matches RTCOR (compare match), the CMF flag in DRAMCR is set to 1 and RTCNT is cleared to H'00. If the RFSHE bit in DRAMCR is set to 1 at this time, a refresh cycle is started.
Section 6 Bus Controller 6.3 Overview of Bus Control 6.3.1 Area Partitioning In advanced mode, the bus controller partitions the 16-Mbyte address space into eight areas, 0 to 7, in 2-Mbyte units, and performs bus control for external space in area units. Figure 6.2 shows an outline of the memory map. Chip select signals (CS0 to CS7) can be output for each area.
Section 6 Bus Controller 6.3.2 Bus Specifications The external space bus specifications consist of three elements: bus width, number of access states, and number of program wait states. The bus width and number of access states for on-chip memory and internal I/O registers are fixed, and are not affected by the bus controller. Bus Width: A bus width of 8 or 16 bits can be selected with ABWCR.
Section 6 Bus Controller Table 6.3 Bus Specifications for Each Area (Basic Bus Interface) WCRH, WCRL Bus Specifications (Basic Bus Interface) ABWCR ABWn ASTCR ASTn Wn1 Wn0 Bus Width Program Wait Access States States 0 0 — — 16 2 0 1 0 0 3 0 1 1 1 0 2 1 3 1 6.3.
Section 6 Bus Controller 6.3.4 Advanced Mode The initial state of each area is basic bus interface, 3-state access space. The initial bus width is selected according to the operating mode. The bus specifications described here cover basic items only, and the sections on each memory interface (6.4, Basic Bus Interface, 6.5, DRAM Interface (Not supported in the H8S/2321), and 6.7, Burst ROM Interface) should be referred to for further details.
Section 6 Bus Controller 6.3.5 Chip Select Signals The chip can output chip select signals (CS0 to CS7) to areas 0 to 7, the signal being driven low when the corresponding external space area is accessed. Figure 6.3 shows an example of CSn (n = 0 to 7) output timing. Enabling or disabling of the CSn signal is performed by setting the data direction register (DDR) for the port corresponding to the particular CSn pin and either the CS167 enable bit (CS167E) or the CS25 enable bit (CS25E).
Section 6 Bus Controller 6.4 Basic Bus Interface 6.4.1 Overview The basic bus interface enables direct connection of ROM, SRAM, and so on. The bus specifications can be selected with ABWCR, ASTCR, WCRH, and WCRL. (See table 6.3.) 6.4.2 Data Size and Data Alignment Data sizes for the CPU and other internal bus masters are byte, word, and longword.
Section 6 Bus Controller 16-Bit Access Space: Figure 6.5 illustrates data alignment control for the 16-bit access space. With the 16-bit access space, the upper data bus (D15 to D8) and lower data bus (D7 to D0) are used for accesses. The amount of data that can be accessed at one time is one byte or one word, and a longword transfer instruction is executed as two word transfer instructions. In byte access, whether the upper or lower data bus is used is determined by whether the address is even or odd.
Section 6 Bus Controller 6.4.3 Valid Strobes Table 6.4 shows the data buses used and valid strobes for the access spaces. In a read, the RD signal is valid without discrimination between the upper and lower halves of the data bus. In a write, the HWR signal is valid for the upper half of the data bus, and the LWR signal for the lower half. Table 6.
Section 6 Bus Controller 6.4.4 Basic Timing 8-Bit 2-State Access Space: Figure 6.6 shows the bus timing for an 8-bit 2-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. The LWR pin is fixed high. Wait states cannot be inserted. Bus cycle T1 T2 φ Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR LWR High Write D15 to D8 D7 to D0 Valid High impedance Note: n = 0 to 7 Figure 6.
Section 6 Bus Controller 8-Bit 3-State Access Space: Figure 6.7 shows the bus timing for an 8-bit 3-state access space. When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. The LWR pin is fixed high. Wait states can be inserted. Bus cycle T1 T2 T3 φ Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR LWR High Write D15 to D8 D7 to D0 Valid High impedance Note: n = 0 to 7 Figure 6.7 Bus Timing for 8-Bit 3-State Access Space Rev.6.
Section 6 Bus Controller 16-Bit 2-State Access Space: Figures 6.8 to 6.10 show bus timings for a 16-bit 2-state access space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used for the even address, and the lower half (D7 to D0) for the odd address. Wait states cannot be inserted. Bus cycle T1 T2 φ Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR LWR High Write D15 to D8 D7 to D0 Valid High impedance Note: n = 0 to 7 Figure 6.
Section 6 Bus Controller Bus cycle T1 T2 φ Address bus CSn AS RD Read D15 to D8 Invalid D7 to D0 Valid HWR High LWR Write D15 to D8 D7 to D0 High impedance Valid Note: n = 0 to 7 Figure 6.9 Bus Timing for 16-Bit 2-State Access Space (2) (Odd Address Byte Access) Rev.6.00 Sep.
Section 6 Bus Controller Bus cycle T1 T2 φ Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Valid HWR LWR Write D15 to D8 Valid D7 to D0 Valid Note: n = 0 to 7 Figure 6.10 Bus Timing for 16-Bit 2-State Access Space (3) (Word Access) Rev.6.00 Sep.
Section 6 Bus Controller 16-Bit 3-State Access Space: Figures 6.11 to 6.13 show bus timings for a 16-bit 3-state access space. When a 16-bit access space is accessed , the upper half (D15 to D8) of the data bus is used for the even address, and the lower half (D7 to D0) for the odd address. Wait states can be inserted. Bus cycle T1 T2 T3 φ Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Invalid HWR LWR High Write D15 to D8 D7 to D0 Valid High impedance Note: n = 0 to 7 Figure 6.
Section 6 Bus Controller Bus cycle T1 T2 T3 φ Address bus CSn AS RD Read D15 to D8 Invalid D7 to D0 Valid HWR High LWR Write D15 to D8 D7 to D0 High impedance Valid Note: n = 0 to 7 Figure 6.12 Bus Timing for 16-Bit 3-State Access Space (2) (Odd Address Byte Access) Rev.6.00 Sep.
Section 6 Bus Controller Bus cycle T1 T2 T3 φ Address bus CSn AS RD Read D15 to D8 Valid D7 to D0 Valid HWR LWR Write D15 to D8 Valid D7 to D0 Valid Note: n = 0 to 7 Figure 6.13 Bus Timing for 16-Bit 3-State Access Space (3) (Word Access) Rev.6.00 Sep.
Section 6 Bus Controller 6.4.5 Wait Control When accessing external space, the chip can extend the bus cycle by inserting one or more wait states (Tw). There are two ways of inserting wait states: program wait insertion and pin wait insertion using the WAIT pin. Program Wait Insertion: From 0 to 3 wait states can be inserted automatically between the T2 state and T3 state on an individual area basis in 3-state access space, according to the settings of WCRH and WCRL.
Section 6 Bus Controller Figure 6.14 shows an example of wait state insertion timing. By program wait T1 T2 Tw By WAIT pin Tw Tw T3 φ WAIT Address bus AS RD Read Data bus Read data HWR, LWR Write Data bus Note: Write data indicates the timing of WAIT pin sampling. Figure 6.14 Example of Wait State Insertion Timing The settings after a power-on reset are: 3-state access, 3 program wait state insertion, and WAIT input disabled. Rev.6.00 Sep.
Section 6 Bus Controller 6.5 DRAM Interface (Not supported in the H8S/2321) 6.5.1 Overview When the chip is in advanced mode, external space areas 2 to 5 can be designated as DRAM space, and DRAM interfacing performed. With the DRAM interface, DRAM can be directly connected to the chip. A DRAM space of 2, 4, or 8 Mbytes can be set by means of bits RMTS2 to RMTS0 in BCRH. Burst operation is also possible, using fast page mode. 6.5.
Section 6 Bus Controller 6.5.3 Address Multiplexing With DRAM space, the row address and column address are multiplexed. In address multiplexing, the size of the shift of the row address is selected with bits MXC1 and MXC0 in MCR. Table 6.6 shows the relation between the settings of MXC1 and MXC0 and the shift size. Table 6.
Section 6 Bus Controller 6.5.5 Pins Used for DRAM Interface Table 6.7 shows the pins used for DRAM interfacing and their functions. Table 6.
Section 6 Bus Controller 6.5.6 Basic Timing Figure 6.15 shows the basic access timing for DRAM space. The basic DRAM access timing is 4 states. Unlike the basic bus interface, the corresponding bits in ASTCR control only enabling or disabling of wait insertion, and do not affect the number of access states. When the corresponding bit in ASTCR is cleared to 0, wait states cannot be inserted in the DRAM access cycle.
Section 6 Bus Controller 6.5.7 Precharge State Control When DRAM is accessed, an RAS precharging time must be secured. With the chip, one Tp state is always inserted when DRAM space is accessed. This can be changed to two Tp states by setting the TPC bit in MCR to 1. Set the appropriate number of Tp cycles according to the DRAM connected and the operating frequency of the chip. Figure 6.16 shows the timing when two Tp states are inserted.
Section 6 Bus Controller 6.5.8 Wait Control There are two ways of inserting wait states in a DRAM access cycle: program wait insertion and pin wait insertion using the WAIT pin. Program Wait Insertion: When the bit in ASTCR corresponding to an area designated as DRAM space is set to 1, from 0 to 3 wait states can be inserted automatically between the Tc1 state and Tc2 state, according to the settings of WCRH and WCRL.
Section 6 Bus Controller By program wait Tp Tr Tc1 Tw By WAIT pin Tw Tc2 φ WAIT* Address bus CSn (RAS) CAS Read Data bus Read data CAS Write Data bus Notes: Write data indicates the timing of WAIT pin sampling. n = 2 to 5 Figure 6.17 Example of Wait State Insertion Timing Rev.6.00 Sep.
Section 6 Bus Controller 6.5.9 Byte Access Control When DRAM with a ×16 configuration is connected, the 2-CAS system can be used for the control signals required for byte access. Figure 6.18 shows the control timing in the 2-CAS system, and figure 6.19 shows an example of 2-CAS type DRAM connection. Tp Tr Tc1 Tc2 φ A23 to A0 Row Column CSn (RAS) CAS Byte control LCAS HWR (WE) Note: n = 2 to 5 Figure 6.18 2-CAS System Control Timing (Upper Byte Write Access) Rev.6.00 Sep.
Section 6 Bus Controller Chip (Address shift size set to 9 bits) CS (RAS) 2-CAS type 4-Mbit DRAM 256-kbyte × 16-bit configuration 9-bit column address RAS CAS UCAS LCAS LCAS HWR (WE) WE A9 A8 A8 A7 A7 A6 A6 A5 A5 A4 A4 A3 A3 A2 A2 A1 A1 A0 D15 to D0 Row address input: A8 to A0 Column address input: A8 to A0 D15 to D0 OE Figure 6.19 Example of 2-CAS DRAM Connection Rev.6.00 Sep.
Section 6 Bus Controller 6.5.10 Burst Operation With DRAM, in addition to full access (normal access) in which data is accessed by outputting a row address for each access, a fast page mode is also provided which can be used when making a number of consecutive accesses to the same row address. This mode enables fast (burst) access of data by simply changing the column address after the row address has been output. Burst access can be selected by setting the BE bit in MCR to 1.
Section 6 Bus Controller RAS Down Mode and RAS Up Mode: Even when burst operation is selected, it may happen that access to DRAM space is not continuous, but is interrupted by access to another space. In this case, if the RAS signal is held low during the access to the other space, burst operation can be resumed when the same row address in DRAM space is accessed again. • RAS down mode To select RAS down mode, set the RCDM bit in MCR to 1.
Section 6 Bus Controller • RAS up mode To select RAS up mode, clear the RCDM bit in MCR to 0. Each time access to DRAM space is interrupted and another space is accessed, the RAS signal goes high again. Burst operation is only performed if DRAM space is continuous. Figure 6.22 shows an example of the timing in RAS up mode. In the case of burst ROM space access, the RAS signal is not restored to the high level.
Section 6 Bus Controller 6.5.11 Refresh Control The chip is provided with a DRAM refresh control function. Either of two refreshing methods can be selected: CAS-before-RAS (CBR) refreshing, or self-refreshing. CAS-before-RAS (CBR) Refreshing: To select CBR refreshing, set the RFSHE bit in DRAMCR to 1, and clear the RMODE bit to 0.
Section 6 Bus Controller φ RTCNT N H'00 RTCOR N Refresh request signal and CMF bit setting signal Figure 6.24 Compare Match Timing TRp TRr TRc1 TRc2 φ CS (RAS) CAS, LCAS Note: n = 2 to 5 Figure 6.25 CBR Refresh Timing When the RCW bit is set to 1, RAS signal output is delayed by one cycle. The width of the RAS signal should be adjusted with bits RLW1 and RLW0. These bits are only enabled in refresh operations. Figure 6.26 shows the timing when the RCW bit is set to 1. Rev.6.00 Sep.
Section 6 Bus Controller TRp TRr TRc1 TRw TRc2 φ CSn (RAS) CAS, LCAS Note: n = 2 to 5 Figure 6.26 CBR Refresh Timing (When RCW = 1, RLW1 = 0, RLW0 = 1) Self-Refreshing: A self-refresh mode (battery backup mode) is provided for DRAM as a kind of standby mode. In this mode, refresh timing and refresh addresses are generated within the DRAM. To select self-refreshing, set the RFSHE bit and RMODE bit in DRAMCR to 1.
Section 6 Bus Controller 6.6 DMAC Single Address Mode and DRAM Interface (Not supported in the H8S/2321) When burst mode is selected with the DRAM interface, the DACK output timing can be selected with the DDS bit. When DRAM space is accessed in DMAC single address mode at the same time, this bit selects whether or not burst access is to be performed. 6.6.1 When DDS = 1 Burst access is performed by determining the address only, irrespective of the bus master.
Section 6 Bus Controller 6.6.2 When DDS = 0 When DRAM space is accessed in DMAC single address mode, full access (normal access) is always performed. The DACK output goes low from the Tr state in the case of the DRAM interface. In modes other than DMAC single address mode, burst access can be used when accessing DRAM space. Figure 6.29 shows the DACK output timing for the DRAM interface when DDS = 0.
Section 6 Bus Controller 6.7 Burst ROM Interface 6.7.1 Overview With the chip, external space area 0 can be designated as burst ROM space, and burst ROM interfacing can be performed. The burst ROM space interface enables 16-bit configuration ROM with burst access capability to be accessed at high speed. Area 0 can be designated as burst ROM space by means of the BRSTRM bit in BCRH. Consecutive burst accesses of a maximum of 4 words or 8 words can be performed for CPU instruction fetches only.
Section 6 Bus Controller Full access T1 T2 Burst access T3 T1 T2 T1 T2 φ Only lower address changed Address bus CS0 AS RD Data bus Read data Read data Read data Figure 6.30 (a) Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 1) Rev.6.00 Sep.
Section 6 Bus Controller Full access T1 T2 Burst access T1 T1 φ Only lower address changed Address bus CS0 AS RD Data bus Read data Read data Read data Figure 6.30 (b) Example of Burst ROM Access Timing (When AST0 = BRSTS1 = 0) 6.7.3 Wait Control As with the basic bus interface, either program wait insertion or pin wait insertion using the WAIT pin can be used in the initial cycle (full access) of the burst ROM interface. See section 6.4.5, Wait Control.
Section 6 Bus Controller 6.8 Idle Cycle 6.8.1 Operation When the chip accesses external space, it can insert a 1-state idle cycle (TI) between bus cycles in the following two cases: (1) when read accesses in different areas occur consecutively, and (2) when a write cycle occurs immediately after a read cycle. By inserting an idle cycle it is possible, for example, to avoid data collisions between ROM, with a long output floating time, and highspeed memory, I/O interfaces, and so on.
Section 6 Bus Controller Write after Read: If an external write occurs after an external read while the ICIS0 bit in BCRH is set to 1, an idle cycle is inserted at the start of the write cycle. Figure 6.32 shows an example of the operation in this case. In this example, bus cycle A is a read cycle from ROM with a long output floating time, and bus cycle B is a CPU write cycle. In (a), an idle cycle is not inserted, and a collision occurs in cycle B between the read data from ROM and the CPU write data.
Section 6 Bus Controller Relationship between Chip Select (CS) Signal and Read (RD) Signal: Depending on the system’s load conditions, the RD signal may lag behind the CS signal. An example is shown in figure 6.33. In this case, with the setting for no idle cycle insertion (a), there may be a period of overlap between the bus cycle A RD signal and the bus cycle B CS signal. Setting idle cycle insertion, as in (b), however, will prevent any overlap between the RD and CS signals.
Section 6 Bus Controller Usage Notes: When DRAM space* is accessed, the ICIS0 and ICIS1 bit settings are disabled. In the case of consecutive reads between different areas, for example, if the second access is a DRAM access*, only a Tp cycle is inserted, and a TI cycle is not. The timing in this case is shown in figure 6.34. However, in burst access in RAS down mode these settings are enabled, and an idle cycle is inserted. The timing in this case is shown in figures 6.35 (a) and (b).
Section 6 Bus Controller DRAM space read Tp Tr Tc1 External read Tc2 T1 T1 T2 DRAM space read T3 Tc1 Tc1 Tc2 EXTAL Address RD RAS CAS, LCAS Data bus Idle cycle Figure 6.35 (a) Example of Idle Cycle Operation in RAS Down Mode (ICIS1 = 1) DRAM space read Tp Tr Tc1 External read Tc2 T1 T1 T2 DRAM space write T3 Tc1 Tc1 Tc2 EXTAL Address RD HWR RAS CAS, LCAS Data bus Idle cycle Figure 6.35 (b) Example of Idle Cycle Operation in RAS Down Mode (ICIS0 = 1) Rev.6.00 Sep.
Section 6 Bus Controller 6.8.2 Pin States in Idle Cycle Table 6.8 shows the pin states in an idle cycle. Table 6.8 Pin States in Idle Cycle Pins Pin State A23 to A0 Contents of next bus cycle D15 to D0 2 CSn* High impedance 1 High* CAS* High AS High RD High HWR High LWR High 4 3 4 DACKm* * Notes: 1. 2. 3. 4. High Remains low in DRAM space RAS down mode or a refresh cycle. n = 0 to 7 m = 0 and 1 The CAS and DACKm pin functions are not supported in the H8S/2321. Rev.6.00 Sep.
Section 6 Bus Controller 6.9 Write Data Buffer Function The chip has a write data buffer function in the external data bus. Using the write data buffer function enables external writes and DMA single address mode transfers to be executed in parallel with internal accesses. The write data buffer function is made available by setting the WDBE bit in BCRL to 1. Figure 6.36 shows an example of the timing when the write data buffer function is used.
Section 6 Bus Controller 6.10 Bus Release 6.10.1 Overview The chip can release the external bus in response to a bus request from an external device. In the external bus released state, the internal bus master continues to operate as long as there is no external access. If an internal bus master wants to make an external access in the external bus released state, or if a refresh request* is generated, it can issue a bus request off-chip.
Section 6 Bus Controller If a refresh request* and external bus release request occur simultaneously, the order of priority is as follows: (High) Refresh* > External bus release (Low) As a refresh* and an external access by an internal bus master can be executed simultaneously, there is no relative order of priority for these two operations. Note: * The DRAM interface is not supported in the H8S/2321. 6.10.3 Pin States in External Bus Released State Table 6.
Section 6 Bus Controller 6.10.4 Transition Timing Figure 6.37 shows the timing for transition to the bus released state. CPU cycle T0 CPU cycle External bus released state T1 T2 φ High impedance Address bus Address High impedance Data bus High impedance AS High impedance RD High impedance HWR, LWR BREQ BACK BREQO * Minimum 1 state [1] [2] [3] [4] [1] Low level of BREQ pin is sampled at rise of T2 state.
Section 6 Bus Controller 6.10.5 Usage Note Do not set MSTPCR to H'FFFF or H'EFFF, since the external bus release function will halt if a transition is made to sleep mode when either of these settings has been made. 6.11 Bus Arbitration 6.11.1 Overview The chip has a bus arbiter that arbitrates bus master operations. There are three bus masters, the CPU, DTC, and DMAC*, which perform read/write operations when they have possession of the bus.
Section 6 Bus Controller As a refresh* and an external access by an internal bus master can be executed simultaneously, there is no relative order of priority for these two operations. Note: * The DMAC and DRAM interface are not supported in the H8S/2321. 6.11.3 Bus Transfer Timing Even if a bus request is received from a bus master with a higher priority than that of the bus master that has acquired the bus and is currently operating, the bus is not necessarily transferred immediately.
Section 6 Bus Controller 6.11.4 External Bus Release Usage Note External bus release can be performed on completion of an external bus cycle. The RD signal and the DRAM interface* RAS and CAS signals remain low until the end of the external bus cycle. Therefore, when external bus release is performed, the RD, RAS, and CAS signals may change from the low level to the high-impedance state. Note: * The DRAM interface is not supported in the H8S/2321. 6.
Section 6 Bus Controller Rev.6.00 Sep.
Section 7 DMA Controller (Not Supported in the H8S/2321) Section 7 DMA Controller (Not Supported in the H8S/2321) 7.1 Overview The chip has a built-in DMA controller* (DMAC) which can carry out data transfer on up to 4 channels. Note: * The DMAC is not supported in the H8S/2321. 7.1.1 Features The features of the DMAC are listed below.
Section 7 DMA Controller (Not Supported in the H8S/2321) ⎯ External request ⎯ Auto-request • Module stop mode can be set ⎯ The initial setting enables DMAC registers to be accessed. DMAC operation is halted by setting module stop mode 7.1.2 Block Diagram A block diagram of the DMAC is shown in figure 7.1.
Section 7 DMA Controller (Not Supported in the H8S/2321) 7.1.3 Overview of Functions Tables 7.1 (1) and (2) summarize DMAC functions in short address mode and full address mode, respectively. Table 7.
Section 7 DMA Controller (Not Supported in the H8S/2321) Table 7.
Section 7 DMA Controller (Not Supported in the H8S/2321) 7.1.4 Pin Configuration Table 7.2 summarizes the DMAC pins. In short address mode, external request transfer, single address transfer, and transfer end output are not performed for channel A. The DMA transfer acknowledge function is used in channel B single address mode in short address mode. When the DREQ pin is used, do not designate the corresponding port for output.
Section 7 DMA Controller (Not Supported in the H8S/2321) 7.1.5 Register Configuration Table 7.3 summarizes the DMAC registers. Table 7.
Section 7 DMA Controller (Not Supported in the H8S/2321) 7.2 Register Descriptions (1) (Short Address Mode) Short address mode transfer can be performed for channels A and B independently. Short address mode transfer is specified for each channel by clearing the FAE bit in DMABCR to 0, as shown in table 7.4. Short address mode or full address mode can be selected for channels 1 and 0 independently by means of bits FAE1 and FAE0. Table 7.
Section 7 DMA Controller (Not Supported in the H8S/2321) 7.2.
Section 7 DMA Controller (Not Supported in the H8S/2321) 7.2.2 I/O Address Register (IOAR) Bit : IOAR : Initial value : R/W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 * * * * * * * * * * * * * * * * : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W *: Undefined IOAR is a 16-bit readable/writable register that specifies the lower 16 bits of the transfer source address or destination address.
Section 7 DMA Controller (Not Supported in the H8S/2321) In sequential mode and idle mode, ETCR functions as a 16-bit transfer counter (with a count range of 1 to 65,536). ETCR is decremented by 1 each time a transfer is performed, and when the count reaches H'0000, the DTE bit in DMABCR is cleared, and transfer ends.
Section 7 DMA Controller (Not Supported in the H8S/2321) 7.2.4 DMA Control Register (DMACR) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 DTSZ DTID5 RPE DTDIR DTF3 DTF2 DTF1 DTF0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W DMACR is an 8-bit readable/writable register that controls the operation of each DMAC channel. DMACR is initialized to H'00 by a reset, and in standby mode. Bit 7—Data Transfer Size (DTSZ): Selects the size of data to be transferred at one time.
Section 7 DMA Controller (Not Supported in the H8S/2321) Bit 5—Repeat Enable (RPE): Used in combination with the DTIE bit in DMABCR to select the mode (sequential, idle, or repeat) in which transfer is to be performed.
Section 7 DMA Controller (Not Supported in the H8S/2321) Bits 3 to 0—Data Transfer Factor (DTF3 to DTF0): These bits select the data transfer factor (activation source). There are some differences in activation sources for channel A and for channel B.
Section 7 DMA Controller (Not Supported in the H8S/2321) Channel B Bit 3 DTF3 Bit 2 DTF2 Bit 1 DTF1 Bit 0 DTF0 Description 0 0 0 0 — 1 0 Activated by A/D converter conversion end interrupt Activated by DREQ pin falling edge input* 1 Activated by DREQ pin low-level input 0 0 Activated by SCI channel 0 transmit-data-empty interrupt 1 Activated by SCI channel 0 receive-data-full interrupt 1 0 Activated by SCI channel 1 transmit-data-empty interrupt 1 Activated by SCI channel 1 receive-d
Section 7 DMA Controller (Not Supported in the H8S/2321) 7.2.
Section 7 DMA Controller (Not Supported in the H8S/2321) Bit 14—Full Address Enable 0 (FAE0): Specifies whether channel 0 is to be used in short address mode or full address mode. In short address mode, channels 0A and 0B can be used as independent channels. Bit 14 FAE0 Description 0 Short address mode 1 Full address mode (Initial value) Bit 13—Single Address Enable 1 (SAE1): Specifies whether channel 1B is to be used for transfer in dual address mode or single address mode.
Section 7 DMA Controller (Not Supported in the H8S/2321) When DTE = 1 and DTA = 0, the internal interrupt source selected by the data transfer factor setting is not cleared when a transfer is performed, and can issue an interrupt request to the CPU or DTC in parallel. In this case, the interrupt source should be cleared by the CPU or DTC transfer.
Section 7 DMA Controller (Not Supported in the H8S/2321) Bit 8—Data Transfer Acknowledge 0A (DTA0A): Enables or disables clearing, when DMA transfer is performed, of the internal interrupt source selected by the channel 0A data transfer factor setting.
Section 7 DMA Controller (Not Supported in the H8S/2321) Bit 6—Data Transfer Enable 1A (DTE1A): Enables or disables data transfer on channel 1A. Bit 6 DTE1A Description 0 Data transfer disabled 1 Data transfer enabled (Initial value) Bit 5—Data Transfer Enable 0B (DTE0B): Enables or disables data transfer on channel 0B.
Section 7 DMA Controller (Not Supported in the H8S/2321) Bit 2—Data Transfer Interrupt Enable 1A (DTIE1A): Enables or disables the channel 1A transfer end interrupt. Bit 2 DTIE1A Description 0 Transfer end interrupt disabled 1 Transfer end interrupt enabled (Initial value) Bit 1—Data Transfer Interrupt Enable 0B (DTIE0B): Enables or disables the channel 0B transfer end interrupt.
Section 7 DMA Controller (Not Supported in the H8S/2321) 7.3 Register Descriptions (2) (Full Address Mode) Full address mode transfer is performed with channels A and B together. For details of full address mode setting, see table 7.4. 7.3.
Section 7 DMA Controller (Not Supported in the H8S/2321) 7.3.3 Execute Transfer Count Register (ETCR) ETCR is a 16-bit readable/writable register that specifies the number of transfers. The function of this register is different in normal mode and in block transfer mode. ETCR is not initialized by a reset or in standby mode.
Section 7 DMA Controller (Not Supported in the H8S/2321) Block Transfer Mode ETCRA Block Size Storage (ETCRAH) Bit : 15 14 13 12 11 10 9 8 * * * * * * * * R/W R/W R/W R/W R/W R/W R/W R/W Initial value : R/W : Block Size Counter (ETCRAL) Bit : 7 6 5 4 3 2 1 0 Initial value : * * * * * * * * R/W R/W R/W R/W R/W R/W R/W R/W R/W : *: Undefined ETCRB Block Transfer Counter Bit : Initial value : R/W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Section 7 DMA Controller (Not Supported in the H8S/2321) 7.3.4 DMA Control Register (DMACR) DMACR is a 16-bit readable/writable register that controls the operation of each DMAC channel. In full address mode, DMACRA and DMACRB have different functions. DMACR is initialized to H'0000 by a reset, and in hardware standby mode.
Section 7 DMA Controller (Not Supported in the H8S/2321) Bit 14—Source Address Increment/Decrement (SAID) Bit 13—Source Address Increment/Decrement Enable (SAIDE): These bits specify whether source address register MARA is to be incremented, decremented, or left unchanged, when data transfer is performed.
Section 7 DMA Controller (Not Supported in the H8S/2321) Bit 6—Destination Address Increment/Decrement (DAID) Bit 5—Destination Address Increment/Decrement Enable (DAIDE): These bits specify whether destination address register MARB is to be incremented, decremented, or left unchanged, when data transfer is performed.
Section 7 DMA Controller (Not Supported in the H8S/2321) • Block Transfer Mode Bit 3 DTF3 Bit 2 DTF2 Bit 1 DTF1 Bit 0 DTF0 Description 0 0 0 0 — 1 0 Activated by A/D converter conversion end interrupt Activated by DREQ pin falling edge input* 1 Activated by DREQ pin low-level input 0 0 Activated by SCI channel 0 transmit-data-empty interrupt 1 Activated by SCI channel 0 receive-data-full interrupt 1 0 Activated by SCI channel 1 transmit-data-empty interrupt 1 Activated by SCI channel
Section 7 DMA Controller (Not Supported in the H8S/2321) 7.3.
Section 7 DMA Controller (Not Supported in the H8S/2321) Bit 14—Full Address Enable 0 (FAE0): Specifies whether channel 0 is to be used in short address mode or full address mode. In full address mode, channels 0A and 0B are used together as a single channel. Bit 14 FAE0 Description 0 Short address mode 1 Full address mode (Initial value) Bits 13 and 12—Reserved: Can be read or written to. Only 0 should be written to these bits.
Section 7 DMA Controller (Not Supported in the H8S/2321) Bit 9—Data Transfer Acknowledge 0 (DTA0): Enables or disables clearing, when DMA transfer is performed, of the internal interrupt source selected by the channel 0 data transfer factor setting.
Section 7 DMA Controller (Not Supported in the H8S/2321) Bit 5—Data Transfer Master Enable 0 (DTME0): Enables or disables data transfer on channel 0. Bit 5 DTME0 Description 0 Data transfer disabled. In normal mode, cleared to 0 by an NMI interrupt (Initial value) 1 Data transfer enabled Bits 6 and 4—Data Transfer Enable (DTE): When DTE = 0, data transfer is disabled and the activation source selected by the data transfer factor setting is ignored.
Section 7 DMA Controller (Not Supported in the H8S/2321) Bit 4—Data Transfer Enable 0 (DTE0): Enables or disables data transfer on channel 0. Bit 4 DTE0 Description 0 Data transfer disabled 1 Data transfer enabled (Initial value) Bits 3 and 1—Data Transfer Interrupt Enable B (DTIEB): These bits enable or disable an interrupt to the CPU or DTC when transfer is interrupted.
Section 7 DMA Controller (Not Supported in the H8S/2321) Bit 2—Data Transfer Interrupt Enable 1A (DTIE1A): Enables or disables the channel 1 transfer end interrupt. Bit 2 DTIE1A Description 0 Transfer end interrupt disabled 1 Transfer end interrupt enabled (Initial value) Bit 0—Data Transfer Interrupt Enable 0A (DTIE0A): Enables or disables the channel 0 transfer end interrupt. Bit 0 DTIE0A Description 0 Transfer end interrupt disabled 1 Transfer end interrupt enabled (Initial value) Rev.6.
Section 7 DMA Controller (Not Supported in the H8S/2321) 7.4 Register Descriptions (3) 7.4.1 DMA Write Enable Register (DMAWER) The DMAC can activate the DTC with a transfer end interrupt, rewrite the channel on which the transfer ended using a DTC chain transfer, and reactivate the DTC. DMAWER applies restrictions so that specific bits of DMACR for the specific channel, and also DMATCR and DMABCR, can be changed to prevent inadvertent rewriting of registers other than those for the channel concerned.
Section 7 DMA Controller (Not Supported in the H8S/2321) Bit : 7 6 5 4 3 2 1 0 — — — — WE1B WE1A WE0B WE0A Initial value : 0 0 0 0 0 0 0 0 R/W — — — — R/W R/W R/W R/W : DMAWER is an 8-bit readable/writable register that controls enabling or disabling of writes to DMACR, DMABCR, and DMATCR by the DTC. DMAWER is initialized to H'00 by a reset, and in hardware standby mode. Bits 7 to 4—Reserved: Read-only bits, always read as 0.
Section 7 DMA Controller (Not Supported in the H8S/2321) Bit 1—Write Enable 0B (WE0B): Enables or disables writes to all bits in DMACR0B, bits 9, 5, and 1 in DMABCR, and bit 4 in DMATCR, by the DTC.
Section 7 DMA Controller (Not Supported in the H8S/2321) 7.4.2 Bit DMA Terminal Control Register (DMATCR) : 7 6 5 4 3 2 1 0 — — TEE1 TEE0 — — — — Initial value : 0 0 0 0 0 0 0 0 R/W — — R/W R/W — — — — : DMATCR is an 8-bit readable/writable register that controls enabling or disabling of DMAC transfer end pin output. A port can be set for output automatically, and a transfer end signal output, by setting the appropriate bit.
Section 7 DMA Controller (Not Supported in the H8S/2321) 7.4.3 Module Stop Control Register (MSTPCR) MSTPCRH Bit MSTPCRL : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR is a 16-bit readable/writable register that performs module stop mode control.
Section 7 DMA Controller (Not Supported in the H8S/2321) 7.5 Operation 7.5.1 Transfer Modes Table 7.5 lists the DMAC modes. Table 7.
Section 7 DMA Controller (Not Supported in the H8S/2321) Operation in each mode is summarized below. Sequential Mode: In response to a single transfer request, the specified number of transfers are carried out, one byte or one word at a time. An interrupt request can be sent to the CPU or DTC when the specified number of transfers have been completed. One address is specified as 24 bits, and the other as 16 bits. The transfer direction is programmable.
Section 7 DMA Controller (Not Supported in the H8S/2321) • External request In response to a single transfer request, the specified number of transfers are carried out, one byte or one word at a time. An interrupt request can be sent to the CPU or DTC when the specified number of transfers have been completed. Both addresses are specified as 24 bits. Block Transfer Mode: In response to a single transfer request, a block transfer of the specified block size is carried out.
Section 7 DMA Controller (Not Supported in the H8S/2321) MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is incremented or decremented by 1 or 2 each time a byte or word is transferred. IOAR specifies the lower 16 bits of the other address. The 8 bits above IOAR have a value of H'FF. Figure 7.3 illustrates operation in sequential mode.
Section 7 DMA Controller (Not Supported in the H8S/2321) Transfer requests (activation sources) consist of A/D converter conversion end interrupts, external requests, SCI transmission data empty/reception data full interrupts, and TPU channel 0 to 5 compare match/input capture A interrupts. External requests can be set for channel B only. Figure 7.4 shows an example of the setting procedure for sequential mode. [1] Set each bit in DMABCRH. • Clear the FAE bit to 0 to select short address mode.
Section 7 DMA Controller (Not Supported in the H8S/2321) 7.5.3 Idle Mode Idle mode can be specified by setting the RPE bit and DTIE bit in DMACR to 1. In idle mode, one byte or word is transferred in response to a single transfer request, and this is executed the number of times specified in ETCR. One address is specified by MAR, and the other by IOAR. The transfer direction can be specified by the DTDIR bit in DMACR. Table 7.7 summarizes register functions in idle mode. Table 7.
Section 7 DMA Controller (Not Supported in the H8S/2321) Figure 7.5 illustrates operation in idle mode. MAR Transfer IOAR 1 byte or word transfer performed in response to 1 transfer request Figure 7.5 Operation in Idle Mode The number of transfers is specified as 16 bits in ETCR. ETCR is decremented by 1 each time a transfer is executed, and when its value reaches H'0000, the DTE bit is cleared and transfer ends. If the DTIE bit is set to 1 at this time, an interrupt request is sent to the CPU or DTC.
Section 7 DMA Controller (Not Supported in the H8S/2321) Figure 7.6 shows an example of the setting procedure for idle mode. [1] Set each bit in DMABCRH. • Clear the FAE bit to 0 to select short address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit. Idle mode setting Set DMABCRH [1] [2] Set the transfer source address and transfer destination address in MAR and IOAR. [3] Set the number of transfers in ETCR.
Section 7 DMA Controller (Not Supported in the H8S/2321) 7.5.4 Repeat Mode Repeat mode can be specified by setting the RPE bit in DMACR to 1, and clearing the DTIE bit to 0. In repeat mode, MAR is updated after each byte or word transfer in response to a single transfer request, and this is executed the number of times specified in ETCR. On completion of the specified number of transfers, MAR and ETCRL are automatically restored to their original settings and operation continues.
Section 7 DMA Controller (Not Supported in the H8S/2321) MAR specifies the start address of the transfer source or transfer destination as 24 bits. MAR is incremented or decremented by 1 or 2 each time a byte or word is transferred. IOAR specifies the lower 16 bits of the other address. The 8 bits above IOAR have a value of H'FF. The number of transfers is specified as 8 bits by ETCRH and ETCRL. The maximum number of transfers, when H'00 is set in both ETCRH and ETCRL, is 256.
Section 7 DMA Controller (Not Supported in the H8S/2321) Figure 7.7 illustrates operation in repeat mode. Address T Transfer IOAR 1 byte or word transfer performed in response to 1 transfer request Address B Legend: Address T = L Address B = L + (–1)DTID · (2DTSZ · (N –1)) Where : L = Value set in MAR N = Value set in ETCR Figure 7.
Section 7 DMA Controller (Not Supported in the H8S/2321) Figure 7.8 shows an example of the setting procedure for repeat mode. [1] Set each bit in DMABCRH. • Clear the FAE bit to 0 to select short address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit. Repeat mode setting Set DMABCRH [1] [2] Set the transfer source address and transfer destination address in MAR and IOAR. [3] Set the number of transfers in both ETCRH and ETCRL.
Section 7 DMA Controller (Not Supported in the H8S/2321) 7.5.5 Single Address Mode Single address mode can only be specified for channel B. This mode can be specified by setting the SAE bit in DMABCR to 1 in short address mode. One address is specified by MAR, and the other is set automatically to the data transfer acknowledge pin (DACK). The transfer direction can be specified by the DTDIR bit in DMACR. Table 7.9 summarizes register functions in single address mode. Table 7.
Section 7 DMA Controller (Not Supported in the H8S/2321) Figure 7.9 illustrates operation in single address mode (when sequential mode is specified). Address T Transfer DACK 1 byte or word transfer performed in response to 1 transfer request Address B Legend: Address T = L Address B = L + (–1)DTID · (2DTSZ · (N–1)) Where : L = Value set in MAR N = Value set in ETCR Figure 7.9 Operation in Single Address Mode (When Sequential Mode is Specified) Rev.6.00 Sep.
Section 7 DMA Controller (Not Supported in the H8S/2321) Figure 7.10 shows an example of the setting procedure for single address mode (when sequential mode is specified). Single address mode setting Set DMABCRH Set transfer source and transfer destination addresses [1] [1] Set each bit in DMABCRH. • Clear the FAE bit to 0 to select short address mode. • Set the SAE bit to 1 to select single address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit.
Section 7 DMA Controller (Not Supported in the H8S/2321) 7.5.6 Normal Mode In normal mode, transfer is performed with channels A and B used in combination. Normal mode can be specified by setting the FAE bit in DMABCR to 1 and clearing the BLKE bit in DMACRA to 0. In normal mode, MAR is updated after each byte or word transfer in response to a single transfer request, and this is executed the number of times specified in ETCRA.
Section 7 DMA Controller (Not Supported in the H8S/2321) Figure 7.11 illustrates operation in normal mode. Address TA Transfer Address TB Address BB Address BA Legend: Address Address Address Address Where : TA TB BA BB LA LB N = LA = LB = LA + SAIDE · (–1)SAID · (2DTSZ · (N–1)) = LB + DAIDE · (–1)DAID · (2DTSZ · (N–1)) = Value set in MARA = Value set in MARB = Value set in ETCRA Figure 7.11 Operation in Normal Mode Transfer requests (activation sources) are external requests and auto-requests.
Section 7 DMA Controller (Not Supported in the H8S/2321) For setting details, see section 7.3.4, DMA Control Register (DMACR). Figure 7.12 shows an example of the setting procedure for normal mode. [1] Set each bit in DMABCRH. • Set the FAE bit to 1 to select full address mode. • Specify enabling or disabling of internal interrupt clearing with the DTA bit. Normal mode setting Set DMABCRH [1] [2] Set the transfer source address in MARA, and the transfer destination address in MARB.
Section 7 DMA Controller (Not Supported in the H8S/2321) 7.5.7 Block Transfer Mode In block transfer mode, transfer is performed with channels A and B used in combination. Block transfer mode can be specified by setting the FAE bit in DMABCR and the BLKE bit in DMACRA to 1. In block transfer mode, a transfer of the specified block size is carried out in response to a single transfer request, and this is executed the specified number of times.
Section 7 DMA Controller (Not Supported in the H8S/2321) MARA and MARB specify the start addresses of the transfer source and transfer destination, respectively, as 24 bits. MAR can be incremented or decremented by 1 or 2 each time a byte or word is transferred, or can be fixed. Incrementing, decrementing, or holding a fixed value can be set separately for MARA and MARB. Whether a block is to be designated for MARA or for MARB is specified by the BLKDIR bit in DMACRA.
Section 7 DMA Controller (Not Supported in the H8S/2321) Address TB Address TA 1st block 2nd block Block area Transfer Consecutive transfer of M bytes or words is performed in response to one request Address BB Nth block Address BA Legend: Address Address Address Address Where : TA TB BA BB LA LB N M = LA = LB = LA + SAIDE · (–1)SAID · (2DTSZ · (M·N–1)) = LB + DAIDE · (–1)DAID · (2DTSZ · (N–1)) = Value set in MARA = Value set in MARB = Value set in ETCRB = Value set in ETCRAH and ETCRAL Figure 7
Section 7 DMA Controller (Not Supported in the H8S/2321) Address TA Address TB Block area Transfer 1st block Consecutive transfer of M bytes or words is performed in response to one request Address BA 2nd block Nth block Address BB Legend: Address Address Address Address Where : TA TB BA BB LA LB N M = LA = LB = LA + SAIDE · (–1)SAID · (2DTSZ · (N–1)) = LB + DAIDE · (–1)DAID · (2DTSZ · (M·N–1)) = Value set in MARA = Value set in MARB = Value set in ETCRB = Value set in ETCRAH and ETCRAL Figure 7
Section 7 DMA Controller (Not Supported in the H8S/2321) ETCRB is decremented by 1 after every block transfer, and when the count reaches H'0000 the DTE bit is cleared and transfer ends. If the DTIE bit is set to 1 at this point, an interrupt request is sent to the CPU or DTC. Figure 7.15 shows the operation flow in block transfer mode.
Section 7 DMA Controller (Not Supported in the H8S/2321) Transfer requests (activation sources) consist of A/D converter conversion end interrupts, external requests, SCI transmission data empty and reception data full interrupts, and TPU channel 0 to 5 compare match/input capture A interrupts. For details, see section 7.3.4, DMA Control Register (DMACR). Figure 7.16 shows an example of the setting procedure for block transfer mode. [1] Set each bit in DMABCRH.
Section 7 DMA Controller (Not Supported in the H8S/2321) 7.5.8 DMAC Activation Sources DMAC activation sources consist of internal interrupts, external requests, and auto-requests. The activation sources that can be specified depend on the transfer mode and the channel, as shown in table 7.12. Table 7.
Section 7 DMA Controller (Not Supported in the H8S/2321) unless the prescribed register is accessed in a DMA transfer. If the same interrupt is used as an activation source for more than one channel, the interrupt request flag is cleared when the highestpriority channel is activated first. Transfer requests for other channels are held pending in the DMAC, and activation is carried out in order of priority.
Section 7 DMA Controller (Not Supported in the H8S/2321) In dual address mode, transfer is performed with the source address and destination address specified separately. In single address mode, on the other hand, transfer is performed between external space in which either the transfer source or the transfer destination is specified by an address, and an external device for which selection is performed by means of the DACK strobe, without regard to the address. Figure 7.
Section 7 DMA Controller (Not Supported in the H8S/2321) 7.5.9 Basic DMAC Bus Cycles An example of the basic DMAC bus cycle timing is shown in figure 7.18. In this example, wordsize transfer is performed from 16-bit , 2-state access space to 8-bit, 3-state access space. When the bus is transferred from the CPU to the DMAC, a source address read and destination address write are performed. The bus is not released in response to another bus request, etc., between these read and write operations.
Section 7 DMA Controller (Not Supported in the H8S/2321) 7.5.10 DMAC Bus Cycles (Dual Address Mode) Short Address Mode: Figure 7.19 shows a transfer example in which TEND output is enabled and byte-size short address mode transfer (sequential/idle/repeat mode) is performed from external 8-bit, 2-state access space to internal I/O space.
Section 7 DMA Controller (Not Supported in the H8S/2321) Full Address Mode (Cycle Steal Mode): Figure 7.20 shows a transfer example in which TEND output is enabled and word-size full address mode transfer (cycle steal mode) is performed from external 16-bit, 2-state access space to external 16-bit, 2-state access space. DMA read DMA write DMA read DMA write DMA read DMA write DMA dead φ Address bus RD HWR LWR TEND Bus release Bus release Bus release Last transfer cycle Bus release Figure 7.
Section 7 DMA Controller (Not Supported in the H8S/2321) Full Address Mode (Burst Mode): Figure 7.21 shows a transfer example in which TEND output is enabled and word-size full address mode transfer (burst mode) is performed from external 16bit, 2-state access space to external 16-bit, 2-state access space. DMA read DMA write DMA read DMA write DMA read DMA write DMA dead φ Address bus RD HWR LWR TEND Last transfer cycle Bus release Bus release Burst transfer Figure 7.
Section 7 DMA Controller (Not Supported in the H8S/2321) Full Address Mode (Block Transfer Mode): Figure 7.22 shows a transfer example in which TEND output is enabled and word-size full address mode transfer (block transfer mode) is performed from internal 16-bit, 1-state access space to external 16-bit, 2-state access space.
Section 7 DMA Controller (Not Supported in the H8S/2321) DREQ Pin Falling Edge Activation Timing: Set the DTA bit for the channel for which the DREQ pin is selected to 1. Figure 7.23 shows an example of DREQ pin falling edge activated normal mode transfer.
Section 7 DMA Controller (Not Supported in the H8S/2321) Figure 7.24 shows an example of DREQ pin falling edge activated block transfer mode transfer.
Section 7 DMA Controller (Not Supported in the H8S/2321) DREQ Level Activation Timing (Normal Mode): Set the DTA bit for the channel for which the DREQ pin is selected to 1. Figure 7.25 shows an example of DREQ level activated normal mode transfer.
Section 7 DMA Controller (Not Supported in the H8S/2321) Figure 7.26 shows an example of DREQ level activated block transfer mode transfer.
Section 7 DMA Controller (Not Supported in the H8S/2321) 7.5.11 DMAC Bus Cycles (Single Address Mode) Single Address Mode (Read): Figure 7.27 shows a transfer example in which TEND output is enabled and byte-size single address mode transfer (read) is performed from external 8-bit, 2-state access space to an external device. DMA read DMA read DMA read DMA DMA read dead φ Address bus RD DACK TEND Bus release Bus release Bus release Bus Last transfer release cycle Bus release Figure 7.
Section 7 DMA Controller (Not Supported in the H8S/2321) Figure 7.28 shows a transfer example in which TEND output is enabled and word-size single address mode transfer (read) is performed from external 8-bit, 2-state access space to an external device. DMA read DMA read DMA read DMA dead φ Address bus RD DACK TEND Bus release Bus release Bus release Last transfer cycle Bus release Figure 7.
Section 7 DMA Controller (Not Supported in the H8S/2321) Single Address Mode (Write): Figure 7.29 shows a transfer example in which TEND output is enabled and byte-size single address mode transfer (write) is performed from an external device to external 8-bit, 2-state access space. DMA write DMA write DMA write DMA DMA write dead φ Address bus HWR LWR DACK TEND Bus release Bus release Bus release Bus Last transfer release cycle Bus release Figure 7.
Section 7 DMA Controller (Not Supported in the H8S/2321) Figure 7.30 shows a transfer example in which TEND output is enabled and word-size single address mode transfer (write) is performed from an external device to external 8-bit, 2-state access space. DMA write DMA write DMA write DMA dead φ Address bus HWR LWR DACK TEND Bus release Bus release Bus release Last transfer cycle Bus release Figure 7.
Section 7 DMA Controller (Not Supported in the H8S/2321) DREQ Pin Falling Edge Activation Timing: Set the DTA bit for the channel for which the DREQ pin is selected to 1. Figure 7.31 shows an example of DREQ pin falling edge activated single address mode transfer.
Section 7 DMA Controller (Not Supported in the H8S/2321) resumes after the end of the single cycle, DREQ pin low level sampling is performed again, and this operation is repeated until the transfer ends. DREQ Pin Low Level Activation Timing: Set the DTA bit for the channel for which the DREQ pin is selected to 1. Figure 7.32 shows an example of DREQ pin low level activated single address mode transfer.
Section 7 DMA Controller (Not Supported in the H8S/2321) When the DREQ pin low level is sampled while acceptance by means of the DREQ pin is possible, the request is held in the DMAC. Then, when activation is initiated in the DMAC, the request is cleared. After the end of the single cycle, acceptance resumes, DREQ pin low level sampling is performed again, and this operation is repeated until the transfer ends. 7.5.
Section 7 DMA Controller (Not Supported in the H8S/2321) Figure 7.34 shows an example of single address transfer using the write data buffer function. In this example, the CPU program area is in on-chip memory. DMA read DMA single CPU read DMA single CPU read φ Internal address Internal read signal External address RD DACK Figure 7.
Section 7 DMA Controller (Not Supported in the H8S/2321) If transfer requests are issued simultaneously for more than one channel, or if a transfer request for another channel is issued during a transfer, when the bus is released the DMAC selects the highest-priority channel from among those issuing a request according to the priority order shown in table 7.13. During burst transfer, or when one block is being transferred in block transfer, the channel will not be changed until the end of the transfer.
Section 7 DMA Controller (Not Supported in the H8S/2321) 7.5.14 Relation Between the DMAC and External Bus Requests, Refresh Cycles, and the DTC There can be no break between a DMA cycle read and a DMA cycle write. This means that a refresh cycle, external bus release cycle, or DTC cycle is not generated between the external read and external write in a DMA cycle.
Section 7 DMA Controller (Not Supported in the H8S/2321) 7.5.15 NMI Interrupts and DMAC When an NMI interrupt is requested, burst mode transfer in full address mode is interrupted. An NMI interrupt does not affect the operation of the DMAC in other modes. In full address mode, transfer is enabled for a channel when both the DTE bit and the DTME bit are set to 1. With burst mode setting, the DTME bit is cleared when an NMI interrupt is requested.
Section 7 DMA Controller (Not Supported in the H8S/2321) 7.5.16 Forced Termination of DMAC Operation If the DTE bit for the channel currently operating is cleared to 0, the DMAC stops on completion of the 1-byte or 1-word transfer in progress. DMAC operation resumes when the DTE bit is set to 1 again. In full address mode, the same applies to the DTME bit. Figure 7.37 shows the procedure for forcibly terminating DMAC operation by software.
Section 7 DMA Controller (Not Supported in the H8S/2321) 7.5.17 Clearing Full Address Mode Figure 7.38 shows the procedure for releasing and initializing a channel designated for full address mode. After full address mode has been cleared, the channel can be set to another transfer mode using the appropriate setting procedure.
Section 7 DMA Controller (Not Supported in the H8S/2321) 7.6 Interrupts The sources of interrupts generated by the DMAC are transfer end and transfer break. Table 7.14 shows the interrupt sources and their priority order. Table 7.
Section 7 DMA Controller (Not Supported in the H8S/2321) 7.7 Usage Notes DMAC Register Access during Operation: Except for forced termination, the operating (including transfer waiting state) channel setting should not be changed. The operating channel setting should only be changed when transfer is disabled. Also, MAC registers should not be written to in a DMA transfer. DMAC register reads during operation (including the transfer waiting state) are described below.
Section 7 DMA Controller (Not Supported in the H8S/2321) (b) If a DMAC transfer cycle occurs immediately after a DMAC register read cycle, the DMAC register is read as shown in figure 7.41. DMA transfer cycle CPU longword read MAR upper word read MAR lower word read DMA read DMA write φ DMA internal address DMA control Idle DMA register operation [1] Transfe source Transfer destination Read Write Idle [2] Note: The lower word of MAR is the updated value after the operation in [1]. Figure 7.
Section 7 DMA Controller (Not Supported in the H8S/2321) Write Data Buffer Function: When the WDBE bit of BCRL in the bus controller is set to 1, enabling the write data buffer function, dual address transfer external write cycles or single address transfers and internal accesses (on-chip memory or internal I/O registers) are executed in parallel.
Section 7 DMA Controller (Not Supported in the H8S/2321) DMA read DMA write φ Internal address Internal read signal Internal write signal External address HWR, LWR TEND Not output External write by CPU, etc. Figure 7.42 Example in Which Low Level is Not Output at TEND Pin Activation by Falling Edge on DREQ Pin: DREQ pin falling edge detection is performed in synchronization with DMAC internal operations.
Section 7 DMA Controller (Not Supported in the H8S/2321) Internal Interrupt after End of Transfer: When the DTE bit is cleared to 0 at the end of a transfer or by a forcible termination, the selected internal interrupt request will be sent to the CPU or DTC even if DTA is set to 1. Also, if internal DMAC activation has already been initiated when operation is forcibly terminated, the transfer is executed but flag clearing is not performed for the selected internal interrupt even if DTA is set to 1.
Section 7 DMA Controller (Not Supported in the H8S/2321) Rev.6.00 Sep.
Section 8 Data Transfer Controller Section 8 Data Transfer Controller 8.1 Overview The chip includes a data transfer controller (DTC). The DTC can be activated for data transfer by an interrupt or software. 8.1.
Section 8 Data Transfer Controller 8.1.2 Block Diagram Figure 8.1 shows a block diagram of the DTC. The DTC’s register information is stored in the on-chip RAM*. A 32-bit bus connects the DTC to the on-chip RAM (1 kbyte), enabling 32-bit, 1-state reading and writing of DTC register information. Note: * When the DTC is used, the RAME bit in SYSCR must be set to 1.
Section 8 Data Transfer Controller 8.1.3 Register Configuration Table 8.1 summarizes the DTC registers. Table 8.
Section 8 Data Transfer Controller 8.2 Register Descriptions 8.2.1 DTC Mode Register A (MRA) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 SM1 SM0 DM1 DM0 MD1 MD0 DTS Sz Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined — — — — — — — — MRA is an 8-bit register that controls the DTC operating mode.
Section 8 Data Transfer Controller Bits 3 and 2—DTC Mode (MD1, MD0): These bits specify the DTC transfer mode. Bit 3 MD1 Bit 2 MD0 Description 0 0 Normal mode 1 Repeat mode 0 Block transfer mode 1 — 1 Bit 1—DTC Transfer Mode Select (DTS): Specifies whether the source side or the destination side is set to be a repeat area or block area, in repeat mode or block transfer mode.
Section 8 Data Transfer Controller Bit 7—DTC Chain Transfer Enable (CHNE): Specifies chain transfer. With chain transfer, a number of data transfers can be performed consecutively in response to a single transfer request. In data transfer with CHNE set to 1, determination of the end of the specified number of transfers, clearing of the interrupt source flag, and clearing of DTCER are not performed. When CHNE is set to 1, the chain transfer condition can be selected with the CHNS bit.
Section 8 Data Transfer Controller 8.2.3 Bit DTC Source Address Register (SAR) : 23 22 21 20 19 ––– 4 3 2 1 0 ––– Initial value : R/W : Unde- Unde- Unde- Unde- Undefined fined fined fined fined — — — — — ––– ––– Unde- Unde- Unde- Unde- Undefined fined fined fined fined — — — — — SAR is a 24-bit register that designates the source address of data to be transferred by the DTC. For word-size transfer, specify an even source address. 8.2.
Section 8 Data Transfer Controller 8.2.
Section 8 Data Transfer Controller 8.2.7 DTC Enable Registers (DTCER) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 DTCE7 DTCE6 DTCE5 DTCE4 DTCE3 DTCE2 DTCE1 DTCE0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W The DTC enable registers comprise six 8-bit readable/writable registers, DTCERA to DTCERF, with bits corresponding to the interrupt sources that can activate the DTC. These bits enable or disable DTC service for the corresponding interrupt sources.
Section 8 Data Transfer Controller 8.2.8 DTC Vector Register (DTVECR) Bit : 7 6 5 4 3 2 1 0 SWDTE DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0 Initial value : R/W : 0 0 0 0 0 0 0 0 R/(W) R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Note: * Bits DTVEC6 to DTVEC0 can be written to when SWDTE = 0. DTVECR is an 8-bit readable/writable register that enables or disables DTC activation by software, and sets a vector number for the software activation interrupt.
Section 8 Data Transfer Controller 8.2.9 Module Stop Control Register (MSTPCR) MSTPCRH Bit MSTPCRL : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR is a 16-bit readable/writable register that performs module stop mode control.
Section 8 Data Transfer Controller Figure 8.2 shows a flowchart of DTC operation, and table 8.2 summarizes the chain transfer conditions (combinations for performing the second and third transfers are omitted).
Section 8 Data Transfer Controller Table 8.
Section 8 Data Transfer Controller Table 8.
Section 8 Data Transfer Controller 8.3.2 Activation Sources The DTC operates when activated by an interrupt or by a write to DTVECR by software. An interrupt request can be directed to the CPU or DTC, as designated by the corresponding DTCER bit. An interrupt becomes a DTC activation source when the corresponding bit is set to 1, and a CPU interrupt source when the bit is cleared to 0.
Section 8 Data Transfer Controller Source flag clearance Clear control Clear DTCER Clear request On-chip supporting module IRQ interrupt Interrupt request Selection circuit Select DTVECR DTC Interrupt controller CPU Interrupt mask Figure 8.3 Block Diagram of DTC Activation Source Control When an interrupt has been designated a DTC activation source, existing CPU mask level and interrupt controller priorities have no effect.
Section 8 Data Transfer Controller Table 8.
Section 8 Data Transfer Controller Interrupt Source Origin of Interrupt Source TGI3A (GR3A compare match/ input capture) TPU channel 3 Vector Number Vector Address DTCE* Priority 48 H'0460 DTCEC5 High TGI3B (GR3B compare match/ input capture) 49 H'0462 DTCEC4 TGI3C (GR3C compare match/ input capture) 50 H'0464 DTCEC3 TGI3D (GR3D compare match/ input capture) 51 H'0466 DTCEC2 56 H'0470 DTCEC1 57 H'0472 DTCEC0 72 H'0490 DTCEE7 DMTEND0B (DMAC transfer complete 1 73 H'0492 D
Section 8 Data Transfer Controller Origin of Interrupt Source Vector Number Vector Address DTCE* Priority SCI channel 0 81 H'04A2 DTCEE3 High 82 H'04A4 DTCEE2 85 H'04AA DTCEE1 TXI1 (transmit-data-empty 1) SCI channel 1 86 H'04AC DTCEE0 RXI2 (receive-data-full 2) SCI 89 H'04B2 DTCEF7 TXI2 (transmit-data-empty 2) channel 2 90 H'04B4 DTCEF6 Interrupt Source RXI0 (receive-data-full 0) TXI0 (transmit-data-empty 0) RXI1 (receive-data-full 1) 1 Low Notes: 1.
Section 8 Data Transfer Controller 8.3.4 Location of Register Information in Address Space Figure 8.5 shows how the register information should be located in the address space. Locate the MRA, SAR, MRB, DAR, CRA, and CRB registers, in that order, from the start address of the register information (contents of the vector address). In the case of chain transfer, register information should be located in consecutive areas. Locate the register information in the on-chip RAM (addresses: H'FFF800 to H'FFFBFF).
Section 8 Data Transfer Controller 8.3.5 Normal Mode In normal mode, one operation transfers one byte or one word of data. From 1 to 65,536 transfers can be specified. Once the specified number of transfers have ended, a CPU interrupt can be requested. Table 8.6 lists the register information in normal mode and figure 8.6 shows the memory map in normal mode. Table 8.
Section 8 Data Transfer Controller 8.3.6 Repeat Mode In repeat mode, one operation transfers one byte or one word of data. From 1 to 256 transfers can be specified. Once the specified number of transfers have ended, the initial state of the transfer counter and the address register specified as the repeat area is restored, and transfer is repeated. In repeat mode the transfer counter value does not reach H'00, and therefore CPU interrupts cannot be requested when DISEL = 0. Table 8.
Section 8 Data Transfer Controller 8.3.7 Block Transfer Mode In block transfer mode, one operation transfers one block of data. Either the transfer source or the transfer destination is designated as a block area. The block size is 1 to 256. When the transfer of one block ends, the initial state of the block size counter and the address register specified as the block area is restored. The other address register is then incremented, decremented, or left fixed. From 1 to 65,536 transfers can be specified.
Section 8 Data Transfer Controller First block SAR or DAR · · · Block area Transfer Nth block Figure 8.8 Memory Map in Block Transfer Mode Rev.6.00 Sep.
Section 8 Data Transfer Controller 8.3.8 Chain Transfer Setting the CHNE bit to 1 enables a number of data transfers to be performed consecutively in response to a single transfer request. It is also possible, by setting both the CHNE bit and CHNS bit to 1, to specify execution of chain transfer only when the transfer counter value is 0. SAR, DAR, CRA, CRB, MRA, and MRB, which define data transfers, can be set independently. Figure 8.9 shows the memory map for chain transfer.
Section 8 Data Transfer Controller 8.3.9 Operation Timing Figures 8.10 to 8.12 show examples of DTC operation timing. φ DTC activation request DTC request Data transfer Vector read Address Read Write Transfer information read Transfer information write Figure 8.10 DTC Operation Timing (Example in Normal Mode or Repeat Mode) φ DTC activation request DTC request Data transfer Vector read Address Read Write Read Write Transfer information read Transfer information write Figure 8.
Section 8 Data Transfer Controller φ DTC activation request DTC request Data transfer Data transfer Read Write Read Write Vector read Address Transfer information read Transfer Transfer information information write read Transfer information write Figure 8.12 DTC Operation Timing (Example of Chain Transfer) 8.3.10 Number of DTC Execution States Table 8.9 lists execution phases for a single DTC data transfer, and table 8.10 shows the number of states required for each execution phase. Table 8.
Section 8 Data Transfer Controller Table 8.
Section 8 Data Transfer Controller 8.3.11 Procedures for Using DTC Activation by Interrupt: The procedure for using the DTC with interrupt activation is as follows: [1] Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM. [2] Set the start address of the register information in the DTC vector address. [3] Set the corresponding bit in DTCER to 1. [4] Set the enable bits for the interrupt sources to be used as the activation sources to 1.
Section 8 Data Transfer Controller 8.3.12 Examples of Use of the DTC Normal Mode: An example is shown in which the DTC is used to receive 128 bytes of data via the SCI. [1] Set MRA to fixed source address (SM1 = SM0 = 0), incrementing destination address (DM1 = 1, DM0 = 0), normal mode (MD1 = MD0 = 0), and byte size (Sz = 0). The DTS bit can have any value. Set MRB for one data transfer by one interrupt (CHNE = 0, DISEL = 0).
Section 8 Data Transfer Controller Chain Transfer: An example of DTC chain transfer is shown in which pulse output is performed using the PPG. Chain transfer can be used to perform pulse output data transfer and PPG output trigger cycle updating. Repeat mode transfer to the PPG’s NDR is performed in the first half of the chain transfer, and normal mode transfer to the TPU’s TGR in the second half.
Section 8 Data Transfer Controller Chain Transfer when Counter = 0: By executing a second data transfer, and performing resetting of the first data transfer, only when the counter value is 0, it is possible to perform 256 or more repeat transfers. An example is shown in which a 128-kbyte input buffer is configured. The input buffer is assumed to have been set to start at lower address H'0000. Figure 8.13 shows the memory map. [1] For the first transfer, set the normal mode for input data.
Section 8 Data Transfer Controller Input circuit Input buffer First data transfer register information Chain transfer (counter = 0) Second data transfer register information Upper 8 bits of DAR Figure 8.13 Chain Transfer when Counter = 0 Software Activation: An example is shown in which the DTC is used to transfer a block of 128 bytes of data by means of software activation. The transfer source address is H'1000 and the destination address is H'2000.
Section 8 Data Transfer Controller [4] Write 1 to the SWDTE bit and the vector number (H'60) to DTVECR. The write data is H'E0. [5] Read DTVECR again and check that it is set to the vector number (H'60). If it is not, this indicates that the write failed. This is presumably because an interrupt occurred between steps [3] and [4] and led to a different software activation. To activate this transfer, go back to step [3].
Section 8 Data Transfer Controller 8.5 Usage Notes Module Stop: When the MSTP14 bit in MSTPCR is set to 1, the DTC clock stops, and the DTC enters the module stop state. However, 1 cannot be written to the MSTP14 bit while the DTC is operating. On-Chip RAM: The MRA, MRB, SAR, DAR, CRA, and CRB registers are all located in on-chip RAM. When the DTC is used, the RAME bit in SYSCR must not be cleared to 0.
Section 8 Data Transfer Controller Rev.6.00 Sep.
Section 9 I/O Ports Section 9 I/O Ports 9.1 Overview The chip has 12 I/O ports (ports 1, 2, 3, 5, 6, and A to G), and one input-only port (port 4). Table 9.1 summarizes the port functions. The pins of each port also have other functions. Each port includes a data direction register (DDR) that controls input/output (not provided for the input-only port), a data register (DR) that stores output data, and a port register (PORT) used to read the pin states.
Section 9 I/O Ports Table 9.
Section 9 I/O Ports Port Description Port 5 • 4-bit I/O port Pins Mode 4*1 Mode 5*1 Mode 6 Mode 7 P53/ADTRG/IRQ7/WAIT/ BREQO I/O port also functioning as A/D converter input pin (ADTRG), and as interrupt input pin (IRQ7) when IRQPAS = 1, WAIT input pin when WAITE = 1, BREQOE = 0, WAITPS = 1, DDR = 0, and WAITE = 0, BREQOE = 1, BREQO output pin when BREQOPS = 1 P52/SCK2/IRQ6 I/O port also functioning as SCI (channel 2) I/O pins (TxD2, RxD2, SCK2), and as interrupt input pins (IRQ4 to IRQ6) when IRQP
Section 9 I/O Ports Port Description Port B • 8-bit I/O port Pins PB7/A15 to PB0/A8 Mode 4*1 Mode 5*1 Address output • Built-in MOS input pull-up Port C • 8-bit I/O port Mode 7 When DDR = 1: address output PC7/A7 to PC0/A0 Address output • Built-in MOS input pull-up Port D • 8-bit I/O port Mode 6 When DDR = I/O ports 0 (after reset): input port When DDR = I/O ports 0 (after reset): input port When DDR = 1: address output PD7/D15 to PD0/D8 Data bus input/output I/O ports PE7/D7 to PE0/D0 In
Section 9 I/O Ports Port Description Pins Mode 4*1 Mode 5*1 Mode 6 Port F • 8-bit I/O port PF1/BACK PF0/BREQ When BRLE = 1: BREQ input, BACK output Port G • 5-bit I/O port PG4/CS0 When DDR = 0*3: input port When DDR = 1*4: CS0 output PG3/CS1 When DDR = 0 (after reset): input port When BRLE = 0 (after reset): I/O port Mode 7 I/O ports I/O ports When CS167E = 0 and DDR = 1: output port When CS167E = 1 and DDR = 1: CS1 output PG2/CS2 When DDR = 0 (after reset): input port When CS25E = 0 and DD
Section 9 I/O Ports 9.2 Port 1 9.2.1 Overview Port 1 is an 8-bit I/O port. Port 1 pins also function as PPG output pins (PO15 to PO8), TPU I/O pins (TCLKA, TCLKB, TCLKC, TCLKD, TIOCA0, TIOCB0, TIOCC0, TIOCD0, TIOCA1, TIOCB1, TIOCA2, and TIOCB2), and DMAC* output pins (DACK0 and DACK1). Port 1 pin functions are the same in all operating modes. Port 1 uses Schmitt-triggered input. Figure 9.1 shows the port 1 pin configuration. Note: * Not supported in the H8S/2321.
Section 9 I/O Ports 9.2.2 Register Configuration Table 9.2 shows the port 1 register configuration. Table 9.2 Port 1 Registers Name Abbreviation R/W Initial Value Address* Port 1 data direction register P1DDR W H'00 H'FEB0 Port 1 data register P1DR R/W H'00 H'FF60 Port 1 register PORT1 R Undefined H'FF50 Note: * Lower 16 bits of the address.
Section 9 I/O Ports Port 1 Data Register (P1DR) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 P17DR P16DR P15DR P14DR P13DR P12DR P11DR P10DR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W P1DR is an 8-bit readable/writable register that stores output data for the port 1 pins (P17 to P10). P1DR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode.
Section 9 I/O Ports 9.2.3 Pin Functions Port 1 pins also function as PPG output pins (PO15 to PO8), TPU I/O pins (TCLKA, TCLKB, TCLKC, TCLKD, TIOCA0, TIOCB0, TIOCC0, TIOCD0, TIOCA1, TIOCB1, TIOCA2, and TIOCB2), and DMAC* output pins (DACK0 and DACK1). Port 1 pin functions are shown in table 9.3. Note: * The DMAC is not supported in the H8S/2321. Table 9.
Section 9 I/O Ports Pin Selection Method and Pin Functions P16/PO14/ TIOCA2 The pin function is switched as shown below according to the combination of the TPU channel 2 setting (by bits MD3 to MD0 in TMDR2, bits IOA3 to IOA0 in TIOR2, and bits CCLR1 and CCLR0 in TCR2), bit NDER14 in NDERH, and bit P16DDR.
Section 9 I/O Ports Pin Selection Method and Pin Functions P15/PO13/ TIOCB1/TCLKC The pin function is switched as shown below according to the combination of the TPU channel 1 setting (by bits MD3 to MD0 in TMDR1, bits IOB3 to IOB0 in TIOR1, and bits CCLR1 and CCLR0 in TCR1), bits TPSC2 to TPSC0 in TCR0, TCR2, TCR4, and TCR5, bit NDER13 in NDERH, and bit P15DDR.
Section 9 I/O Ports Pin Selection Method and Pin Functions P14/PO12/ TIOCA1 The pin function is switched as shown below according to the combination of the TPU channel 1 setting (by bits MD3 to MD0 in TMDR1, bits IOA3 to IOA0 in TIOR1, and bits CCLR1 and CCLR0 in TCR1), bit NDER12 in NDERH, and bit P14DDR.
Section 9 I/O Ports Pin Selection Method and Pin Functions P13/PO11/ TIOCD0/TCLKB The pin function is switched as shown below according to the combination of the TPU channel 0 setting (by bits MD3 to MD0 in TMDR0, bits IOD3 to IOD0 in TIOR0L, and bits CCLR2 to CCLR0 in TCR0), bits TPSC2 to TPSC0 in TCR0 to TCR2, bit NDER11 in NDERH, and bit P13DDR.
Section 9 I/O Ports Pin Selection Method and Pin Functions P12/PO10/ TIOCC0/TCLKA The pin function is switched as shown below according to the combination of the TPU channel 0 setting (by bits MD3 to MD0 in TMDR0, bits IOC3 to IOC0 in TIOR0L, and bits CCLR2 to CCLR0 in TCR0), bits TPSC2 to TPSC0 in TCR0 to TCR5, bit NDER10 in NDERH, and bit P12DDR.
Section 9 I/O Ports Pin Selection Method and Pin Functions P11/PO9/TIOCB0/ 2 DACK1* The pin function is switched as shown below according to the combination of the TPU channel 0 setting (by bits MD3 to MD0 in TMDR0, bits IOB3 to IOB0 in TIOR0H, and bits CCLR2 to CCLR0 in TCR0), bit NDER9 in NDERH, bit 2 SAE1* in DMABCRH, and bit P11DDR.
Section 9 I/O Ports Pin Selection Method and Pin Functions P10/PO8/TIOCA0/ 2 DACK0* The pin function is switched as shown below according to the combination of the TPU channel 0 setting (by bits MD3 to MD0 in TMDR0, bits IOA3 to IOA0 in TIOR0H, and bits CCLR2 to CCLR0 in TCR0), bit NDER8 in NDERH, bit 2 SAE0* in DMABCRH, and bit P10DDR.
Section 9 I/O Ports 9.3 Port 2 9.3.1 Overview Port 2 is an 8-bit I/O port. Port 2 pins also function as PPG output pins (PO7 to PO0), TPU I/O pins (TIOCA3, TIOCB3, TIOCC3, TIOCD3, TIOCA4, TIOCB4, TIOCA5, and TIOCB5) and 8-bit timer I/O pins (TMRI0, TMCI0, TMO0, TMRI1, TMCI1, TMO1). Port 2 pin functions are the same in all operating modes. Port 2 uses Schmitt-triggered input. Figure 9.2 shows the port 2 pin configuration.
Section 9 I/O Ports 9.3.2 Register Configuration Table 9.4 shows the port 2 register configuration. Table 9.4 Port 2 Registers Name Abbreviation R/W Initial Value Address* Port 2 data direction register P2DDR W H'00 H'FEB1 Port 2 data register P2DR R/W H'00 H'FF61 Port 2 register PORT2 R Undefined H'FF51 Note: * Lower 16 bits of the address.
Section 9 I/O Ports Port 2 Data Register (P2DR) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 P27DR P26DR P25DR P24DR P23DR P22DR P21DR P20DR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W P2DR is an 8-bit readable/writable register that stores output data for the port 2 pins (P27 to P20). P2DR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode.
Section 9 I/O Ports 9.3.3 Pin Functions Port 2 pins also function as PPG output pins (PO7 to PO0) and TPU I/O pins (TIOCA3, TIOCB3, TIOCC3, TIOCD3, TIOCA4, TIOCB4, TIOCA5, and TIOCB5), and 8-bit timer I/O pins (TMRI0, TMCI0, TMO0, TMRI1, TMCI1, and TMO1). Port 2 pin functions are shown in table 9.5. Table 9.
Section 9 I/O Ports Pin Selection Method and Pin Functions P26/PO6/TIOCA5/ TMO0 The pin function is switched as shown below according to the combination of the TPU channel 5 setting (by bits MD3 to MD0 in TMDR5, bits IOA3 to IOA0 in TIOR5, and bits CCLR1 and CCLR0 in TCR5), bit NDER6 in NDERL, bits OS3 to OS0 in TCSR0, and bit P26DDR.
Section 9 I/O Ports Pin Selection Method and Pin Functions P25/PO5/TIOCB4/ TMCI1 This pin is used as the 8-bit timer external clock input pin when an external clock is selected with bits CKS2 to CKS0 in TCR1. The pin function is switched as shown below according to the combination of the TPU channel 4 setting (by bits MD3 to MD0 in TMDR4, bits IOB3 to IOB0 in TIOR4, and bits CCLR1 and CCLR0 in TCR4), bit NDER5 in NDERL, and bit P25DDR.
Section 9 I/O Ports Pin Selection Method and Pin Functions P24/PO4/TIOCA4/ TMRI1 This pin is used as the 8-bit timer counter reset pin when bits CCLR1 and CCLR0 in TCR1 are both set to 1. The pin function is switched as shown below according to the combination of the TPU channel 4 setting (by bits MD3 to MD0 in TMDR4, bits IOA3 to IOA0 in TIOR4, and bits CCLR1 and CCLR0 in TCR4), bit NDER4 in NDERL, and bit P24DDR.
Section 9 I/O Ports Pin Selection Method and Pin Functions P23/PO3/TIOCD3/ TMCI0 This pin is used as the 8-bit timer external clock input pin when an external clock is selected with bits CKS2 to CKS0 in TCR0. The pin function is switched as shown below according to the combination of the TPU channel 3 setting (by bits MD3 to MD0 in TMDR3, bits IOD3 to IOD0 in TIOR3L, and bits CCLR2 to CCLR0 in TCR3), bit NDER3 in NDERL, and bit P23DDR.
Section 9 I/O Ports Pin Selection Method and Pin Functions P22/PO2/TIOCC3/ TMRI0 This pin is used as the 8-bit timer counter reset pin when bits CCLR1 and CCLR0 in TCR0 are both set to 1. The pin function is switched as shown below according to the combination of the TPU channel 3 setting (by bits MD3 to MD0 in TMDR3, bits IOC3 to IOC0 in TIOR3L, and bits CCLR2 to CCLR0 in TCR3), bit NDER2 in NDERL, and bit P22DDR.
Section 9 I/O Ports Pin Selection Method and Pin Functions P21/PO1/TIOCB3 The pin function is switched as shown below according to the combination of the TPU channel 3 setting (by bits MD3 to MD0 in TMDR3, bits IOB3 to IOB0 in TIOR3H, and bits CCLR2 to CCLR0 in TCR3), bit NDER1 in NDERL, and bit P21DDR.
Section 9 I/O Ports Pin Selection Method and Pin Functions P20/PO0/TIOCA3 The pin function is switched as shown below according to the combination of the TPU channel 3 setting (by bits MD3 to MD0 in TMDR3, bits IOA3 to IOA0 in TIOR3H, and bits CCLR2 to CCLR0 in TCR3), bit NDER0 in NDERL, and bit P20DDR.
Section 9 I/O Ports 9.4 Port 3 9.4.1 Overview Port 3 is a 6-bit I/O port. Port 3 pins also function as SCI I/O pins (TxD0, RxD0, SCK0, TxD1, RxD1, and SCK1). Port 3 pin functions are the same in all operating modes. Figure 9.3 shows the port 3 pin configuration. Port 3 pins P35 (I/O) / SCK1 (I/O) P34 (I/O) / SCK0 (I/O) P33 (I/O) / RxD1 (input) Port 3 P32 (I/O) / RxD0 (input) P31 (I/O) / TxD1 (output) P30 (I/O) / TxD0 (output) Figure 9.3 Port 3 Pin Functions 9.4.2 Register Configuration Table 9.
Section 9 I/O Ports Port 3 Data Direction Register (P3DDR) Bit : 7 6 — — 5 4 3 2 1 0 P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR Initial value : Undefined Undefined 0 0 0 0 0 0 R/W W W W W W W : — — P3DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 3. Bits 7 and 6 are reserved. P3DDR cannot be read; if it is, an undefined value will be read.
Section 9 I/O Ports Port 3 Register (PORT3) Bit : 7 6 5 4 3 2 1 0 — — P35 —* P34 —* P33 —* P32 —* P31 —* P30 —* R R R R R R Initial value : Undefined Undefined R/W : — — Note: * Determined by state of pins P35 to P30. PORT3 is an 8-bit read-only register that shows the pin states. Writing of output data for the port 3 pins (P35 to P30) must always be performed on P3DR. Bits 7 and 6 are reserved; they return an undefined value if read, and cannot be modified.
Section 9 I/O Ports 9.4.3 Pin Functions Port 3 pins also function as SCI I/O pins (TxD0, RxD0, SCK0, TxD1, RxD1, and SCK1). Port 3 pin functions are shown in table 9.7. Table 9.7 Port 3 Pin Functions Pin Selection Method and Pin Functions P35/SCK1 The pin function is switched as shown below according to the combination of bit C/A in the SCI1 SMR, bits CKE0 and CKE1 in SCR, and bit P35DDR.
Section 9 I/O Ports Pin Selection Method and Pin Functions P33/RxD1 The pin function is switched as shown below according to the combination of bit RE in the SCI1 SCR, and bit P33DDR. RE 0 P33DDR Pin function 1 0 1 — P33 input pin P33 output pin* RxD1 input pin Note: * When P33ODR = 1, the pin becomes an NMOS open-drain output. P32/RxD0 The pin function is switched as shown below according to the combination of bit RE in the SCI0 SCR, and bit P32DDR.
Section 9 I/O Ports 9.5 Port 4 9.5.1 Overview Port 4 is an 8-bit input-only port. Port 4 pins also function as A/D converter analog input pins (AN0 to AN7) and D/A converter analog output pins (DA0 and DA1). Port 4 pin functions are the same in all operating modes. Figure 9.4 shows the port 4 pin configuration.
Section 9 I/O Ports 9.5.2 Register Configuration Table 9.8 shows the port 4 register configuration. Port 4 is an input-only port, and does not have a data direction register or data register. Table 9.8 Port 4 Register Name Abbreviation R/W Initial Value Address* Port 4 register PORT4 R Undefined H'FF53 Note: * Lower 16 bits of the address. Port 4 Register (PORT4): The pin states are always read when a port 4 read is performed.
Section 9 I/O Ports 9.6 Port 5 9.6.1 Overview Port 5 is a 4-bit I/O port. Port 5 pins also function as SCI I/O pins (TxD2, RxD2, and SCK2), the A/D converter input pin (ADTRG), interrupt input pins (IRQ4 to IRQ7), and bus control signal I/O pins (WAIT and BREQO). The pin functions can be switched by means of settings in PFCR2 and SYSCR. IRQ4 to IRQ7 only are Schmitt-triggered inputs. Figure 9.5 shows the port 5 pin configuration.
Section 9 I/O Ports 9.6.2 Register Configuration Table 9.9 shows the port 5 register configuration. Table 9.9 Port 5 Registers 1 Address* Name Abbreviation R/W Initial Value Port 5 data direction register P5DDR W H'FEB4 Port 5 data register P5DR R/W H'0* 2 H'0* Port 5 register PORT5 R Undefined H'FF54 2 H'FF64 Port function control register 2 PFCR2 R/W H'30 H'FFAC System control register SYSCR R/W H'01 H'FF39 Notes: 1. Lower 16 bits of the address. 2. Value of bits 3 to 0.
Section 9 I/O Ports Port 5 Data Register (P5DR) Bit : 7 6 5 4 3 2 1 0 — — — — P53DR P52DR P51DR P50DR 0 0 0 0 R/W R/W R/W R/W Initial value : Undefined Undefined Undefined Undefined R/W : — — — — P5DR is an 8-bit readable/writable register that stores output data for the port 5 pins (P53 to P50). Bits 7 to 4 are reserved; they return an undefined value if read, and cannot be modified. P5DR is initialized to H'0 (bits 3 to 0) by a reset, and in hardware standby mode.
Section 9 I/O Ports Port Function Control Register 2 (PFCR2) Bit : 7 6 5 WAITPS BREQOPS CS167E Initial value : R/W : 4 3 2 1 0 CS25E ASOD — — — 0 0 1 1 0 0 0 0 R/W R/W R/W R/W R/W R R R PFCR2 is an 8-bit readable/writable register that performs I/O port control. PFCR2 is initialized to H'30 by a reset, and in hardware standby mode. Bit 7—WAIT Pin Select (WAITPS): Selects the WAIT input pin.
Section 9 I/O Ports System Control Register (SYSCR) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 — — INTM1 INTM0 NMIEG 0 0 0 0 0 0 0 1 R/W — R/W R/W R/W R/W R/W R/W LWROD IRQPAS RAME SYSCR is an 8-bit readable/writable register that selects the interrupt control mode, controls the LWR pin, switches the IRQ4 to IRQ7 input pins, and selects the detected edge for NMI. SYSCR is initialized to H'01 by a reset, and in hardware standby mode.
Section 9 I/O Ports 9.6.3 Pin Functions Port 5 pins also function as SCI I/O pins (TxD2, RxD2, and SCK2), the A/D converter input pin (ADTRG), interrupt input pins (IRQ4 to IRQ7), and bus control signal I/O pins (WAIT and BREQO). Port 5 pin functions are shown in table 9.10. Table 9.
Section 9 I/O Ports Pin Selection Method and Pin Functions P51/RxD2/IRQ5 The pin function is switched as shown below according to the combination of bit RE in the SCI2 SCR, and bits IRQPAS and P51DDR. RE P51DDR Pin function 0 1 0 1 — P51 input pin P51 output pin RxD2 input pin IRQ5 interrupt input pin* Note: * IRQ5 input when IRQPAS = 1. P50/TxD2/IRQ4 The pin function is switched as shown below according to the combination of bit TE in the SCI2 SCR, and bits IRQPAS and P50DDR.
Section 9 I/O Ports 9.7 Port 6 9.7.1 Overview Port 6 is an 8-bit I/O port. Port 6 pins also function as interrupt input pins (IRQ0 to IRQ3), DMAC* I/O pins (DREQ0, TEND0, DREQ1, and TEND1), and bus control output pins (CS4 to CS7). The functions of pins P65 to P62 are the same in all operating modes, while the functions of pins P67, P66, P61, and P60 change according to the operating mode. Switching of CS4 to CS7 output can be performed by setting PFCR2. Pins P67 to P64 are Schmitt-triggered inputs.
Section 9 I/O Ports 9.7.2 Register Configuration Table 9.11 shows the port 6 register configuration. Table 9.11 Port 6 Registers Name Abbreviation R/W Initial Value Address* Port 6 data direction register P6DDR W H'00 H'FEB5 Port 6 data register P6DR R/W H'00 H'FF65 Port 6 register PORT6 R Undefined H'FF55 Port function control register 2 PFCR2 R/W H'30 H'FFAC Note: * Lower 16 bits of the address.
Section 9 I/O Ports Port 6 Data Register (P6DR) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 P67DR P66DR P65DR P64DR P63DR P62DR P61DR P60DR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W P6DR is an 8-bit readable/writable register that stores output data for the port 6 pins (P67 to P60). P6DR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode.
Section 9 I/O Ports Port Function Control Register 2 (PFCR2) Bit : 7 6 5 WAITPS BREQOPS CS167E Initial value : R/W : 4 3 2 1 0 CS25E ASOD — — — 0 0 1 1 0 0 0 0 R/W R/W R/W R/W R/W R R R PFCR2 is an 8-bit readable/writable register that performs I/O port control. PFCR2 is initialized to H'30 by a reset, and in hardware standby mode. Bit 7—WAIT Pin Select (WAITPS): Selects the WAIT input pin. For details, see section 9.6, Port 5.
Section 9 I/O Ports 9.7.3 Pin Functions Port 6 pins also function as interrupt input pins (IRQ0 to IRQ3), DMAC I/O pins (DREQ0, TEND0, DREQ1, and TEND1)*, and bus control output pins (CS4 to CS7). Port 6 pin functions are shown in table 9.12. Table 9.12 Port 6 Pin Functions Pin Selection Method and Pin Functions P67/IRQ3/CS7 The pin function is switched as shown below according to the combination of bits P67DDR and CS167E.
Section 9 I/O Ports Pin Selection Method and Pin Functions P63/TEND1* The pin function is switched as shown below according to the combination of bit TEE1* in the DMAC DMATCR, and bit P63DDR. TEE1* 0 1 P63DDR Pin function P62/DREQ1* 0 1 — P63 input pin P63 output pin TEND1 output* The pin function is switched as shown below according to bit P62DDR.
Section 9 I/O Ports 9.8 Port A 9.8.1 Overview Port A is an 8-bit I/O port. Port A pins also function as address bus outputs and interrupt input pins (IRQ4 to IRQ7). The pin functions change according to the operating mode. IRQ4 to IRQ7 input can be switched to P50 to P53 by setting the IRQPAS bit in SYSCR to 1. The address output or port output function can be selected by means of bits A23E to A20E in PFCR1. Port A has a built-in MOS input pull-up function that can be controlled by software.
Section 9 I/O Ports 9.8.2 Register Configuration Table 9.13 shows the port A register configuration. Table 9.
Section 9 I/O Ports Port A Data Register (PADR) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 PA7DR PA6DR PA5DR PA4DR PA3DR PA2DR PA1DR PA0DR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W PADR is an 8-bit readable/writable register that stores output data for the port A pins (PA7 to PA0). PADR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode.
Section 9 I/O Ports Port A MOS Pull-Up Control Register (PAPCR) Bit : 7 6 5 4 3 2 1 0 PA7PCR PA6PCR PA5PCR PA4PCR PA3PCR PA2PCR PA1PCR PA0PCR Initial value : R/W : 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W PAPCR is an 8-bit readable/writable register that controls the MOS input pull-up function incorporated into port A on an individual bit basis. All the bits are valid in modes 6 and 7, and bits 7 to 5 are valid in modes 4 and 5.
Section 9 I/O Ports Port Function Control Register 1 (PFCR1) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 — — — — A23E A22E A21E A20E 0 0 0 0 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W PFCR1 is an 8-bit readable/writable register that performs I/O port control. PFCR1 is initialized to H'0F by a reset, and in hardware standby mode. Bits 7 to 4—Reserved: Only 0 should be written to these bits. Bit 3—Address 23 Enable (A23E): Enables or disables address output 23 (A23).
Section 9 I/O Ports Bit 0—Address 20 Enable (A20E): Enables or disables address output 20 (A20). This bit is valid in modes 4 to 6. Bit 0 A20E Description 0 DR is output when PA4DDR = 1 1 A20 is output when PA4DDR = 1 (Initial value) System Control Register (SYSCR) Bit : 7 6 5 4 3 — — INTM1 INTM0 NMIEG 0 0 0 0 0 0 0 1 R/W — R/W R/W R/W R/W R/W R/W Initial value : R/W : 2 1 0 LWROD IRQPAS RAME Bit 7—Reserved: Only 0 should be written to this bit.
Section 9 I/O Ports Bit 2—LWR Output Disable (LWROD): Enables or disables LWR output. Bit 2 LWROD Description 0 PF3 is designated as LWR output pin 1 PF3 is designated as I/O port, and does not function as LWR output pin (Initial value) Bit 1—IRQ Port Switching Select (IRQPAS): Selects switching of input pins for IRQ4 to IRQ7. IRQ4 to IRQ7 input is always performed from one of the ports.
Section 9 I/O Ports Table 9.14 Port A Pin Functions Pin Selection Method and Pin Functions PA7/A23/IRQ7 The pin function is switched as shown below according to the combination of the operating mode and bits A23E and PA7DDR. Operating mode Modes 4 to 6 A23E PA7DDR Pin function 0 0 Mode 7 1 1 0 — 1 0 1 PA7 PA7 PA7 A23 PA7 input pin output pin input pin output pin input pin PA7 output 2 pin* IRQ7 interrupt input pin* 1 Notes: 1. IRQ7 input when IRQPAS = 0. 2.
Section 9 I/O Ports Pin Selection Method and Pin Functions PA4/A20/IRQ4 The pin function is switched as shown below according to the combination of the operating mode and bits A20E and PA4DDR. Operating mode Modes 4 and 5 A20E 0 PA4DDR 0 Mode 6 1 1 Mode 7 0 — 0 1 1 — 0 1 0 1 A20 PA4 PA4 PA4 A20 PA4 PA4 Pin function Setting PA4 pro- output output input output input output input output 2 hibited pin pin pin pin pin pin pin pin* 1 IRQ4 interrupt input pin* Notes: 1.
Section 9 I/O Ports 9.8.4 MOS Input Pull-Up Function Port A has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used by pins PA7 to PA5 in modes 4 and 5, and by all pins in modes 6 and 7. MOS input pull-up can be specified as on or off on an individual bit basis. When a PADDR bit is cleared to 0, setting the corresponding PAPCR bit to 1 turns on the MOS input pull-up for that pin.
Section 9 I/O Ports 9.9 Port B 9.9.1 Overview Port B is an 8-bit I/O port. Port B has an address bus output function, and the pin functions change according to the operating mode. Port B has a built-in MOS input pull-up function that can be controlled by software. Figure 9.8 shows the port B pin configuration.
Section 9 I/O Ports 9.9.2 Register Configuration Table 9.16 shows the port B register configuration. Table 9.16 Port B Registers Name Abbreviation R/W Initial Value Address* Port B data direction register PBDDR W H'00 H'FEBA Port B data register PBDR R/W H'00 H'FF6A Port B register PORTB R Undefined H'FF5A Port B MOS pull-up control register PBPCR R/W H'00 H'FF71 Note: * Lower 16 bits of the address.
Section 9 I/O Ports Port B Data Register (PBDR) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 PB7DR PB6DR PB5DR PB4DR PB3DR PB2DR PB1DR PB0DR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W PBDR is an 8-bit readable/writable register that stores output data for the port B pins (PB7 to PB0). PBDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode.
Section 9 I/O Ports Port B MOS Pull-Up Control Register (PBPCR) Bit : 7 6 5 4 3 2 1 0 PB7PCR PB6PCR PB5PCR PB4PCR PB3PCR PB2PCR PB1PCR PB0PCR Initial value : R/W : 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W PBPCR is an 8-bit readable/writable register that controls the MOS input pull-up function incorporated into port B on an individual bit basis.
Section 9 I/O Ports Mode 6: In mode 6, port B pins function as address outputs or input ports. Input or output can be specified on an individual bit basis. Setting a PBDDR bit to 1 makes the corresponding port B pin an address output, while clearing the bit to 0 makes the pin an input port. Port B pin functions in mode 6 are shown in figure 9.10.
Section 9 I/O Ports 9.9.4 MOS Input Pull-Up Function Port B has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in modes 6 and 7, and can be specified as on or off on an individual bit basis. When a PBDDR bit is cleared to 0 in mode 6 or 7, setting the corresponding PBPCR bit to 1 turns on the MOS input pull-up for that pin. The MOS input pull-up function is in the off state after a reset, and in hardware standby mode.
Section 9 I/O Ports 9.10 Port C 9.10.1 Overview Port C is an 8-bit I/O port. Port C has an address bus output function, and the pin functions change according to the operating mode. Port C has a built-in MOS input pull-up function that can be controlled by software. Figure 9.12 shows the port C pin configuration.
Section 9 I/O Ports 9.10.2 Register Configuration Table 9.18 shows the port C register configuration. Table 9.18 Port C Registers Name Abbreviation R/W Initial Value Address* Port C data direction register PCDDR W H'00 H'FEBB Port C data register PCDR R/W H'00 H'FF6B Port C register PORTC R Undefined H'FF5B Port C MOS pull-up control register PCPCR R/W H'00 H'FF72 Note: * Lower 16 bits of the address.
Section 9 I/O Ports Port C Data Register (PCDR) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 PC7DR PC6DR PC5DR PC4DR PC3DR PC2DR PC1DR PC0DR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W PCDR is an 8-bit readable/writable register that stores output data for the port C pins (PC7 to PC0). PCDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode.
Section 9 I/O Ports Port C MOS Pull-Up Control Register (PCPCR) Bit : 7 6 5 4 3 2 1 0 PC7PCR PC6PCR PC5PCR PC4PCR PC3PCR PC2PCR PC1PCR PC0PCR Initial value : R/W : 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W PCPCR is an 8-bit readable/writable register that controls the MOS input pull-up function incorporated into port C on an individual bit basis.
Section 9 I/O Ports Mode 6: In mode 6, port C pins function as address outputs or input ports. Input or output can be specified on an individual bit basis. Setting a PCDDR bit to 1 makes the corresponding port C pin an address output, while clearing the bit to 0 makes the pin an input port. Port C pin functions in mode 6 are shown in figure 9.14.
Section 9 I/O Ports 9.10.4 MOS Input Pull-Up Function Port C has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in modes 6 and 7, and can be specified as on or off on an individual bit basis. When a PCDDR bit is cleared to 0 in mode 6 or 7, setting the corresponding PCPCR bit to 1 turns on the MOS input pull-up for that pin. The MOS input pull-up function is in the off state after a reset, and in hardware standby mode.
Section 9 I/O Ports 9.11 Port D 9.11.1 Overview Port D is an 8-bit I/O port. Port D has a data bus I/O function, and the pin functions change according to the operating mode. Port D has a built-in MOS input pull-up function that can be controlled by software. Figure 9.16 shows the port D pin configuration.
Section 9 I/O Ports 9.11.2 Register Configuration Table 9.20 shows the port D register configuration. Table 9.20 Port D Registers Name Abbreviation R/W Initial Value Address* Port D data direction register PDDDR W H'00 H'FEBC Port D data register PDDR R/W H'00 H'FF6C Port D register PORTD R Undefined H'FF5C Port D MOS pull-up control register PDPCR R/W H'00 H'FF73 Note: * Lower 16 bits of the address.
Section 9 I/O Ports Port D Data Register (PDDR) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 PD7DR PD6DR PD5DR PD4DR PD3DR PD2DR PD1DR PD0DR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W PDDR is an 8-bit readable/writable register that stores output data for the port D pins (PD7 to PD0). PDDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode.
Section 9 I/O Ports Port D MOS Pull-Up Control Register (PDPCR) Bit : 7 6 5 4 3 2 1 0 PD7PCR PD6PCR PD5PCR PD4PCR PD3PCR PD2PCR PD1PCR PD0PCR Initial value : R/W : 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W PDPCR is an 8-bit readable/writable register that controls the MOS input pull-up function incorporated into port D on an individual bit basis.
Section 9 I/O Ports 9.11.3 Pin Functions Modes 4 to 6: In modes 4 to 6, port D pins are automatically designated as data I/O pins. Port D pin functions in modes 4 to 6 are shown in figure 9.17. D15 (I/O) D14 (I/O) D13 (I/O) Port D D12 (I/O) D11 (I/O) D10 (I/O) D9 (I/O) D8 (I/O) Figure 9.17 Port D Pin Functions (Modes 4 to 6) Mode 7: In mode 7, port D pins function as I/O ports. Input or output can be specified for each pin on an individual bit basis.
Section 9 I/O Ports 9.11.4 MOS Input Pull-Up Function Port D has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in mode 7, and can be specified as on or off on an individual bit basis. When a PDDDR bit is cleared to 0 in mode 7, setting the corresponding PDPCR bit to 1 turns on the MOS input pull-up for that pin. The MOS input pull-up function is in the off state after a reset, and in hardware standby mode.
Section 9 I/O Ports 9.12 Port E 9.12.1 Overview Port E is an 8-bit I/O port. Port E has a data bus I/O function, and the pin functions change according to the operating mode and whether 8-bit or 16-bit bus mode is selected. Port E has a built-in MOS input pull-up function that can be controlled by software. Figure 9.19 shows the port E pin configuration.
Section 9 I/O Ports 9.12.2 Register Configuration Table 9.22 shows the port E register configuration. Table 9.22 Port E Registers Name Abbreviation R/W Initial Value Address* Port E data direction register PEDDR W H'00 H'FEBD Port E data register PEDR R/W H'00 H'FF6D Port E register PORTE R Undefined H'FF5D Port E MOS pull-up control register PEPCR R/W H'00 H'FF74 Note: * Lower 16 bits of the address.
Section 9 I/O Ports Port E Data Register (PEDR) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 PE7DR PE6DR PE5DR PE4DR PE3DR PE2DR PE1DR PE0DR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W PEDR is an 8-bit readable/writable register that stores output data for the port E pins (PE7 to PE0). PEDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode.
Section 9 I/O Ports Port E MOS Pull-Up Control Register (PEPCR) Bit : 7 6 5 4 3 2 1 0 PE7PCR PE6PCR PE5PCR PE4PCR PE3PCR PE2PCR PE1PCR PE0PCR Initial value : R/W : 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W PEPCR is an 8-bit readable/writable register that controls the MOS input pull-up function incorporated into port E on an individual bit basis.
Section 9 I/O Ports Port E 8-bit bus mode 16-bit bus mode PE7 (I/O) D7 (I/O) PE6 (I/O) D6 (I/O) PE5 (I/O) D5 (I/O) PE4 (I/O) D4 (I/O) PE3 (I/O) D3 (I/O) PE2 (I/O) D2 (I/O) PE1 (I/O) D1 (I/O) PE0 (I/O) D0 (I/O) Figure 9.20 Port E Pin Functions (Modes 4 to 6) Mode 7: In mode 7, port E pins function as I/O ports. Input or output can be specified for each pin on a bit-by-bit basis.
Section 9 I/O Ports 9.12.4 MOS Input Pull-Up Function Port E has a built-in MOS input pull-up function that can be controlled by software. This MOS input pull-up function can be used in modes 4 to 6 when 8-bit bus mode is selected, or in mode 7, and can be specified as on or off on an individual bit basis. When a PEDDR bit is cleared to 0 in mode 4, 5, or 6 when 8-bit bus mode is selected, or in mode 7, setting the corresponding PEPCR bit to 1 turns on the MOS input pull-up for that pin.
Section 9 I/O Ports 9.13 Port F 9.13.1 Overview Port F is an 8-bit I/O port. Port F pins also function as bus control signal input/output pins (AS, RD, HWR, LWR, LCAS*, WAIT, BREQO, BREQ, and BACK) and the system clock (φ) output pin. The AS, LWR, and BREQO output pins can be switched by means of settings in PFCR2 and SYSCR. Figure 9.22 shows the port F pin configuration. Note: * LCAS is not supported in the H8S/2321.
Section 9 I/O Ports 9.13.2 Register Configuration Table 9.24 shows the port F register configuration. Table 9.24 Port F Registers 1 Address* Name Abbreviation R/W Initial Value Port F data direction register PFDDR W H'80/H'00* H'FEBE Port F data register PFDR R/W H'00 H'FF6E Port F register PORTF R Undefined H'FF5E 2 Port function control register 2 PFCR2 R/W H'30 H'FFAC System control register SYSCR R/W H'01 H'FF39 Notes: 1. Lower 16 bits of the address. 2.
Section 9 I/O Ports Port F Data Register (PFDR) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 PF7DR PF6DR PF5DR PF4DR PF3DR PF2DR PF1DR PF0DR 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W PFDR is an 8-bit readable/writable register that stores output data for the port F pins (PF7 to PF0). PFDR is initialized to H'00 by a reset, and in hardware standby mode. It retains its prior state in software standby mode.
Section 9 I/O Ports Port Function Control Register 2 (PFCR2) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 WAITPS BREQOPS CS167E CS25E ASOD — — — 0 0 1 1 0 0 0 0 R/W R/W R/W R/W R/W R R R PFCR2 is an 8-bit readable/writable register that performs I/O port control. PFCR2 is initialized to H'30 by a reset, and in hardware standby mode. Bit 7—WAIT Pin Select (WAITPS): Selects the WAIT input pin.
Section 9 I/O Ports Bits 2 to 0—Reserved: These bits are always read as 0. System Control Register (SYSCR) Bit : Initial value : R/W : 7 6 5 4 3 — — INTM1 INTM0 NMIEG 2 1 0 0 0 0 0 0 0 0 1 R/W — R/W R/W R/W R/W R/W R/W LWROE IRQPAS RAME SYSCR is an 8-bit readable/writable register that selects the interrupt control mode, controls the LWR pin, switches the IRQ4 to IRQ7 input pins, and selects the detected edge for NMI.
Section 9 I/O Ports 9.13.3 Pin Functions Port F pins also function as bus control signal input/output pins (AS, RD, HWR, LWR, LCAS*, WAIT, BREQO, BREQ, and BACK) and the system clock (φ) output pin. The pin functions differ between modes 4 to 6, and mode 7. Port F pin functions are shown in table 9.25. Note: * The LCAS is not supported in the H8S/2321. Table 9.25 Port F Pin Functions Pin Selection Method and Pin Functions PF7/φ The pin function is switched as shown below according to bit PF7DDR.
Section 9 I/O Ports Pin Selection Method and Pin Functions PF3/LWR The pin function is switched as shown below according to the operating mode, bit PF3DDR, and bit LWROD in SYSCR.
Section 9 I/O Ports Pin Selection Method and Pin Functions PF0/BREQ The pin function is switched as shown below according to the combination of the operating mode, and bits BRLE and PF0DDR. Operating Mode Modes 4 to 6 BRLE 0 PF0DDR Pin function 9.14 Port G 9.14.1 Overview Mode 7 1 — 0 1 — 0 1 PF0 input pin PF0 output pin BREQ input pin PF0 input pin PF0 output pin Port G is a 5-bit I/O port. Port G pins also function as bus control signal output pins (CS0 to CS3, and CAS*).
Section 9 I/O Ports 9.14.2 Register Configuration Table 9.26 shows the port G register configuration. Table 9.26 Port G Registers 2 1 Name Abbreviation R/W Initial Value* Address* Port G data direction register PGDDR W H'10/H'00* H'FEBF Port G data register PGDR R/W H'00 H'FF6F Port G register PORTG R Undefined H'FF5F Port function register 2 PFCR2 R/W H'30 H'FFAC 3 Notes: 1. Lower 16 bits of the address. 2. Value of bits 4 to 0. 3. Initial value depends on the mode.
Section 9 I/O Ports Port G Data Register (PGDR) Bit : 7 6 5 4 3 2 1 0 — — — PG4DR PG3DR PG2DR PG1DR PG0DR 0 0 0 0 0 R/W R/W R/W R/W R/W Initial value : Undefined Undefined Undefined R/W : — — — PGDR is an 8-bit readable/writable register that stores output data for the port G pins (PG4 to PG0). Bits 7 to 5 are reserved; they return an undefined value if read, and cannot be modified. PGDR is initialized to H'00 (bits 4 to 0) by a reset, and in hardware standby mode.
Section 9 I/O Ports Port Function Control Register 2 (PFCR2) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 WAITPS BREQOPS CS167E CS25E ASOD — — — 0 0 1 1 0 0 0 0 R/W R/W R/W R/W R/W R R R PFCR2 is an 8-bit readable/writable register that performs I/O port control. PFCR2 is initialized to H'30 by a reset, and in hardware standby mode. Bit 7—WAIT Pin Select (WAITPS): Selects the WAIT input pin. For details, see section 9.6, Port 5.
Section 9 I/O Ports 9.14.3 Pin Functions Port G pins also function as bus control signal output pins (CS0 to CS3, and CAS*). The pin functions are different in mode 7, and modes 4 to 6. Port G pin functions are shown in table 9.27. Note: * The CAS is not supported in the H8S/2321. Table 9.27 Port G Pin Functions Pin Selection Method and Pin Functions PG4/CS0 The pin function is switched as shown below according to the operating mode and bit PG4DDR.
Section 9 I/O Ports Pin Selection Method and Pin Functions PG1/CS3 The pin function is switched as shown below according to the operating mode and bits PG1DDR and CS25E. Operating Mode PG1DDR 0 CS25E — Pin function PG0/CAS* Modes 4 to 6 Mode 7 1 0 1 PG1 input PG1 output CS3 output pin pin pin 0 1 — — PG1 input PG1 output pin pin The pin function is switched as shown below according to the combination of the operating mode and bits RMTS2 to RMTS0* and PG0DDR.
Section 10 16-Bit Timer Pulse Unit (TPU) Section 10 16-Bit Timer Pulse Unit (TPU) 10.1 Overview The chip has an on-chip 16-bit timer pulse unit (TPU) that comprises six 16-bit timer channels. 10.1.
Section 10 16-Bit Timer Pulse Unit (TPU) • 26 interrupt sources ⎯ For channels 0 and 3, four compare match/input capture dual-function interrupts and one overflow interrupt can be requested independently ⎯ For channels 1, 2, 4, and 5, two compare match/input capture dual-function interrupts, one overflow interrupt, and one underflow interrupt can be requested independently • Automatic transfer of register data ⎯ Block transfer, 1-word data transfer, and 1-byte data transfer possible by data transfer contro
Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.1 lists the functions of the TPU. Table 10.
Section 10 16-Bit Timer Pulse Unit (TPU) Item Channel 1 Channel 2 Channel 3 Channel 4 Channel 5 DMAC* TGR0A activation compare match or input capture Channel 0 TGR1A compare match or input capture TGR2A compare match or input capture TGR3A compare match or input capture TGR4A compare match or input capture TGR5A compare match or input capture DTC TGR activation compare match or input capture TGR compare match or input capture TGR compare match or input capture TGR compare match or input capt
Section 10 16-Bit Timer Pulse Unit (TPU) 10.1.
Section 10 16-Bit Timer Pulse Unit (TPU) 10.1.3 Pin Configuration Table 10.2 summarizes the TPU pins. Table 10.
Section 10 16-Bit Timer Pulse Unit (TPU) Channel Name Symbol I/O Function 3 Input capture/out compare match A3 TIOCA3 I/O TGR3A input capture input/output compare output/PWM output pin Input capture/out compare match B3 TIOCB3 I/O TGR3B input capture input/output compare output/PWM output pin Input capture/out compare match C3 TIOCC3 I/O TGR3C input capture input/output compare output/PWM output pin Input capture/out compare match D3 TIOCD3 I/O TGR3D input capture input/output compare o
Section 10 16-Bit Timer Pulse Unit (TPU) 10.1.4 Register Configuration Table 10.3 summarizes the TPU registers. Table 10.
Section 10 16-Bit Timer Pulse Unit (TPU) 1 Channel Name Abbreviation R/W Initial Value Address* 3 Timer control register 3 TCR3 R/W H'00 H'FE80 Timer mode register 3 TMDR3 R/W H'C0 H'FE81 Timer I/O control register 3H TIOR3H R/W H'00 H'FE82 Timer I/O control register 3L TIOR3L R/W H'00 H'FE83 Timer interrupt enable register 3 TIER3 R/W H'FE84 Timer status register 3 TSR3 H'40 2 * R/(W) H'C0 Timer counter 3 TCNT3 R/W H'0000 H'FE86 4 5 All H'FE85 Timer general regist
Section 10 16-Bit Timer Pulse Unit (TPU) 10.2 Register Descriptions 10.2.
Section 10 16-Bit Timer Pulse Unit (TPU) Bits 7 to 5—Counter Clear 2 to 0 (CCLR2 to CCLR0): These bits select the TCNT counter clearing source.
Section 10 16-Bit Timer Pulse Unit (TPU) Bits 4 and 3—Clock Edge 1 and 0 (CKEG1, CKEG0): These bits select the input clock edge. When the input clock is counted using both edges, the input clock period is halved (e.g. φ/4 both edges = φ/2 rising edge). If phase counting mode is used on channels 1, 2, 4, and 5, this setting is ignored and the phase counting mode setting has priority.
Section 10 16-Bit Timer Pulse Unit (TPU) Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 0 0 0 0 Internal clock: counts on φ/1 1 Internal clock: counts on φ/4 1 0 Internal clock: counts on φ/16 1 Internal clock: counts on φ/64 0 External clock: counts on TCLKA pin input 1 External clock: counts on TCLKB pin input 0 External clock: counts on TCLKC pin input 1 External clock: counts on TCLKD pin input 1 0 1 (Initial value) Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 De
Section 10 16-Bit Timer Pulse Unit (TPU) Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 3 0 0 0 Internal clock: counts on φ/1 1 Internal clock: counts on φ/4 1 0 Internal clock: counts on φ/16 1 Internal clock: counts on φ/64 0 External clock: counts on TCLKA pin input 1 Internal clock: counts on φ/1024 0 Internal clock: counts on φ/256 1 Internal clock: counts on φ/4096 1 0 1 (Initial value) Channel Bit 2 TPSC2 Bit 1 TPSC1 Bit 0 TPSC0 Description 4 0 0 0 Inter
Section 10 16-Bit Timer Pulse Unit (TPU) 10.2.
Section 10 16-Bit Timer Pulse Unit (TPU) Bit 4—Buffer Operation A (BFA): Specifies whether TGRA is to operate in the normal way, or TGRA and TGRC are to be used together for buffer operation. When TGRC is used as a buffer register, TGRC input capture/output compare is not generated. In channels 1, 2, 4, and 5, which have no TGRC, bit 4 is reserved. It is always read as 0 and cannot be modified.
Section 10 16-Bit Timer Pulse Unit (TPU) 10.2.
Section 10 16-Bit Timer Pulse Unit (TPU) Bits 7 to 4— I/O Control B3 to B0 (IOB3 to IOB0) I/O Control D3 to D0 (IOD3 to IOD0): Bits IOB3 to IOB0 specify the function of TGRB. Bits IOD3 to IOD0 specify the function of TGRD.
Section 10 16-Bit Timer Pulse Unit (TPU) Channel Bit 7 Bit 6 Bit 5 Bit 4 IOD3 IOD2 IOD1 IOD0 0 0 0 0 0 1 1 0 Description TGR0D Output disabled is output Initial output is 0 compare output 2 register* 0 1 0 Output disabled 1 Initial output is 1 output 0 1 1 0 0 0 1 1 1 * * * 1 output at compare match Toggle output at compare match 1 1 (Initial value) 0 output at compare match 0 output at compare match 1 output at compare match Toggle output at compare match TGR0D Capture input i
Section 10 16-Bit Timer Pulse Unit (TPU) Channel Bit 7 Bit 6 Bit 5 Bit 4 IOB3 IOB2 IOB1 IOB0 1 0 0 0 0 1 1 0 Description TGR1B Output disabled is output Initial output is 0 compare output register 0 1 0 Output disabled 1 Initial output is 1 output 0 1 1 0 0 0 1 1 1 * * * 1 output at compare match Toggle output at compare match 1 1 (Initial value) 0 output at compare match 0 output at compare match 1 output at compare match Toggle output at compare match TGR1B is input capture r
Section 10 16-Bit Timer Pulse Unit (TPU) Channel Bit 7 Bit 6 Bit 5 Bit 4 IOB3 IOB2 IOB1 IOB0 3 0 0 0 0 1 0 1 Description TGR3B Output disabled is output Initial output is 0 compare output register 0 1 0 Output disabled 1 Initial output is 1 output 0 0 0 0 1 1 Note: 1 * * * 1 output at compare match 0 output at compare match 1 output at compare match Toggle output at compare match 1 1 0 output at compare match Toggle output at compare match 1 1 (Initial value) TGR3B is input
Section 10 16-Bit Timer Pulse Unit (TPU) Channel Bit 7 Bit 6 Bit 5 Bit 4 IOD3 IOD2 IOD1 IOD0 3 0 0 0 0 1 1 0 Description TGR3D Output disabled is output Initial output is 0 compare output 2 register* 0 1 0 Output disabled 1 Initial output is 1 output 0 1 1 0 0 0 1 1 1 * * * 1 output at compare match Toggle output at compare match 1 1 (Initial value) 0 output at compare match 0 output at compare match 1 output at compare match Toggle output at compare match TGR3D Capture input i
Section 10 16-Bit Timer Pulse Unit (TPU) Channel Bit 7 Bit 6 Bit 5 Bit 4 IOB3 IOB2 IOB1 IOB0 4 0 0 0 0 1 1 0 Description TGR4B Output disabled is output Initial output is 0 compare output register 0 1 0 Output disabled 1 Initial output is 1 output 0 1 1 0 0 0 1 * * * 1 1 1 output at compare match Toggle output at compare match 1 1 (Initial value) 0 output at compare match 0 output at compare match 1 output at compare match Toggle output at compare match TGR4B is input capture
Section 10 16-Bit Timer Pulse Unit (TPU) Bits 3 to 0— I/O Control A3 to A0 (IOA3 to IOA0) I/O Control C3 to C0 (IOC3 to IOC0): IOA3 to IOA0 specify the function of TGRA. IOC3 to IOC0 specify the function of TGRC.
Section 10 16-Bit Timer Pulse Unit (TPU) Channel Bit 3 Bit 2 Bit 1 Bit 0 IOC3 IOC2 IOC1 IOC0 0 0 0 0 0 1 0 1 Description TGR0C Output disabled is output Initial output is 0 compare output 1 register* 0 1 0 Output disabled 1 Initial output is 1 output 0 0 0 0 1 1 Note: 1 * * * 1 output at compare match 0 output at compare match 1 output at compare match Toggle output at compare match 1 1 0 output at compare match Toggle output at compare match 1 1 (Initial value) TGR0C Captur
Section 10 16-Bit Timer Pulse Unit (TPU) Channel Bit 3 Bit 2 Bit 1 Bit 0 IOA3 IOA2 IOA1 IOA0 1 0 0 0 0 1 0 1 Description TGR1A Output disabled is output Initial output is 0 compare output register 0 1 0 Output disabled 1 Initial output is 1 output 0 0 0 0 1 1 1 * * * 1 output at compare match 0 output at compare match 1 output at compare match Toggle output at compare match 1 1 0 output at compare match Toggle output at compare match 1 1 (Initial value) TGR1A is input capture
Section 10 16-Bit Timer Pulse Unit (TPU) Channel Bit 3 Bit 2 Bit 1 Bit 0 IOA3 IOA2 IOA1 IOA0 2 0 0 0 0 1 0 1 Description Output disabled TGR2A is output compare register Initial output is 0 output at compare match 0 output 1 output at compare match Toggle output at compare match 1 1 0 1 0 Output disabled 1 Initial output is 0 output at compare match 1 output 1 output at compare match 0 Toggle output at compare match 1 1 * 0 1 (Initial valu 0 TGR2A is Capture input Input capture a
Section 10 16-Bit Timer Pulse Unit (TPU) Channel Bit 3 Bit 2 Bit 1 Bit 0 IOC3 IOC2 IOC1 IOC0 3 0 0 0 0 1 0 1 Description TGR3C Output disabled is output Initial output is 0 compare output 1 register* 0 1 0 Output disabled 1 Initial output is 1 output 0 0 0 0 1 1 Note: 1 * * * 1 output at compare match 0 output at compare match 1 output at compare match Toggle output at compare match 1 1 0 output at compare match Toggle output at compare match 1 1 (Initial value) TGR3C Captur
Section 10 16-Bit Timer Pulse Unit (TPU) Channel Bit 3 Bit 2 Bit 1 Bit 0 IOA3 IOA2 IOA1 IOA0 4 0 0 0 0 1 1 0 Description TGR4A Output disabled is output Initial output is 0 compare output register 0 1 0 Output disabled 1 Initial output is 1 output 0 1 1 0 0 0 1 1 1 * * * 1 output at compare match Toggle output at compare match 1 1 (Initial value) 0 output at compare match 0 output at compare match 1 output at compare match Toggle output at compare match TGR4A is input capture r
Section 10 16-Bit Timer Pulse Unit (TPU) 10.2.
Section 10 16-Bit Timer Pulse Unit (TPU) Bit 5 TCIEU Description 0 Interrupt requests (TCIU) by TCFU disabled 1 Interrupt requests (TCIU) by TCFU enabled (Initial value) Bit 4—Overflow Interrupt Enable (TCIEV): Enables or disables interrupt requests (TCIV) by the TCFV bit when the TCFV bit in TSR is set to 1.
Section 10 16-Bit Timer Pulse Unit (TPU) Bit 1 TGIEB Description 0 Interrupt requests (TGIB) by TGFB disabled 1 Interrupt requests (TGIB) by TGFB enabled (Initial value) Bit 0—TGR Interrupt Enable A (TGIEA): Enables or disables interrupt requests (TGIA) by the TGFA bit when the TGFA bit in TSR is set to 1. Bit 0 TGIEA Description 0 Interrupt requests (TGIA) by TGFA disabled 1 Interrupt requests (TGIA) by TGFA enabled 10.2.
Section 10 16-Bit Timer Pulse Unit (TPU) The TSR registers are 8-bit registers that indicate the status of each channel. The TPU has six TSR registers, one for each channel. The TSR registers are initialized to H'C0 by a reset and in hardware standby mode. Bit 7—Count Direction Flag (TCFD): Status flag that shows the direction in which TCNT counts in channels 1, 2, 4, and 5. In channels 0 and 3, bit 7 is reserved. It is always read as 1 and cannot be modified.
Section 10 16-Bit Timer Pulse Unit (TPU) Bit 3—Input Capture/Output Compare Flag D (TGFD): Status flag that indicates the occurrence of TGRD input capture or compare match in channels 0 and 3. In channels 1, 2, 4, and 5, bit 3 is reserved. It is always read as 0 and cannot be modified.
Section 10 16-Bit Timer Pulse Unit (TPU) Bit 1—Input Capture/Output Compare Flag B (TGFB): Status flag that indicates the occurrence of TGRB input capture or compare match.
Section 10 16-Bit Timer Pulse Unit (TPU) 10.2.
Section 10 16-Bit Timer Pulse Unit (TPU) 10.2.7 Bit Timer General Registers (TGR) : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W The TGR registers are 16-bit registers with a dual function as output compare and input capture registers. The TPU has 16 TGR registers, four each for channels 0 and 3 and two each for channels 1, 2, 4, and 5.
Section 10 16-Bit Timer Pulse Unit (TPU) 10.2.8 Bit Timer Start Register (TSTR) : 7 6 5 4 3 2 1 0 — — CST5 CST4 CST3 CST2 CST1 CST0 Initial value : 0 0 0 0 0 0 0 0 R/W — — R/W R/W R/W R/W R/W R/W : TSTR is an 8-bit readable/writable register that selects operation/stoppage for channels 0 to 5. TSTR is initialized to H'00 by a reset, and in hardware standby mode. When setting the operating mode in TMDR or setting the count clock in TCR, first stop the TCNT counter.
Section 10 16-Bit Timer Pulse Unit (TPU) 10.2.9 Bit Timer Synchro Register (TSYR) : 7 6 5 4 3 2 1 0 — — SYNC5 SYNC4 SYNC3 SYNC2 SYNC1 SYNC0 Initial value : 0 0 0 0 0 0 0 0 R/W — — R/W R/W R/W R/W R/W R/W : TSYR is an 8-bit readable/writable register that selects independent operation or synchronous operation for the channel 0 to 4 TCNT counters. A channel performs synchronous operation when the corresponding bit in TSYR is set to 1.
Section 10 16-Bit Timer Pulse Unit (TPU) 10.2.10 Module Stop Control Register (MSTPCR) MSTPCRH Bit MSTPCRL : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR is a 16-bit readable/writable register that performs module stop mode control.
Section 10 16-Bit Timer Pulse Unit (TPU) 10.3 Interface to Bus Master 10.3.1 16-Bit Registers TCNT and TGR are 16-bit registers. As the data bus to the bus master is 16 bits wide, these registers can be read and written to in 16-bit units. These registers cannot be read or written to in 8-bit units; 16-bit access must always be used. An example of 16-bit register access operation is shown in figure 10.2. Internal data bus H Bus master L Module data bus Bus interface TCNTH TCNTL Figure 10.
Section 10 16-Bit Timer Pulse Unit (TPU) Internal data bus H Bus master L Module data bus Bus interface TCR Figure 10.3 8-Bit Register Access Operation [Bus Master ↔ TCR (Upper 8 Bits)] Internal data bus H Bus master L Module data bus Bus interface TMDR Figure 10.4 8-Bit Register Access Operation [Bus Master ↔ TMDR (Lower 8 Bits)] Internal data bus H Bus master L Module data bus Bus interface TCR TMDR Figure 10.5 8-Bit Register Access Operation [Bus Master ↔ TCR and TMDR (16 Bits)] Rev.6.
Section 10 16-Bit Timer Pulse Unit (TPU) 10.4 Operation 10.4.1 Overview Operation in each mode is outlined below. Normal Operation: Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of free-running operation, synchronous counting, and external event counting. Each TGR can be used as an input capture register or output compare register.
Section 10 16-Bit Timer Pulse Unit (TPU) 10.4.2 Basic Functions Counter Operation: When one of bits CST0 to CST5 is set to 1 in TSTR, the TCNT counter for the corresponding channel starts counting. TCNT can operate as a free-running counter, periodic counter, and so on. • Example of count operation setting procedure Figure 10.6 shows an example of the count operation setting procedure. [1] Select the counter clock with bits TPSC2 to TPSC0 in TCR.
Section 10 16-Bit Timer Pulse Unit (TPU) • Free-running count operation and periodic count operation Immediately after a reset, the TPU’s TCNT counters are all designated as free-running counters. When the relevant bit in TSTR is set to 1 the corresponding TCNT counter starts upcount operation as a free-running counter. When TCNT overflows (from H'FFFF to H'0000), the TCFV bit in TSR is set to 1. If the value of the corresponding TCIEV bit in TIER is 1 at this point, the TPU requests an interrupt.
Section 10 16-Bit Timer Pulse Unit (TPU) Counter cleared by TGR compare match TCNT value TGR H'0000 Time CST bit Flag cleared by software or DTC/DMAC* activation TGF Note: * The DMAC is not supported in the H8S/2321. Figure 10.8 Periodic Counter Operation Waveform Output by Compare Match: The TPU can perform 0, 1, or toggle output from the corresponding output pin using compare match. • Example of setting procedure for waveform output by compare match Figure 10.
Section 10 16-Bit Timer Pulse Unit (TPU) • Examples of waveform output operation Figure 10.10 shows an example of 0 output/1 output. In this example TCNT has been designated as a free-running counter, and settings have been made so that 1 is output by compare match A, and 0 is output by compare match B. When the set level and the pin level coincide, the pin level does not change. TCNT value H'FFFF TGRA TGRB Time H'0000 No change No change 1 output TIOCA TIOCB No change No change 0 output Figure 10.
Section 10 16-Bit Timer Pulse Unit (TPU) Input Capture Function: The TCNT value can be transferred to TGR on detection of the TIOC pin input edge. Rising edge, falling edge, or both edges can be selected as the detected edge. For channels 0, 1, 3, and 4, it is also possible to specify another channel’s counter input clock or compare match signal as the input capture source.
Section 10 16-Bit Timer Pulse Unit (TPU) • Example of input capture operation Figure 10.13 shows an example of input capture operation. In this example both rising and falling edges have been selected as the TIOCA pin input capture input edge, falling edge has been selected as the TIOCB pin input capture input edge, and counter clearing by TGRB input capture has been designated for TCNT.
Section 10 16-Bit Timer Pulse Unit (TPU) 10.4.3 Synchronous Operation In synchronous operation, the values in a number of TCNT counters can be rewritten simultaneously (synchronous presetting). Also, a number of TCNT counters can be cleared simultaneously by making the appropriate setting in TCR (synchronous clearing). Synchronous operation enables TGR to be incremented with respect to a single time base. Channels 0 to 5 can all be designated for synchronous operation.
Section 10 16-Bit Timer Pulse Unit (TPU) Example of Synchronous Operation: Figure 10.15 shows an example of synchronous operation. In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to 2, TGR0B compare match has been set as the channel 0 counter clearing source, and synchronous clearing has been set for the channel 1 and 2 counter clearing source. Three-phase PWM waveforms are output from pins TIOC0A, TIOC1A, and TIOC2A.
Section 10 16-Bit Timer Pulse Unit (TPU) 10.4.4 Buffer Operation Buffer operation, provided for channels 0 and 3, enables TGRC and TGRD to be used as buffer registers. Buffer operation differs depending on whether TGR has been designated as an input capture register or as a compare match register. Table 10.5 shows the register combinations used in buffer operation. Table 10.
Section 10 16-Bit Timer Pulse Unit (TPU) • When TGR is an input capture register When input capture occurs, the value in TCNT is transferred to TGR and the value previously held in the timer general register is transferred to the buffer register. This operation is illustrated in figure 10.17. Input capture signal Timer general register Buffer register TCNT Figure 10.17 Input Capture Buffer Operation Example of Buffer Operation Setting Procedure: Figure 10.
Section 10 16-Bit Timer Pulse Unit (TPU) Examples of Buffer Operation • When TGR is an output compare register Figure 10.19 shows an operation example in which PWM mode 1 has been designated for channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0 output at compare match B.
Section 10 16-Bit Timer Pulse Unit (TPU) • When TGR is an input capture register Figure 10.20 shows an operation example in which TGRA has been designated as an input capture register, and buffer operation has been designated for TGRA and TGRC. Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling edges have been selected as the TIOCA pin input capture input edge.
Section 10 16-Bit Timer Pulse Unit (TPU) 10.4.5 Cascaded Operation In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit counter. This function works by counting the channel 1 (channel 4) counter clock upon overflow/underflow of TCNT2 (TCNT5) as set in bits TPSC2 to TPSC0 in TCR. Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode. Table 10.6 shows the register combinations used in cascaded operation.
Section 10 16-Bit Timer Pulse Unit (TPU) Examples of Cascaded Operation: Figure 10.22 illustrates the operation when counting upon TCNT2 overflow/underflow has been set for TCNT1, TGR1A, and TGR2A have been designated as input capture registers, and TIOC pin rising edge has been selected. When a rising edge is input to the TIOCA1 and TIOCA2 pins simultaneously, the upper 16 bits of the 32-bit data are transferred to TGR1A, and the lower 16 bits to TGR2A.
Section 10 16-Bit Timer Pulse Unit (TPU) TCLKC TCLKD TCNT2 FFFD TCNT1 FFFE FFFF 0000 0000 0001 0002 0001 0001 0000 FFFF 0000 Figure 10.23 Example of Cascaded Operation (2) 10.4.6 PWM Modes In PWM mode, PWM waveforms are output from the output pins. 0, 1, or toggle output can be selected as the output level in response to compare match of each TGR. Designating TGR compare match as the counter clearing source enables the period to be set in that register.
Section 10 16-Bit Timer Pulse Unit (TPU) The correspondence between PWM output pins and registers is shown in table 10.7. Table 10.
Section 10 16-Bit Timer Pulse Unit (TPU) Example of PWM Mode Setting Procedure: Figure 10.24 shows an example of the PWM mode setting procedure. PWM mode Select counter clock [1] [1] Select the counter clock with bits TPSC2 to TPSC0 in TCR. At the same time, select the input clock edge with bits CKEG1 and CKEG0 in TCR. [2] Use bits CCLR2 to CCLR0 in TCR to select the TGR to be used as the TCNT clearing source.
Section 10 16-Bit Timer Pulse Unit (TPU) Examples of PWM Mode Operation: Figure 10.25 shows an example of PWM mode 1 operation. In this example, TGRA compare match is set as the TCNT clearing source, 0 is set for the TGRA initial output value and output value, and 1 is set as the TGRB output value. In this case, the value set in TGRA is used as the period, and the value set in TGRB as the duty. TCNT value TGRA Counter cleared by TGRA compare match TGRB H'0000 Time TIOCA Figure 10.
Section 10 16-Bit Timer Pulse Unit (TPU) Figure 10.26 shows an example of PWM mode 2 operation. In this example, synchronous operation is designated for channels 0 and 1, TGR1B compare match is set as the TCNT clearing source, and 0 is set for the initial output value and 1 for the output value of the other TGR registers (TGR0A to TGR0D, TGR1A), to output a 5-phase PWM waveform. In this case, the value set in TGR1B is used as the period, and the values set in the other TGR registers as the duty.
Section 10 16-Bit Timer Pulse Unit (TPU) Figure 10.27 shows examples of PWM waveform output with 0% duty and 100% duty in PWM mode.
Section 10 16-Bit Timer Pulse Unit (TPU) 10.4.7 Phase Counting Mode In phase counting mode, the phase difference between two external clock inputs is detected and TCNT is incremented/decremented accordingly. This mode can be set for channels 1, 2, 4, and 5. When phase counting mode is set, an external clock is selected as the counter input clock and TCNT operates as an up/down-counter regardless of the setting of bits TPSC2 to TPSC0 and bits CKEG1 and CKEG0 in TCR.
Section 10 16-Bit Timer Pulse Unit (TPU) Examples of Phase Counting Mode Operation: In phase counting mode, TCNT counts up or down according to the phase difference between two external clocks. There are four modes, according to the count conditions. • Phase counting mode 1 Figure 10.29 shows an example of phase counting mode 1 operation, and table 10.9 summarizes the TCNT up/down-count conditions.
Section 10 16-Bit Timer Pulse Unit (TPU) • Phase counting mode 2 Figure 10.30 shows an example of phase counting mode 2 operation, and table 10.10 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Up-count Down-count Time Figure 10.30 Example of Phase Counting Mode 2 Operation Table 10.
Section 10 16-Bit Timer Pulse Unit (TPU) • Phase counting mode 3 Figure 10.31 shows an example of phase counting mode 3 operation, and table 10.11 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Down-count Up-count Time Figure 10.31 Example of Phase Counting Mode 3 Operation Table 10.
Section 10 16-Bit Timer Pulse Unit (TPU) • Phase counting mode 4 Figure 10.32 shows an example of phase counting mode 4 operation, and table 10.12 summarizes the TCNT up/down-count conditions. TCLKA (channels 1 and 5) TCLKC (channels 2 and 4) TCLKB (channels 1 and 5) TCLKD (channels 2 and 4) TCNT value Up-count Down-count Time Figure 10.32 Example of Phase Counting Mode 4 Operation Table 10.
Section 10 16-Bit Timer Pulse Unit (TPU) Phase Counting Mode Application Example: Figure 10.33 shows an example in which phase counting mode is designated for channel 1, and channel 1 is coupled with channel 0 to input servo motor 2-phase encoder pulses in order to detect the position or speed. Channel 1 is set to phase counting mode 1, and the encoder pulse A-phase and B-phase are input to TCLKA and TCLKB.
Section 10 16-Bit Timer Pulse Unit (TPU) Channel 1 TCLKA TCLKB Edge detection circuit TCNT1 TGR1A (speed period capture) TGR1B (position period capture) TCNT0 + TGR0A (speed control period) TGR0C (position control period) – + – TGR0B (pulse width capture) TGR0D (buffer operation) Channel 0 Figure 10.33 Phase Counting Mode Application Example 10.5 Interrupts 10.5.
Section 10 16-Bit Timer Pulse Unit (TPU) Table 10.13 lists the TPU interrupt sources. Table 10.
Section 10 16-Bit Timer Pulse Unit (TPU) Input Capture/Compare Match Interrupt: An interrupt is requested if the TGIE bit in TIER is set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare match on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0. The TPU has 16 input capture/compare match interrupts, four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5.
Section 10 16-Bit Timer Pulse Unit (TPU) In the TPU, a total of six TGRA input capture/compare match interrupts can be used as A/D converter conversion start sources, one for each channel. 10.6 Operation Timing 10.6.1 Input/Output Timing TCNT Count Timing: Figure 10.34 shows TCNT count timing in internal clock operation, and figure 10.35 shows TCNT count timing in external clock operation. φ Internal clock Falling edge Rising edge TCNT input clock TCNT N–1 N N+1 N+2 Figure 10.
Section 10 16-Bit Timer Pulse Unit (TPU) Output Compare Output Timing: A compare match signal is generated in the final state in which TCNT and TGR match (the point at which the count value matched by TCNT is updated). When a compare match signal is generated, the output value set in TIOR is output at the output compare output pin. After a match between TCNT and TGR, the compare match signal is not generated until the TCNT input clock is generated. Figure 10.36 shows output compare output timing.
Section 10 16-Bit Timer Pulse Unit (TPU) Timing for Counter Clearing by Compare Match/Input Capture: Figure 10.38 shows the timing when counter clearing by compare match occurrence is specified, and figure 10.39 shows the timing when counter clearing by input capture occurrence is specified. φ Compare match signal Counter clear signal TCNT N TGR N H'0000 Figure 10.38 Counter Clear Timing (Compare Match) φ Input capture signal Counter clear signal TCNT TGR N H'0000 N Figure 10.
Section 10 16-Bit Timer Pulse Unit (TPU) Buffer Operation Timing: Figures 10.40 and 10.41 show the timing in buffer operation. φ TCNT n n+1 Compare match signal TGRA, TGRB n TGRC, TGRD N N Figure 10.40 Buffer Operation Timing (Compare Match) φ Input capture signal TCNT N TGRA, TGRB n TGRC, TGRD N+1 N N+1 n N Figure 10.41 Buffer Operation Timing (Input Capture) Rev.6.00 Sep.
Section 10 16-Bit Timer Pulse Unit (TPU) 10.6.2 Interrupt Signal Timing TGF Flag Setting Timing in Case of Compare Match: Figure 10.42 shows the timing for setting of the TGF flag in TSR by compare match occurrence, and TGI interrupt request signal timing. φ TCNT input clock TCNT N TGR N N+1 Compare match signal TGF flag TGI interrupt Figure 10.42 TGI Interrupt Timing (Compare Match) Rev.6.00 Sep.
Section 10 16-Bit Timer Pulse Unit (TPU) TGF Flag Setting Timing in Case of Input Capture: Figure 10.43 shows the timing for setting of the TGF flag in TSR by input capture occurrence, and TGI interrupt request signal timing. φ Input capture signal TCNT N TGR N TGF flag TGI interrupt Figure 10.43 TGI Interrupt Timing (Input Capture) Rev.6.00 Sep.
Section 10 16-Bit Timer Pulse Unit (TPU) TCFV Flag/TCFU Flag Setting Timing: Figure 10.44 shows the timing for setting of the TCFV flag in TSR by overflow occurrence, and TCIV interrupt request signal timing. Figure 10.45 shows the timing for setting of the TCFU flag in TSR by underflow occurrence, and TCIU interrupt request signal timing. φ TCNT input clock TCNT (overflow) H'FFFF H'0000 Overflow signal TCFV flag TCIV interrupt Figure 10.
Section 10 16-Bit Timer Pulse Unit (TPU) Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing 0 to it. When the DTC or DMAC* is activated, the flag is cleared automatically. Figure 10.46 shows the timing for status flag clearing by the CPU, and figure 10.47 shows the timing for status flag clearing by the DTC or DMAC*. Note: * The DMAC is not supported in the H8S/2321.
Section 10 16-Bit Timer Pulse Unit (TPU) 10.7 Usage Notes Note that the kinds of operation and contention described below can occur during TPU operation. Input Clock Restrictions: The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at least 2.5 states in the case of both-edge detection. The TPU will not operate properly with a narrower pulse width. In phase counting mode, the phase difference and overlap between the two input clocks must be at least 1.
Section 10 16-Bit Timer Pulse Unit (TPU) Contention between TCNT Write and Clear Operations: If the counter clear signal is generated in the T2 state of a TCNT write cycle, TCNT clearing takes precedence and the TCNT write is not performed. Figure 10.49 shows the timing in this case. TCNT write cycle T2 T1 φ TCNT address Address Write signal Counter clear signal N TCNT H'0000 Figure 10.49 Contention between TCNT Write and Clear Operations Rev.6.00 Sep.
Section 10 16-Bit Timer Pulse Unit (TPU) Contention between TCNT Write and Increment Operations: If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence and TCNT is not incremented. Figure 10.50 shows the timing in this case. TCNT write cycle T1 T2 φ TCNT address Address Write signal TCNT input clock TCNT N M TCNT write data Figure 10.50 Contention between TCNT Write and Increment Operations Rev.6.00 Sep.
Section 10 16-Bit Timer Pulse Unit (TPU) Contention between TGR Write and Compare Match: If a compare match occurs in the T2 state of a TGR write cycle, the TGR write takes precedence and the compare match signal is inhibited. A compare match does not occur even if the same value as before is written. Figure 10.51 shows the timing in this case. TGR write cycle T2 T1 φ TGR address Address Write signal Compare match signal Inhibited TCNT N N+1 TGR N M TGR write data Figure 10.
Section 10 16-Bit Timer Pulse Unit (TPU) Contention between Buffer Register Write and Compare Match: If a compare match occurs in the T2 state of a TGR write cycle, the data transferred to TGR by the buffer operation will be the data prior to the write. Figure 10.52 shows the timing in this case. TGR write cycle T1 T2 φ Buffer register address Address Write signal Compare match signal Buffer register write data Buffer register TGR N M N Figure 10.
Section 10 16-Bit Timer Pulse Unit (TPU) Contention between TGR Read and Input Capture: If the input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will be the data after input capture transfer. Figure 10.53 shows the timing in this case. TGR read cycle T2 T1 φ TGR address Address Read signal Input capture signal TGR X M M Internal data bus Figure 10.53 Contention between TGR Read and Input Capture Rev.6.00 Sep.
Section 10 16-Bit Timer Pulse Unit (TPU) Contention between TGR Write and Input Capture: If the input capture signal is generated in the T2 state of a TGR write cycle, the input capture operation takes precedence and the write to TGR is not performed. Figure 10.54 shows the timing in this case. TGR write cycle T2 T1 φ TGR address Address Write signal Input capture signal TCNT TGR M M Figure 10.54 Contention between TGR Write and Input Capture Rev.6.00 Sep.
Section 10 16-Bit Timer Pulse Unit (TPU) Contention between Buffer Register Write and Input Capture: If the input capture signal is generated in the T2 state of a buffer write cycle, the buffer operation takes precedence and the write to the buffer register is not performed. Figure 10.55 shows the timing in this case. Buffer register write cycle T1 T2 φ Buffer register address Address Write signal Input capture signal TCNT TGR Buffer register N M N M Figure 10.
Section 10 16-Bit Timer Pulse Unit (TPU) Contention between Overflow/Underflow and Counter Clearing: If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is not set and TCNT clearing takes precedence. Figure 10.56 shows the operation timing when a TGR compare match is specified as the clearing source, and H'FFFF is set in TGR. φ TCNT input clock TCNT H'FFFF H'0000 Counter clear signal TGF Prohibited TCFV flag Figure 10.
Section 10 16-Bit Timer Pulse Unit (TPU) Contention between TCNT Write and Overflow/Underflow: If there is an up-count or downcount in the T2 state of a TCNT write cycle, and overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is not set. Figure 10.57 shows the operation timing when there is contention between TCNT write and overflow. TCNT write cycle T2 T1 φ TCNT address Address Write signal TCNT TCNT write data H'FFFF M Prohibited TCFV flag Figure 10.
Section 11 Programmable Pulse Generator (PPG) Section 11 Programmable Pulse Generator (PPG) 11.1 Overview The chip has a built-in programmable pulse generator (PPG) that provides pulse outputs by using the 16-bit timer-pulse unit (TPU) as a time base. The PPG pulse outputs are divided into 4-bit groups (group 3 to group 0) that can operate both simultaneously and independently. 11.1.1 Features PPG features are listed below.
Section 11 Programmable Pulse Generator (PPG) 11.1.2 Block Diagram Figure 11.1 shows a block diagram of the PPG.
Section 11 Programmable Pulse Generator (PPG) 11.1.3 Pin Configuration Table 11.1 summarizes the PPG pins. Table 11.
Section 11 Programmable Pulse Generator (PPG) 11.1.4 Registers Table 11.2 summarizes the PPG registers. Table 11.
Section 11 Programmable Pulse Generator (PPG) 11.2 Register Descriptions 11.2.
Section 11 Programmable Pulse Generator (PPG) NDERL Bits 7 to 0—Next Data Enable 7 to 0 (NDER7 to NDER0): These bits enable or disable pulse output on a bit-by-bit basis. Bits 7 to 0 NDER7 to NDER0 Description 0 Pulse outputs PO7 to PO0 are disabled (NDR7 to NDR0 are not transferred to POD7 to POD0) (Initial value) 1 Pulse outputs PO7 to PO0 are enabled (NDR7 to NDR0 are transferred to POD7 to POD0) 11.2.
Section 11 Programmable Pulse Generator (PPG) 11.2.3 Next Data Registers H and L (NDRH, NDRL) NDRH and NDRL are 8-bit readable/writable registers that store the next data for pulse output. During pulse output, the contents of NDRH and NDRL are transferred to the corresponding bits in PODRH and PODRL when the TPU compare match event specified by PCR occurs. The NDRH and NDRL addresses differ depending on whether pulse output groups have the same output trigger or different output triggers.
Section 11 Programmable Pulse Generator (PPG) Address H'FF4D Bit : 7 6 5 4 3 2 1 0 NDR7 NDR6 NDR5 NDR4 NDR3 NDR2 NDR1 NDR0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 — — — — — — — — Initial value : 1 1 1 1 1 1 1 1 R/W — — — — — — — — Initial value : R/W : Address H'FF4F Bit : : Different Triggers for Pulse Output Groups: If pulse output groups 2 and 3 are triggered by different compare match events, the address of
Section 11 Programmable Pulse Generator (PPG) Address H'FF4D Bit : 7 6 5 4 3 2 1 0 NDR7 NDR6 NDR5 NDR4 — — — — 0 0 0 0 1 1 1 1 R/W R/W R/W R/W — — — — 7 6 5 4 3 2 1 0 — — — — NDR3 NDR2 NDR1 NDR0 Initial value : 1 1 1 1 0 0 0 0 R/W — — — — R/W R/W R/W R/W 4 3 2 1 0 Initial value : R/W : Address H'FF4F Bit 11.2.
Section 11 Programmable Pulse Generator (PPG) Bits 5 and 4—Group 2 Compare Match Select 1 and 0 (G2CMS1, G2CMS0): These bits select the compare match that triggers pulse output group 2 (pins PO11 to PO8).
Section 11 Programmable Pulse Generator (PPG) 11.2.6 Bit PPG Output Mode Register (PMR) : Initial value : R/W : 7 6 5 4 3 2 1 0 G3INV G2INV G1INV G0INV G3NOV G2NOV G1NOV G0NOV 1 1 1 1 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W PMR is an 8-bit readable/writable register that selects pulse output inversion and non-overlapping operation for each group.
Section 11 Programmable Pulse Generator (PPG) Bit 5—Group 1 Inversion (G1INV): Selects direct output or inverted output for pulse output group 1 (pins PO7 to PO4). Bit 5 G1INV Description 0 Inverted output for pulse output group 1 (low-level output at pin for a 1 in PODRL) 1 Direct output for pulse output group 1 (high-level output at pin for a 1 in PODRL) (Initial value) Bit 4—Group 0 Inversion (G0INV): Selects direct output or inverted output for pulse output group 0 (pins PO3 to PO0).
Section 11 Programmable Pulse Generator (PPG) Bit 1—Group 1 Non-Overlap (G1NOV): Selects normal or non-overlapping operation for pulse output group 1 (pins PO7 to PO4).
Section 11 Programmable Pulse Generator (PPG) 11.2.8 Bit Port 2 Data Direction Register (P2DDR) : 7 6 5 4 3 2 1 0 P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR Initial value : 0 0 0 0 0 0 0 0 R/W W W W W W W W W : P2DDR is an 8-bit write-only register, the individual bits of which specify input or output for the pins of port 2. Port 2 is multiplexed with pins PO7 to PO0. Bits corresponding to pins used for PPG output must be set to 1.
Section 11 Programmable Pulse Generator (PPG) 11.3 Operation 11.3.1 Overview PPG pulse output is enabled when the corresponding bits in P1DDR, P2DDR, and NDER are set to 1. In this state the corresponding PODR contents are output. When the compare match event specified by PCR occurs, the corresponding NDR bit contents are transferred to PODR to update the output values. Figure 11.2 illustrates the PPG output operation and table 11.3 summarizes the PPG operating conditions.
Section 11 Programmable Pulse Generator (PPG) 11.3.2 Output Timing If pulse output is enabled, NDR contents are transferred to PODR and output when the specified compare match event occurs. Figure 11.3 shows the timing of these operations for the case of normal output in groups 2 and 3, triggered by compare match A. φ N TCNT TGRA N+1 N Compare match A signal n NDRH PODRH m PO8 to PO15 n m n Figure 11.3 Timing of Transfer and Output of NDR Contents (Example) Rev.6.00 Sep.
Section 11 Programmable Pulse Generator (PPG) 11.3.3 Normal Pulse Output Sample Setup Procedure for Normal Pulse Output: Figure 11.4 shows a sample procedure for setting up normal pulse output. Normal PPG output Select TGR functions [1] Set TGRA value [2] Set counting operation [3] Select interrupt request [4] Set initial output data [5] Enable pulse output [6] Select output trigger [7] [1] Set TIOR to make TGRA an output compare register (with output disabled).
Section 11 Programmable Pulse Generator (PPG) Example of Normal Pulse Output (Example of Five-Phase Pulse Output): Figure 11.5 shows an example in which pulse output is used for cyclic five-phase pulse output. TCNT value Compare match TCNT TGRA H'0000 Time 80 NDRH PODRH 00 C0 80 40 C0 60 40 20 60 30 20 10 30 18 10 08 18 88 08 80 88 C0 80 40 C0 PO15 PO14 PO13 PO12 PO11 Figure 11.
Section 11 Programmable Pulse Generator (PPG) 11.3.4 Non-Overlapping Pulse Output Sample Setup Procedure for Non-Overlapping Pulse Output: Figure 11.6 shows a sample procedure for setting up non-overlapping pulse output. [1] Set TIOR to make TGRA and TGRB an output compare registers (with output disabled).
Section 11 Programmable Pulse Generator (PPG) Example of Non-Overlapping Pulse Output (Example of Four-Phase Complementary NonOverlapping Output): Figure 11.7 shows an example in which pulse output is used for fourphase complementary non-overlapping pulse output. TCNT value TGRB TCNT TGRA H'0000 NDRH PODRH Time 95 00 65 95 59 05 65 56 41 59 95 50 56 65 14 95 05 65 Non-overlap margin PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 Figure 11.
Section 11 Programmable Pulse Generator (PPG) [1] Set up the TPU channel to be used as the output trigger channel so that TGRA and TGRB are output compare registers. Set the trigger period in TGRB and the non-overlap margin in TGRA, and set the counter to be cleared by compare match B. Set the TGIEA bit in TIER to 1 to enable the TGIA interrupt.
Section 11 Programmable Pulse Generator (PPG) 11.3.5 Inverted Pulse Output If the G3INV, G2INV, G1INV, and G0INV bits in PMR are cleared to 0, values that are the inverse of the PODR contents can be output. Figure 11.8 shows the outputs when G3INV and G2INV are cleared to 0, in addition to the settings of figure 11.7. TCNT value TGRB TCNT TGRA H'0000 NDRH PODRL Time 95 00 65 95 59 05 65 56 41 59 95 50 56 65 14 95 05 PO15 PO14 PO13 PO12 PO11 PO10 PO9 PO8 Figure 11.
Section 11 Programmable Pulse Generator (PPG) 11.3.6 Pulse Output Triggered by Input Capture Pulse output can be triggered by TPU input capture as well as by compare match. If TGRA functions as an input capture register in the TPU channel selected by PCR, pulse output will be triggered by the input capture signal. Figure 11.9 shows the timing of this output. φ TIOC pin Input capture signal NDR N PODR M PO M N N Figure 11.9 Pulse Output Triggered by Input Capture (Example) Rev.6.00 Sep.
Section 11 Programmable Pulse Generator (PPG) 11.4 Usage Notes 11.4.1 Operation of Pulse Output Pins Pins PO0 to PO15 are also used for other supporting functions such as the TPU. When output by another supporting function is enabled, the corresponding pins cannot be used for pulse output. Note, however, that data transfer from NDR bits to PODR bits takes place, regardless of the usage of the pins. Pin functions should be changed only under conditions in which the output trigger event will not occur.
Section 11 Programmable Pulse Generator (PPG) Therefore, 0 data can be transferred ahead of 1 data by making compare match B occur before compare match A. The NDR contents should not be altered during the interval from compare match B to compare match A (the non-overlap margin). This can be accomplished by having the TGIA interrupt handling routine write the next data in NDR, or by having the TGIA interrupt activate the DTC or DMAC*.
Section 11 Programmable Pulse Generator (PPG) Rev.6.00 Sep.
Section 12 8-Bit Timers Section 12 8-Bit Timers 12.1 Overview The chip includes an 8-bit timer module with two channels (TMR0 and TMR1). Each channel has an 8-bit counter (TCNT) and two time constant registers (TCORA and TCORB) that are constantly compared with the TCNT value to detect compare match events. The 8-bit timer module can thus be used for a variety of functions, including pulse output with an arbitrary duty cycle. 12.1.1 Features The features of the 8-bit timer module are listed below.
Section 12 8-Bit Timers 12.1.2 Block Diagram Figure 12.1 shows a block diagram of the 8-bit timer module.
Section 12 8-Bit Timers 12.1.3 Pin Configuration Table 12.1 summarizes the input and output pins of the 8-bit timer module. Table 12.1 Input and Output Pins of 8-Bit Timer Channel Name Symbol I/O Function 0 Timer output pin 0 TMO0 Output Outputs at compare match Timer clock input pin 0 TMCI0 Input Inputs external clock for counter Timer reset input pin 0 TMRI0 Input Inputs external reset to counter 1 12.1.
Section 12 8-Bit Timers 12.2 Register Descriptions 12.2.1 Timer Counters 0 and 1 (TCNT0, TCNT1) TCNT0 Bit TCNT1 : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCNT0 and TCNT1 are 8-bit readable/writable up-counters that increment on pulses generated from an internal or external clock source.
Section 12 8-Bit Timers The timer output can be freely controlled by these compare match signals and the settings of bits OS1 and OS0 in TCSR. TCORA0 and TCORA1 are each initialized to H'FF by a reset and in hardware standby mode. 12.2.
Section 12 8-Bit Timers Bit 7—Compare Match Interrupt Enable B (CMIEB): Selects whether CMFB interrupt requests (CMIB) are enabled or disabled when the CMFB flag in TCSR is set to 1. Bit 7 CMIEB Description 0 CMFB interrupt requests (CMIB) are disabled 1 CMFB interrupt requests (CMIB) are enabled (Initial value) Bit 6—Compare Match Interrupt Enable A (CMIEA): Selects whether CMFA interrupt requests (CMIA) are enabled or disabled when the CMFA flag in TCSR is set to 1.
Section 12 8-Bit Timers When use of an external clock is selected, three types of count can be selected: at the rising edge, the falling edge, and both rising and falling edges. Some functions differ between channel 0 and channel 1.
Section 12 8-Bit Timers TCSR0 and TCSR1 are 8-bit registers that display compare match and overflow statuses, and control compare match output. TCSR0 is initialized to H'00, and TCSR1 to H'10, by a reset and in hardware standby mode. Bit 7—Compare Match Flag B (CMFB): Status flag indicating whether the values of TCNT and TCORB match.
Section 12 8-Bit Timers Bit 4—A/D Trigger Enable (ADTE) (TCSR0 Only): Selects enabling or disabling of A/D converter start requests by compare match A. In TCSR1, this bit is reserved: it is always read as 1 and cannot be modified.
Section 12 8-Bit Timers 12.2.6 Module Stop Control Register (MSTPCR) MSTPCRH Bit MSTPCRL : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR is a 16-bit readable/writable register that performs module stop mode control.
Section 12 8-Bit Timers 12.3 Operation 12.3.1 TCNT Incrementation Timing TCNT is incremented by input clock pulses (either internal or external). Internal Clock: Three different internal clock signals (φ/8, φ/64, or φ/8192) divided from the system clock (φ) can be selected, by setting bits CKS2 to CKS0 in TCR. Figure 12.2 shows the count timing. φ Internal clock Clock input to TCNT TCNT N–1 N N+1 Figure 12.
Section 12 8-Bit Timers φ External clock input pin Clock input to TCNT TCNT N–1 N N+1 Figure 12.3 Count Timing for External Clock Input 12.3.2 Compare Match Timing Setting of Compare Match Flags A and B (CMFA, CMFB): The CMFA and CMFB flags in TCSR are set to 1 by a compare match signal generated when the TCOR and TCNT values match. The compare match signal is generated at the last state in which the match is true, just before the timer counter is updated.
Section 12 8-Bit Timers Timer Output Timing: When compare match A or B occurs, the timer output changes as specified by bits OS3 to OS0 in TCSR. Depending on these bits, the output can remain the same, change to 0, change to 1, or toggle. Figure 12.5 shows the timing when the output is set to toggle at compare match A. φ Compare match A signal Timer output pin Figure 12.
Section 12 8-Bit Timers 12.3.3 Timing of TCNT External Reset TCNT is cleared at the rising edge of an external reset input, depending on the settings of the CCLR1 and CCLR0 bits in TCR. The clear pulse width must be at least 1.5 states. Figure 12.7 shows the timing of this operation. φ External reset input pin Clear signal TCNT N–1 N H'00 Figure 12.7 Timing of Clearance by External Reset 12.3.
Section 12 8-Bit Timers 12.3.5 Operation with Cascaded Connection If bits CKS2 to CKS0 in either TCR0 or TCR1 are set to B’100, the 8-bit timers of the two channels are cascaded. With this configuration, a single 16-bit timer could be used (16-bit counter mode) or compare matches of the 8-bit channel 0 could be counted by the timer of channel 1 (compare match counter mode). In this case, the timer operates as below.
Section 12 8-Bit Timers 12.4 Interrupts 12.4.1 Interrupt Sources and DTC Activation There are three 8-bit timer interrupt sources: CMIA, CMIB, and OVI. Their relative priorities are shown in table 12.3. Each interrupt source is set as enabled or disabled by the corresponding interrupt enable bit in TCR, and independent interrupt requests are sent for each to the interrupt controller. It is also possible to activate the DTC by means of CMIA and CMIB interrupts. Table 12.
Section 12 8-Bit Timers 12.5 Sample Application In the example below, the 8-bit timer is used to generate a pulse output with a selected duty cycle, as shown in figure 12.9. The control bits are set as follows: [1] In TCR, bit CCLR1 is cleared to 0 and bit CCLR0 is set to 1 so that the timer counter is cleared when its value matches the constant in TCORA. [2] In TCSR, bits OS3 to OS0 are set to B'0110, causing the output to change to 1 at a TCORA compare match and to 0 at a TCORB compare match.
Section 12 8-Bit Timers 12.6 Usage Notes Note that the following kinds of contention can occur in the 8-bit timer module. 12.6.1 Contention between TCNT Write and Clear If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the clear takes priority, so that the counter is cleared and the write is not performed. Figure 12.10 shows this operation.
Section 12 8-Bit Timers 12.6.2 Contention between TCNT Write and Increment If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write takes priority and the counter is not incremented. Figure 12.11 shows this operation. TCNT write cycle by CPU T1 T2 φ Address TCNT address Internal write signal TCNT input clock TCNT N M Counter write data Figure 12.11 Contention between TCNT Write and Increment Rev.6.00 Sep.
Section 12 8-Bit Timers 12.6.3 Contention between TCOR Write and Compare Match During the T2 state of a TCOR write cycle, the TCOR write has priority and the compare match signal is inhibited even if a compare match event occurs. Figure 12.12 shows this operation. TCOR write cycle by CPU T1 T2 φ Address TCOR address Internal write signal TCNT N N+1 TCOR N M TCOR write data Compare match signal Prohibited Figure 12.12 Contention between TCOR Write and Compare Match Rev.6.00 Sep.
Section 12 8-Bit Timers 12.6.4 Contention between Compare Matches A and B If compare match events A and B occur at the same time, the 8-bit timer operates in accordance with the priorities for the output statuses set for compare match A and compare match B, as shown in table 12.4. Table 12.4 Timer Output Priorities Output Setting Priority Toggle output High 1 output 0 output No change 12.6.
Section 12 8-Bit Timers Table 12.5 Switching of Internal Clock and TCNT Operation No.
Section 12 8-Bit Timers No. 4 Timing of Switchover by Means of CKS1 TCNT Clock Operation and CKS0 Bits Switching from high to high Clock before switchover Clock after switchover TCNT clock TCNT N N+1 N+2 CKS bit write Notes: 1. 2. 3. 4. 12.6.6 Includes switching from low to stop, and from stop to low. Includes switching from stop to high. Includes switching from high to stop. Generated on the assumption that the switchover is a falling edge; TCNT is incremented.
Section 12 8-Bit Timers Rev.6.00 Sep.
Section 13 Watchdog Timer Section 13 Watchdog Timer 13.1 Overview The chip has a single-channel on-chip watchdog timer (WDT) for monitoring system operation. The WDT outputs an overflow signal (WDTOVF)* if a system crash prevents the CPU from writing to the timer counter, allowing it to overflow. At the same time, the WDT can also generate an internal reset signal for the chip. When this watchdog function is not needed, the WDT can be used as an interval timer.
Section 13 Watchdog Timer 13.1.2 Block Diagram Figure 13.1 shows a block diagram of the WDT. Overflow WDTOVF*1 Internal reset signal*2 Clock Clock select Reset control RSTCSR Internal clock sources TCNT TSCR Module bus Bus interface WDT Legend: Timer control/status register TCSR: Timer counter TCNT: RSTCSR: Reset control/status register Notes: 1. The WDTOVF pin function cannot be used in the F-ZTAT versions. 2. Internal reset signal generation is specified by means of a register setting.
Section 13 Watchdog Timer 13.1.3 Pin Configuration Table 13.1 describes the WDT output pin. Table 13.1 WDT Pin Name Symbol I/O Function Watchdog timer overflow WDTOVF* Output Outputs counter overflow signal in watchdog timer mode Note: * The WDTOVF pin function cannot be used in the F-ZTAT versions. 13.1.4 Register Configuration The WDT has three registers, as summarized in table 13.2. These registers control clock selection, WDT mode switching, and the reset signal. Table 13.
Section 13 Watchdog Timer 13.2 Register Descriptions 13.2.1 Timer Counter (TCNT) Bit : 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W : TCNT is an 8-bit readable/writable*1 up-counter. When the TME bit is set to 1 in TCSR, TCNT starts counting pulses generated from the internal clock source selected by bits CKS2 to CKS0 in TCSR.
Section 13 Watchdog Timer 13.2.2 Bit Timer Control/Status Register (TCSR) : Initial value : R/W : 7 6 5 4 3 2 1 0 OVF WT/IT TME — — CKS2 CKS1 CKS0 0 0 0 1 1 0 0 0 R/(W)* R/W R/W — — R/W R/W R/W Note: * Only 0 can be written, to clear the flag. TCSR is an 8-bit readable/writable* register. Its functions include selecting the clock source to be input to TCNT, and the timer mode. TCR is initialized to H'18 by a reset and in hardware standby mode.
Section 13 Watchdog Timer Bit 6 WT/IT Description 0 Interval timer: Sends the CPU an interval timer interrupt request (WOVI) when TCNT overflows (Initial value) 1 2 Watchdog timer: Generates the WDTOVF signal* when TCNT overflows* 1 Notes: 1. The WDTOVF pin function cannot be used in the F-ZTAT versions. 2. For details of the case where TCNT overflows in watchdog timer mode, see section 13.2.3, Reset Control/Status Register (RSTCSR). Bit 5—Timer Enable (TME): Selects whether TCNT runs or is halted.
Section 13 Watchdog Timer 13.2.3 Bit Reset Control/Status Register (RSTCSR) : Initial value : R/W : 7 6 5 4 3 2 1 0 WOVF RSTE — — — — — — 0 0 0 1 1 1 1 1 R/(W)* R/W R/W — — — — — Note: * Only 0 can be written, to clear the flag. RSTCSR is an 8-bit readable/writable* register that controls the generation of the internal reset signal when TCNT overflows, and selects the type of internal reset signal.
Section 13 Watchdog Timer Bit 5—Reserved: This bit should be written with 0. Bits 4 to 0—Reserved: These bits cannot be modified and are always read as 1. 13.2.4 Notes on Register Access The watchdog timer’s TCNT, TCSR, and RSTCSR registers differ from other registers in being more difficult to write to. The procedures for writing to and reading these registers are given below. Writing to TCNT and TCSR: These registers must be written to by a word transfer instruction.
Section 13 Watchdog Timer Writing 0 to WOVF bit 15 8 7 0 H'A5 Address: H'FFBE H'00 Writing to RSTE bit 15 Address: H'FFBE 8 7 H'5A 0 Write data Figure 13.3 Writing to RSTCSR Reading TCNT, TCSR, and RSTCSR: These registers are read in the same way as other registers. The read addresses are H'FFBC for TCSR, H'FFBD for TCNT, and H'FFBF for RSTCSR. 13.3 Operation 13.3.1 Operation in Watchdog Timer Mode To use the WDT as a watchdog timer, set the WT/IT and TME bits to 1.
Section 13 Watchdog Timer TCNT count Overflow H'FF Time H'00 WT/IT=1 TME=1 H'00 written to TCNT WOVF=1 WDTOVF *3 and internal reset are generated WT/IT=1 TME=1 WDTOVF signal*3 132 states*2 Internal reset signal*1 518 states Legend: WT/IT: Timer mode select bit TME: Timer enable bit Notes: 1. The internal reset signal is generated only if the RSTE bit is set to 1. 2. 130 states when the RSTE bit is cleared to 0. 3. The WDTOVF pin function cannot be used in the F-ZTAT versions. Figure 13.
Section 13 Watchdog Timer 13.3.2 Operation in Interval Timer Mode To use the WDT as an interval timer, clear the WT/IT bit in TCSR to 0 and set the TME bit to 1. An interval timer interrupt (WOVI) is generated each time TCNT overflows, provided that the WDT is operating as an interval timer, as shown in figure 13.5. This function can be used to generate interrupt requests at regular intervals.
Section 13 Watchdog Timer 13.3.3 Timing of Overflow Flag (OVF) Setting The OVF flag is set to 1 if TCNT overflows during interval timer operation. At the same time, an interval timer interrupt (WOVI) is requested. This timing is shown in figure 13.6. φ TCNT H'FF Overflow signal (internal signal) OVF Figure 13.6 Timing of OVF Setting Rev.6.00 Sep.
Section 13 Watchdog Timer 13.3.4 Timing of Watchdog Timer Overflow Flag (WOVF) Setting The WOVF flag is set to 1 if TCNT overflows during watchdog timer operation. At the same time, the WDTOVF signal* goes low. If TCNT overflows while the RSTE bit in RSTCSR is set to 1, an internal reset signal is generated for the entire chip. Figure 13.7 shows the timing in this case. Note: * The WDTOVF pin function cannot be used in the F-ZTAT versions.
Section 13 Watchdog Timer 13.4 Interrupts During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI). The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. 13.5 Usage Notes 13.5.1 Contention between Timer Counter (TCNT) Write and Increment If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write takes priority and the timer counter is not incremented. Figure 13.8 shows this operation.
Section 13 Watchdog Timer 13.5.2 Changing Value of CKS2 to CKS0 If bits CKS2 to CKS0 in TCSR are written to while the WDT is operating, errors may occur in the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before changing the value of bits CKS2 to CKS0. 13.5.3 Switching between Watchdog Timer Mode and Interval Timer Mode If the mode is switched from watchdog timer to interval timer, or vice versa, while the WDT is operating, errors may occur in the incrementation.
Section 13 Watchdog Timer 13.5.5 Internal Reset in Watchdog Timer Mode The chip is not reset internally if TCNT overflows while the RSTE bit is cleared to 0 during watchdog timer operation, but TCNT and TCSR of the WDT are reset. TCNT, TCSR, and RSTCR cannot be written to while the WDTOVF signal* is low. Also note that a read of the WOVF flag is not recognized during this period. To clear the WOVF flag, therefore, read RSTCSR after the WDTOVF signal* goes high, then write 0 to the WOVF flag.
Section 14 Serial Communication Interface (SCI) Section 14 Serial Communication Interface (SCI) 14.1 Overview The chip is equipped with a serial communication interface (SCI) that can handle both asynchronous and synchronous serial communication. A function is also provided for serial communication between processors (multiprocessor communication function). 14.1.1 Features SCI features are listed below.
Section 14 Serial Communication Interface (SCI) • Full-duplex communication capability ⎯ The transmitter and receiver are mutually independent, enabling transmission and reception to be executed simultaneously ⎯ Double-buffering is used in both the transmitter and the receiver, enabling continuous transmission and continuous reception of serial data • Choice of LSB-first or MSB-first transfer ⎯ Can be selected regardless of the communication mode*1 (except in the case of asynchronous mode 7-bit data) • Bui
Section 14 Serial Communication Interface (SCI) 14.1.2 Block Diagram Bus interface Figure 14.1 shows a block diagram of the SCI.
Section 14 Serial Communication Interface (SCI) 14.1.3 Pin Configuration Table 14.1 shows the serial pins for each SCI channel. Table 14.
Section 14 Serial Communication Interface (SCI) 14.1.4 Register Configuration The SCI has the internal registers shown in table 14.2. These registers are used to specify asynchronous mode or synchronous mode, the data format, and the bit rate, and to control the transmitter/receiver. Table 14.
Section 14 Serial Communication Interface (SCI) 14.2 Register Descriptions 14.2.1 Receive Shift Register (RSR) Bit : 7 6 5 4 3 2 1 0 R/W : — — — — — — — — RSR is a register used to receive serial data. The SCI sets serial data input from the RxD pin in RSR in the order received, starting with the LSB (bit 0), and converts it to parallel data. When one byte of data has been received, it is transferred to RDR automatically. RSR cannot be directly read or written to by the CPU. 14.2.
Section 14 Serial Communication Interface (SCI) 14.2.3 Transmit Shift Register (TSR) Bit : 7 6 5 4 3 2 1 0 R/W : — — — — — — — — TSR is a register used to transmit serial data. To perform serial data transmission, the SCI first transfers transmit data from TDR to TSR, then sends the data to the TxD pin starting with the LSB (bit 0). When transmission of one byte is completed, the next transmit data is transferred from TDR to TSR, and transmission started, automatically.
Section 14 Serial Communication Interface (SCI) 14.2.5 Bit Serial Mode Register (SMR) : Initial value : R/W : 7 6 5 4 3 2 1 0 C/A CHR PE O/E STOP MP CKS1 CKS0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W SMR is an 8-bit register used to set the SCI’s serial transfer format and select the baud rate generator clock source. SMR can be read or written to by the CPU at all times. SMR is initialized to H'00 by a reset and in hardware standby mode.
Section 14 Serial Communication Interface (SCI) Bit 5—Parity Enable (PE): In asynchronous mode, selects whether or not parity bit addition is performed in transmission, and parity bit checking in reception. In synchronous mode and with a multiprocessor format, parity bit addition and checking is not performed, regardless of the PE bit setting.
Section 14 Serial Communication Interface (SCI) Bit 3 STOP Description 0 1 stop bit: In transmission, a single 1-bit (stop bit) is added to the end of a transmit character before it is sent. (Initial value) 1 2 stop bits: In transmission, two 1-bits (stop bits) are added to the end of a transmit character before it is sent. In reception, only the first stop bit is checked, regardless of the STOP bit setting.
Section 14 Serial Communication Interface (SCI) 14.2.6 Bit Serial Control Register (SCR) : Initial value : R/W : 7 6 5 4 3 2 1 0 TIE RIE TE RE MPIE TEIE CKE1 CKE0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W SCR is a register that performs enabling or disabling of SCI transfer operations, serial clock output in asynchronous mode, and interrupt requests, and selection of the serial clock source. SCR can be read or written to by the CPU at all times.
Section 14 Serial Communication Interface (SCI) Bit 6—Receive Interrupt Enable (RIE): Enables or disables receive-data-full interrupt (RXI) request and receive-error interrupt (ERI) request generation when serial receive data is transferred from RSR to RDR and the RDRF flag in SSR is set to 1.
Section 14 Serial Communication Interface (SCI) Bit 3—Multiprocessor Interrupt Enable (MPIE): Enables or disables multiprocessor interrupts. The MPIE bit setting is only valid in asynchronous mode when the MP bit in SMR is set to 1. The MPIE bit setting is invalid in synchronous mode or when the MP bit is cleared to 0.
Section 14 Serial Communication Interface (SCI) For details of clock source selection, see table 14.9.
Section 14 Serial Communication Interface (SCI) 14.2.7 Serial Status Register (SSR) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 TDRE RDRF ORER FER PER TEND MPB MPBT 1 0 0 0 0 1 0 0 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R R R/W Note: * Only 0 can be written, to clear the flag. SSR is an 8-bit register containing status flags that indicate the operating status of the SCI, and multiprocessor bits. SSR can be read or written to by the CPU at all times.
Section 14 Serial Communication Interface (SCI) Bit 6—Receive Data Register Full (RDRF): Indicates that the received data is stored in RDR.
Section 14 Serial Communication Interface (SCI) Bit 4—Framing Error (FER): Indicates that a framing error occurred during reception in asynchronous mode, causing abnormal termination. Bit 4 FER Description 0 [Clearing condition] 1 (Initial value)* When 0 is written to FER after reading FER = 1 1 [Setting condition] When the SCI checks the stop bit at the end of the receive data when reception ends, 2 and the stop bit is 0 * Notes: 1.
Section 14 Serial Communication Interface (SCI) Bit 2—Transmit End (TEND): Indicates that there is no valid data in TDR when the last bit of the transmit character is sent, and transmission has been ended. The TEND flag is read-only and cannot be modified.
Section 14 Serial Communication Interface (SCI) 14.2.8 Bit Bit Rate Register (BRR) : 7 6 5 4 3 2 1 0 Initial value : 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W R/W : BRR is an 8-bit register that sets the serial transfer bit rate in accordance with the baud rate generator operating clock selected by bits CKS1 and CKS0 in SMR. BRR can be read or written to by the CPU at all times. BRR is initialized to H'FF by a reset and in hardware standby mode.
Section 14 Serial Communication Interface (SCI) φ = 3.6864 MHz φ = 4 MHz φ = 4.9152 MHz φ = 5 MHz Bit Rate (bits/s) n N Error (%) n N Error (%) n N Error (%) n N Error (%) 110 2 64 0.70 2 70 0.03 2 86 0.31 2 88 –0.25 150 1 191 0.00 1 207 0.16 1 255 0.00 2 64 0.16 300 1 95 0.00 1 103 0.16 1 127 0.00 1 129 0.16 600 0 191 0.00 0 207 0.16 0 255 0.00 1 64 0.16 1200 0 95 0.00 0 103 0.16 0 127 0.00 0 129 0.16 2400 0 47 0.
Section 14 Serial Communication Interface (SCI) φ = 9.8304 MHz Bit Rate (bits/s) n N Error (%) 110 2 174 150 2 300 φ = 10 MHz N Error (%) –0.26 2 177 127 0.00 2 1 255 0.00 600 1 127 1200 0 2400 0 4800 φ = 12 MHz φ = 12.288 MHz N Error (%) n N Error (%) –0.25 2 212 0.03 2 217 0.08 129 0.16 2 155 0.16 2 159 0.00 2 64 0.16 2 77 0.16 2 79 0.00 0.00 1 129 0.16 1 155 0.16 1 159 0.00 255 0.00 1 64 0.16 1 77 0.16 1 79 0.00 127 0.
Section 14 Serial Communication Interface (SCI) φ = 18 MHz Bit Rate (bits/s) n N Error (%) 110 3 79 150 2 300 φ = 19.6608 MHz φ = 20 MHz N Error (%) n N Error (%) –0.12 3 86 0.31 3 88 233 0.16 2 255 0.00 3 2 116 0.16 2 127 0.00 600 1 233 0.16 1 255 1200 1 116 0.16 1 2400 0 233 0.16 0 4800 0 116 0.16 0 9600 0 58 19200 0 31250 38400 φ = 25 MHz N Error (%) –0.25 3 110 –0.02 64 0.16 3 80 0.47 2 129 0.16 2 162 –0.15 0.00 2 64 0.
Section 14 Serial Communication Interface (SCI) Table 14.4 BRR Settings for Various Bit Rates (Synchronous Mode) Bit Rate φ = 2 MHz (bits/s) n N 110 3 70 250 2 500 1 1k φ = 4 MHz φ = 8 MHz φ = 10 MHz φ = 16 MHz n N n N n N n N 124 2 249 3 124 — — 3 249 249 2 124 2 249 — — 3 1 124 1 249 2 124 — — 2.
Section 14 Serial Communication Interface (SCI) The BRR setting is found from the following formulas. Asynchronous mode: N= φ 64 × 2 2n–1 ×B × 106 – 1 Synchronous mode: N= Where B: N: φ: n: φ 8×2 2n–1 ×B × 106 – 1 Bit rate (bits/s) BRR setting for baud rate generator (0 ≤ N ≤ 255) Operating frequency (MHz) Baud rate generator input clock (n = 0 to 3) (See the table below for the relation between n and the clock.
Section 14 Serial Communication Interface (SCI) Table 14.5 shows the maximum bit rate for each frequency in asynchronous mode. Tables 14.6 and 14.7 show the maximum bit rates with external clock input. Table 14.5 Maximum Bit Rate for Each Frequency (Asynchronous Mode) φ (MHz) Maximum Bit Rate (bits/s) n N 2 62500 0 0 2.097152 65536 0 0 2.4576 76800 0 0 3 93750 0 0 3.6864 115200 0 0 4 125000 0 0 4.9152 153600 0 0 5 156250 0 0 6 187500 0 0 6.144 192000 0 0 7.
Section 14 Serial Communication Interface (SCI) Table 14.6 Maximum Bit Rate with External Clock Input (Asynchronous Mode) φ (MHz) External Input Clock (MHz) Maximum Bit Rate (bits/s) 2 0.5000 31250 2.097152 0.5243 32768 2.4576 0.6144 38400 3 0.7500 46875 3.6864 0.9216 57600 4 1.0000 62500 4.9152 1.2288 76800 5 1.2500 78125 6 1.5000 93750 6.144 1.5360 96000 7.3728 1.8432 115200 8 2.0000 125000 9.8304 2.4576 153600 10 2.5000 156250 12 3.0000 187500 12.288 3.
Section 14 Serial Communication Interface (SCI) Table 14.7 Maximum Bit Rate with External Clock Input (Synchronous Mode) φ (MHz) External Input Clock (MHz) Maximum Bit Rate (bits/s) 2 0.3333 333333.3 4 0.6667 666666.7 6 1.0000 1000000.0 8 1.3333 1333333.3 10 1.6667 1666666.7 12 2.0000 2000000.0 14 2.3333 2333333.3 16 2.6667 2666666.7 18 3.0000 3000000.0 20 3.3333 3333333.3 25 4.1667 4166666.7 14.2.
Section 14 Serial Communication Interface (SCI) Bit 3—Smart Card Data Transfer Direction (SDIR): Selects the serial/parallel conversion format. This bit is valid when 8-bit data is used as the transmit/receive format. Bit 3 SDIR Description 0 TDR contents are transmitted LSB-first (Initial value) Receive data is stored in RDR LSB-first 1 TDR contents are transmitted MSB-first Receive data is stored in RDR MSB-first Bit 2—Smart Card Data Invert (SINV): Specifies inversion of the data logic level.
Section 14 Serial Communication Interface (SCI) 14.2.10 Module Stop Control Register (MSTPCR) MSTPCRH Bit MSTPCRL : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR is a 16-bit readable/writable register that performs module stop mode control.
Section 14 Serial Communication Interface (SCI) 14.3 Operation 14.3.1 Overview The SCI can carry out serial communication in two modes: asynchronous mode in which synchronization is achieved character by character, and synchronous mode in which synchronization is achieved with clock pulses. Selection of asynchronous or synchronous mode and the transmission format is made using SMR as shown in table 14.8.
Section 14 Serial Communication Interface (SCI) Table 14.
Section 14 Serial Communication Interface (SCI) 14.3.2 Operation in Asynchronous Mode In asynchronous mode, characters are sent or received, each preceded by a start bit indicating the start of communication and one or two stop bits indicating the end of communication. Serial communication is thus carried out with synchronization established on a character-by-character basis. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication.
Section 14 Serial Communication Interface (SCI) Data Transfer Format Table 14.10 shows the data transfer formats that can be used in asynchronous mode. Any of 12 transfer formats can be selected according to the SMR setting. Table 14.
Section 14 Serial Communication Interface (SCI) Clock Either an internal clock generated by the built-in baud rate generator or an external clock input at the SCK pin can be selected as the SCI’s serial clock, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR. For details of SCI clock source selection, see table 14.9. When an external clock is input at the SCK pin, the clock frequency should be 16 times the bit rate used.
Section 14 Serial Communication Interface (SCI) Figure 14.4 shows a sample SCI initialization flowchart. [1] Set the clock selection in SCR. Be sure to clear bits RIE, TIE, TEIE, and MPIE, and bits TE and RE, to 0. Start of initialization Clear TE and RE bits in SCR to 0 Set CKE1 and CKE0 bits in SCR (TE, RE bits 0) [1] Set data transfer format in SMR and SCMR [2] Set value in BRR [3] When the clock is selected in asynchronous mode, it is output immediately after SCR settings are made.
Section 14 Serial Communication Interface (SCI) Serial data transmission (asynchronous mode): Figure 14.5 shows a sample flowchart for serial transmission. The following procedure should be used for serial data transmission. Initialization [1] Start of transmission Read TDRE flag in SSR [2] [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0.
Section 14 Serial Communication Interface (SCI) In serial transmission, the SCI operates as described below. [1] The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. [2] After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a transmit-data-empty interrupt (TXI) is generated.
Section 14 Serial Communication Interface (SCI) Figure 14.6 shows an example of the operation for transmission in asynchronous mode. 1 Start bit 0 Data D0 D1 Parity Stop Start bit bit bit D7 0/1 1 0 Data D0 D1 Parity Stop bit bit D7 0/1 1 1 Idle state (mark state) TDRE TEND TXI interrupt Data written to TDR and TXI interrupt request generated TDRE flag cleared to 0 in request generated TXI interrupt handling routine TEI interrupt request generated 1 frame Figure 14.
Section 14 Serial Communication Interface (SCI) Serial data reception (asynchronous mode): Figure 14.7 shows a sample flowchart for serial reception. The following procedure should be used for serial data reception. Initialization [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin.
Section 14 Serial Communication Interface (SCI) [3] Error handling No ORER = 1? Yes Overrun error handling No FER = 1? Yes No Break? Yes Framing error handling Clear RE bit in SCR to 0 No PER = 1? Yes Parity error handling Clear ORER, PER, and FER flags in SSR to 0 Figure 14.7 Sample Serial Reception Flowchart (cont) Rev.6.00 Sep.
Section 14 Serial Communication Interface (SCI) In serial reception, the SCI operates as described below. [1] The SCI monitors the communication line, and if a 0 stop bit is detected, performs internal synchronization and starts reception. [2] The received data is stored in RSR in LSB-to-MSB order. [3] The parity bit and stop bit are received. After receiving these bits, the SCI carries out the following checks.
Section 14 Serial Communication Interface (SCI) Table 14.
Section 14 Serial Communication Interface (SCI) 14.3.3 Multiprocessor Communication Function The multiprocessor communication function performs serial communication using the multiprocessor format, in which a multiprocessor bit is added to the transfer data, in asynchronous mode. Use of this function enables data transfer to be performed among a number of processors sharing a single serial communication line.
Section 14 Serial Communication Interface (SCI) Clock See section 14.3.2, Operation in Asynchronous Mode. Transmitting station Serial communication line Receiving station A Receiving station B Receiving station C Receiving station D (ID= 01) (ID= 02) (ID= 03) (ID= 04) Serial data H'01 H'AA (MPB= 1) ID transmission cycle= receiving station specification (MPB= 0) Data transmission cycle= Data transmission to receiving station specified by ID Legend: MPB: Multiprocessor bit Figure 14.
Section 14 Serial Communication Interface (SCI) [1] [1] SCI initialization: Initialization Start of transmission Read TDRE flag in SSR [2] No TDRE = 1? Yes Write transmit data to TDR and set MPBT bit in SSR Clear TDRE flag to 0 No All data transmitted? Yes Read TEND flag in SSR No The TxD pin is automatically designated as the transmit data output pin. After the TE bit is set to 1, a frame of 1s is output, and transmission is enabled.
Section 14 Serial Communication Interface (SCI) In serial transmission, the SCI operates as described below. [1] The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. [2] After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a transmit-data-empty interrupt (TXI) is generated.
Section 14 Serial Communication Interface (SCI) Figure 14.11 shows an example of SCI operation for transmission using the multiprocessor format.
Section 14 Serial Communication Interface (SCI) Initialization [1] [1] SCI initialization: The RxD pin is automatically designated as the receive data input pin. [2] [2] ID reception cycle: Set the MPIE bit in SCR to 1. Start of reception Read MPIE bit in SCR Read ORER and FER flags in SSR FER ∨ ORER = 1? [3] SCI status check, ID reception and comparison: Read SSR and check that the RDRF flag is set to 1, then read the receive data in RDR and compare it with this station’s ID.
Section 14 Serial Communication Interface (SCI) [5] Error handling No ORER = 1? Yes Overrun error handling No FER = 1? Yes Yes Break? No Framing error handling Clear RE bit in SCR to 0 Clear ORER, PER, and FER flags in SSR to 0 Figure 14.12 Sample Multiprocessor Serial Reception Flowchart (cont) Rev.6.00 Sep.
Section 14 Serial Communication Interface (SCI) Figure 14.13 shows an example of SCI operation for multiprocessor format reception.
Section 14 Serial Communication Interface (SCI) 14.3.4 Operation in Synchronous Mode In synchronous mode, data is transmitted or received in synchronization with clock pulses, making it suitable for high-speed serial communication. Inside the SCI, the transmitter and receiver are independent units, enabling full-duplex communication by use of a common clock.
Section 14 Serial Communication Interface (SCI) Clock Either an internal clock generated by the built-in baud rate generator or an external serial clock input at the SCK pin can be selected, according to the setting of the C/A bit in SMR and the CKE1 and CKE0 bits in SCR. For details of SCI clock source selection, see table 14.9. When the SCI is operated on an internal clock, the serial clock is output from the SCK pin.
Section 14 Serial Communication Interface (SCI) [1] Set the clock selection in SCR. Be sure to clear bits RIE, TIE, TEIE, and MPIE, TE and RE, to 0. Start of initialization Clear TE and RE bits in SCR to 0 [2] Set the data transfer format in SMR and SCMR. Set CKE1 and CKE0 bits in SCR (TE, RE bits 0) [1] Set data transfer format in SMR and SCMR [2] Set value in BRR [3] Wait [3] Write a value corresponding to the bit rate to BRR. (Not necessary if an external clock is used.
Section 14 Serial Communication Interface (SCI) Serial data transmission (synchronous mode): Figure 14.16 shows a sample flowchart for serial transmission. The following procedure should be used for serial data transmission.
Section 14 Serial Communication Interface (SCI) In serial transmission, the SCI operates as described below. [1] The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to TDR, and transfers the data from TDR to TSR. [2] After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts transmission. If the TIE bit is set to 1 at this time, a transmit-data-empty interrupt (TXI) is generated.
Section 14 Serial Communication Interface (SCI) Transfer direction Serial clock Serial data Bit 7 Bit 0 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7 TDRE TEND TXI interrupt request generated Data written to TDR TXI interrupt and TDRE flag request generated cleared to 0 in TXI interrupt handling routine TEI interrupt request generated 1 frame Figure 14.17 Example of SCI Transmit Operation Serial data reception (synchronous mode): Figure 14.18 shows a sample flowchart for serial reception.
Section 14 Serial Communication Interface (SCI) Initialization [1] [1] Start of reception [2] [3] Receive error handling: If a receive error occurs, read the ORER flag in SSR, and after performing the appropriate error handling, clear the ORER flag to 0. Transfer cannot be resumed if the ORER flag is set to 1.
Section 14 Serial Communication Interface (SCI) In serial reception, the SCI operates as described below. [1] The SCI performs internal initialization in synchronization with serial clock input or output. [2] The received data is stored in RSR in LSB-to-MSB order. After reception, the SCI checks whether the RDRF flag is 0 and the receive data can be transferred from RSR to RDR. If this check is passed, the RDRF flag is set to 1, and the receive data is stored in RDR.
Section 14 Serial Communication Interface (SCI) Initialization [1] SCI initialization: [1] The TxD pin is designated as the transmit data output pin, and the RxD pin is designated as the receive data input pin, enabling simultaneous transmit and receive operations. Start of transmission/reception Read TDRE flag in SSR [2] [2] SCI status check and transmit data write: Read SSR and check that the TDRE flag is set to 1, then write transmit data to TDR and clear the TDRE flag to 0.
Section 14 Serial Communication Interface (SCI) 14.4 SCI Interrupts The SCI has four interrupt sources: the transmit-end interrupt (TEI) request, receive-error interrupt (ERI) request, receive-data-full interrupt (RXI) request, and transmit-data-empty interrupt (TXI) request. Table 14.12 shows the interrupt sources and their relative priorities. Individual interrupt sources can be enabled or disabled with the TIE, RIE, and TEIE bits in the SCR.
Section 14 Serial Communication Interface (SCI) Table 14.
Section 14 Serial Communication Interface (SCI) 14.5 Usage Notes The following points should be noted when using the SCI. Relation between Writes to TDR and the TDRE Flag: The TDRE flag in SSR is a status flag that indicates that transmit data has been transferred from TDR to TSR. When the SCI transfers data from TDR to TSR, the TDRE flag is set to 1. Data can be written to TDR regardless of the state of the TDRE flag.
Section 14 Serial Communication Interface (SCI) Break Detection and Processing (Asynchronous Mode Only): When framing error (FER) detection is performed, a break can be detected by reading the RxD pin value directly. In a break, the input from the RxD pin becomes all 0s, and so the FER flag is set, and the parity error flag (PER) may also be set. Note that, since the SCI continues the receive operation after receiving a break, even if the FER flag is cleared to 0, it will be set to 1 again.
Section 14 Serial Communication Interface (SCI) 16 clocks 8 clocks 0 7 15 0 7 15 0 Internal base clock Receive data (RxD) Start bit D0 D1 Synchronization sampling timing Data sampling timing Figure 14.21 Receive Data Sampling Timing in Asynchronous Mode Thus the receive margin in asynchronous mode is given by formula (1) below. 1 M = | (0.5 – Where M N D L F 2N ) – (L – 0.5) F – | D – 0.5 | N (1 + F) | × 100% ...
Section 14 Serial Communication Interface (SCI) Restrictions on Use of DMAC* or DTC • When an external clock source is used as the serial clock, the transmit clock should not be input until at least 5 φ clock cycles after TDR is updated by the DMAC* or DTC. Misoperation may occur if the transmit clock is input within 4 φ clocks after TDR is updated. (Figure 14.22) • When RDR is read by the DMAC* or DTC, be sure to set the activation source to the relevant SCI receive-data-full interrupt (RXI).
Section 14 Serial Communication Interface (SCI) Operation in Case of Mode Transition • Transmission Operation should be stopped (by clearing TE, TIE, and TEIE to 0) before making a module stop mode or software standby mode transition. TSR, TDR, and SSR are reset. The output pin states in module stop mode or software standby mode depend on the port settings, and becomes high-level output after the relevant mode is cleared.
Section 14 Serial Communication Interface (SCI) All data transmitted? No [1] Yes Read TEND flag in SSR TEND = 1? No Yes TE = 0 [2] Transition to software standby mode, etc. [3] [1] Data being transmitted is interrupted. After exiting software standby mode, etc.
Section 14 Serial Communication Interface (SCI) End of transmission Start of transmission Transition to software standby Exit from software standby TE bit Port input/output SCK output pin TxD output pin Port input/output High output Start Port Stop Port input/output Port SCI TxD output High output SCI TxD output Figure 14.
Section 14 Serial Communication Interface (SCI) Read RDRF flag in SSR RDRF = 1? No [1] [1] Receive data being received becomes invalid. [2] [2] Includes module stop mode. Yes Read receive data in RDR RE = 0 Transition to software standby mode, etc. Exit from software standby mode, etc. Change operating mode? No Yes Initialization RE = 1 Figure 14.26 Sample Flowchart for Mode Transition during Reception Rev.6.00 Sep.
Section 14 Serial Communication Interface (SCI) Rev.6.00 Sep.
Section 15 Smart Card Interface Section 15 Smart Card Interface 15.1 Overview The SCI supports an IC card (smart card) interface conforming to ISO/IEC 7816-3 (identification card) as a serial communication interface extension function. Switching between the normal serial communication interface and the smart card interface is carried out by means of a register setting. 15.1.1 Features Features of the smart card interface supported by the chip is as follows.
Section 15 Smart Card Interface 15.1.2 Block Diagram Bus interface Figure 15.1 shows a block diagram of the smart card interface.
Section 15 Smart Card Interface 15.1.3 Pin Configuration Table 15.1 shows the smart card interface pin configuration. Table 15.
Section 15 Smart Card Interface 15.1.4 Register Configuration Table 15.2 shows the registers used by the smart card interface. Details of SMR, BRR, SCR, TDR, RDR, and MSTPCR are the same as for the normal SCI function: see the register descriptions in section 14, Serial Communication Interface (SCI). Table 15.
Section 15 Smart Card Interface 15.2 Register Descriptions Registers added with the smart card interface and bits for which the function changes are described here. 15.2.1 Bit Smart Card Mode Register (SCMR) : 7 6 5 4 3 2 1 0 — — — — SDIR SINV — SMIF Initial value : 1 1 1 1 0 0 1 0 R/W — — — — R/W R/W — R/W : SCMR is an 8-bit readable/writable register that selects the smart card interface function. SCMR is initialized to H'F2 by a reset and in hardware standby mode.
Section 15 Smart Card Interface Bit 2—Smart Card Data Invert (SINV): Specifies inversion of the data logic level. This function is used together with the SDIR bit for communication with an inverse convention card. The SINV bit does not affect the logic level of the parity bit. For parity-related setting procedures, see section 15.3.4, Register Settings.
Section 15 Smart Card Interface 15.2.2 Serial Status Register (SSR) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 TDRE RDRF ORER ERS PER TEND MPB MPBT 1 0 0 0 0 1 0 0 R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R R R/W Note: * Only 0 can be written to bits 7 to 3, to clear these flags. Bit 4 of SSR has a different function in smart card interface mode. Coupled with this, the setting conditions for bit 2, TEND, are also different.
Section 15 Smart Card Interface Bits 3 to 0—Operate in the same way as for the normal SCI. For details, see section 14.2.7, Serial Status Register (SSR). However, the setting conditions for the TEND bit, are as shown below.
Section 15 Smart Card Interface 15.2.3 Serial Mode Register (SMR) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 GM BLK PE* O/E BCP1 BCP0 CKS1 CKS0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Note: * The DMAC is not supported in the H8S/2321. The function of bits 7, 6, 3, and 2 of SMR changes in smart card interface mode. Bit 7—GSM Mode (GM): Sets the smart card interface function to GSM mode. This bit is cleared to 0 when the normal smart card interface is used.
Section 15 Smart Card Interface Bit 6—Block Transfer Mode (BLK): Selects block transfer mode. Bit 6 BLK Description 0 Normal smart card interface mode operation 1 (Initial value) • Error signal transmission/detection and automatic data retransmission performed • TXI interrupt generated by TEND flag • TEND flag set 12.5 etu after start of transmission (11.
Section 15 Smart Card Interface 15.2.4 Bit Serial Control Register (SCR) : Initial value : R/W : 7 6 5 4 3 2 1 0 TIE RIE TE RE MPIE TEIE CKE1 CKE0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W In smart card interface mode, the function of bits 1 and 0 of SCR changes when bit 7 of the serial mode register (SMR) is set to 1. Bits 7 to 2—Operate in the same way as for the normal SCI. For details, see section 14.2.6, Serial Control Register (SCR).
Section 15 Smart Card Interface 15.3 Operation 15.3.1 Overview The main functions of the smart card interface are as follows. • One frame consists of 8-bit data plus a parity bit. • In transmission, a guard time of at least 2 etu (1 etu in block transfer mode) (elementary time unit: the time for transfer of 1 bit) is left between the end of the parity bit and the start of the next frame. • If a parity error is detected during reception, a low error signal level is output for one etu period, 10.
Section 15 Smart Card Interface VCC TxD I/O RxD SCK Rx (port) Chip Data line Clock line Reset line CLK RST IC card Connected equipment Figure 15.2 Schematic Diagram of Smart Card Interface Pin Connections Note: If an IC card is not connected, and the TE and RE bits are both set to 1, closed transmission/reception is possible, enabling self-diagnosis to be carried out. Rev.6.00 Sep.
Section 15 Smart Card Interface 15.3.3 Data Format Normal Transfer Mode: Figure 15.3 shows the smart card interface data format in the normal transfer mode. In reception in this mode, a parity check is carried out on each frame. If an error is detected an error signal is sent back to the transmitting end, and retransmission of the data is requested. If an error signal is sampled during transmission, the same data is retransmitted.
Section 15 Smart Card Interface The operation sequence is as follows. [1] When the data line is not in use it is in the high-impedance state, and is fixed high with a pullup resistor. [2] The transmitting station starts transfer of one frame of data. The data frame starts with a start bit (Ds, low-level), followed by 8 data bits (D0 to D7) and a parity bit (Dp). [3] With the smart card interface, the data line then returns to the high-impedance state. The data line is pulled high with a pull-up resistor.
Section 15 Smart Card Interface 15.3.4 Register Settings Table 15.3 shows a bit map of the registers used by the smart card interface. Bits indicated as 0 or 1 must be set to the value shown. The setting of other bits is described below. Table 15.
Section 15 Smart Card Interface Smart Card Mode Register (SCMR) Settings: The SDIR bit is cleared to 0 if the IC card is of the direct convention type, and set to 1 if of the inverse convention type. The SINV bit is cleared to 0 if the IC card is of the direct convention type, and set to 1 if of the inverse convention type. The SMIF bit is set to 1 when the smart card interface is used.
Section 15 Smart Card Interface 15.3.5 Clock Only an internal clock generated by the built-in baud rate generator can be used as the transmit/receive clock for the smart card interface. The bit rate is set with BRR and the CKS1, CKS0, BCP1, and BCP0 bits in SMR. The formula for calculating the bit rate is as shown below. Table 15.5 shows some sample bit rates. If clock output is selected by setting CKE0 to 1, the clock is output from the SCK pin.
Section 15 Smart Card Interface The method of calculating the value to be set in the bit rate register (BRR) from the operating frequency and bit rate, on the other hand, is shown below. N is an integer, 0 ≤ N ≤ 255, and the smaller error is specified. N= φ S×2 2n+1 × 106 – 1 ×B Table 15.6 Examples of BRR Settings for Bit Rate B (bits/s) (When n = 0 and S = 372) φ (MHz) 7.1424 10.00 10.7136 13.00 14.2848 16.00 18.00 20.00 25.
Section 15 Smart Card Interface 15.3.6 Data Transfer Operations Initialization: Before transmitting or receiving data, initialize the SCI as described below. Initialization is also necessary when switching from transmit mode to receive mode, or vice versa. [1] Clear the TE and RE bits in SCR to 0. [2] Clear the error flags ERS, PER, and ORER in SSR to 0. [3] Set the GM, BLK, O/E, BCP1, BCP0, CKS1, and CKS0 bits in SMR, and set the PE bit to 1. [4] Set the SMIF, SDIR, and SINV bits in SCMR.
Section 15 Smart Card Interface Serial Data Transmission (Except Block Transfer Mode): As data transmission in smart card mode involves error signal sampling and retransmission processing, the processing procedure is different from that for the normal SCI. Figure 15.4 shows a flowchart for transmitting, and figure 15.5 shows the relation between a transmit operation and the internal registers. [1] Perform smart card interface mode initialization as described above in Initialization.
Section 15 Smart Card Interface Start Initialization Start of transmission ERS = 0? No Yes Error handling No TEND = 1? Yes Write data to TDR, and clear TDRE flag in SSR to 0 No All data transmitted? Yes No ERS = 0? Yes Error handling No TEND = 1? Yes Clear TE bit to 0 End Figure 15.4 Sample Transmission Flowchart Rev.6.00 Sep.
Section 15 Smart Card Interface TDR (1) Data write Data 1 (2) Transfer from TDR to TSR Data 1 (3) Serial data output Data 1 TSR (shift register) Data 1 ; Data remains in TDR Data 1 I/O signal line output In case of normal transmission: TEND flag is set In case of transmit error: ERS flag is set Steps (2) and (3) above are repeated until the TEND flag is set Note: When the ERS flag is set, it should be cleared until transfer of the last bit (D7 in LSB-first transmission, D0 in MSB-first transmissi
Section 15 Smart Card Interface Serial Data Reception (Except Block Transfer Mode): Data reception in smart card mode uses the same processing procedure as for the normal SCI. Figure 15.7 shows an example of the transmission processing flow. [1] Perform smart card interface mode initialization as described above in Initialization. [2] Check that the ORER flag and PER flag in SSR are cleared to 0.
Section 15 Smart Card Interface With the above processing, interrupt handling or data transfer by the DMAC* or DTC is possible. If reception ends and the RDRF flag is set to 1 while the RIE bit is set to 1 and interrupt requests are enabled, a receive data full interrupt (RXI) request will be generated. If an error occurs in reception and either the ORER flag or the PER flag is set to 1, a transmit/receive-error interrupt (ERI) request will be generated.
Section 15 Smart Card Interface Specified pulse width Specified pulse width SCK SCR write (CKE0 = 0) SCR write (CKE0 = 1) Figure 15.8 Timing for Fixing Clock Output Interrupt Operation (Except Block Transfer Mode): There are three interrupt sources in smart card interface mode: transmit-data-empty interrupt (TXI) requests, transmit/receive-error interrupt (ERI) requests, and receive-data-full interrupt (RXI) requests. The transmit-end interrupt (TEI) request is not used in this mode.
Section 15 Smart Card Interface Data Transfer Operation by DMAC* or DTC: In smart card mode, as with the normal SCI, transfer can be carried out using the DMAC* or DTC. In a transmit operation, the TDRE flag is also set to 1 at the same time as the TEND flag in SSR, and a TXI interrupt is generated. If the TXI request is designated beforehand as a DMAC* or DTC activation source, the DMAC* or DTC will be activated by the TXI request, and transfer of the transmit data will be carried out.
Section 15 Smart Card Interface 15.3.7 Operation in GSM Mode Switching the Mode: When switching between smart card interface mode and software standby mode, the following switching procedure should be followed in order to maintain the clock duty. • When changing from smart card interface mode to software standby mode [1] Set the data register (DR) and data direction register (DDR) corresponding to the SCK pin to the value for the fixed output state in software standby mode.
Section 15 Smart Card Interface Powering On: To secure the clock duty from power-on, the following switching procedure should be followed. [1] The initial state is port input and high impedance. Use a pull-up resistor or pull-down resistor to fix the potential. [2] Fix the SCK pin to the specified output level with the CKE1 bit in SCR. [3] Set SMR and SCMR, and switch to smart card mode operation. [4] Set the CKE0 bit in SCR to 1 to start clock output. 15.3.
Section 15 Smart Card Interface 15.4 Usage Notes The following points should be noted when using the SCI as a smart card interface. Receive Data Sampling Timing and Receive Margin in Smart Card Interface Mode: In smart card interface mode, the SCI operates on a base clock with a frequency of 32, 64, 372, or 256 times the transfer rate (determined by bits BCP1 and BCP0). In reception, the SCI samples the falling edge of the start bit using the base clock, and performs internal synchronization.
Section 15 Smart Card Interface Thus the receive margin in asynchronous mode is given by the following formula. M =⎥ (0.5 – Where M: N: D: L: F: 1 2N ) – (L – 0.5) F – ⎥ D – 0.5⎥ N (1 + F)⎥ × 100% Receive margin (%) Ratio of bit rate to clock (N = 32, 64, 372, 256) Clock duty (D = 0 to 1.0) Frame length (L = 10) Absolute value of clock frequency deviation Assuming values of F = 0, D = 0.5, and N=372 in the above formula, the receive margin formula is as follows. When D = 0.5 and F = 0, M = (0.
Section 15 Smart Card Interface Retransfer Operations (Except Block Transfer Mode): Retransfer operations are performed by the SCI in receive mode and transmit mode as described below. • Retransfer operation when SCI is in receive mode Figure 15.11 illustrates the retransfer operation when the SCI is in receive mode. [1] If an error is found when the received parity bit is checked, the PER bit in SSR is automatically set to 1.
Section 15 Smart Card Interface • Retransfer operation when SCI is in transmit mode Figure 15.12 illustrates the retransfer operation when the SCI is in transmit mode. [6] If an error signal is sent back from the receiving end after transmission of one frame is completed, the ERS bit in SSR is set to 1. If the RIE bit in SCR is enabled at this time, an ERI interrupt request is generated. The ERS bit in SSR should be kept cleared to 0 until the next parity bit is sampled.
Section 15 Smart Card Interface Rev.6.00 Sep.
Section 16 A/D Converter (8 Analog Input Channel Version) Section 16 A/D Converter (8 Analog Input Channel Version) 16.1 Overview The chip incorporates a successive-approximations type 10-bit A/D converter that allows up to eight analog input channels to be selected. 16.1.
Section 16 A/D Converter (8 Analog Input Channel Version) 16.1.2 Block Diagram Figure 16.1 shows a block diagram of the A/D converter.
Section 16 A/D Converter (8 Analog Input Channel Version) 16.1.3 Pin Configuration Table 16.1 summarizes the input pins used by the A/D converter. The AVCC and AVSS pins are the power supply pins for the analog block in the A/D converter. The Vref pin is the A/D conversion reference voltage pin. The eight analog input pins are divided into two groups: group 0 (AN0 to AN3), and group 1 (AN4 to AN7). Table 16.
Section 16 A/D Converter (8 Analog Input Channel Version) 16.1.4 Register Configuration Table 16.2 summarizes the registers of the A/D converter. Table 16.
Section 16 A/D Converter (8 Analog Input Channel Version) 16.2 Register Descriptions 16.2.1 A/D Data Registers A to D (ADDRA to ADDRD) Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 — — — — — — Initial value : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R R R R R R R R R R R R R R R R : There are four 16-bit read-only ADDR registers, ADDRA to ADDRD, used to store the results of A/D conversion.
Section 16 A/D Converter (8 Analog Input Channel Version) 16.2.2 A/D Control/Status Register (ADCSR) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 ADF ADIE ADST SCAN CKS CH2 CH1 CH0 0 0 0 0 0 0 0 0 R/(W)* R/W R/W R/W R/W R/W R/W R/W Note: * Only 0 can be written to bit 7, to clear this flag. ADCSR is an 8-bit readable/writable register that controls A/D conversion operations and shows the status of the operation.
Section 16 A/D Converter (8 Analog Input Channel Version) Bit 5—A/D Start (ADST): Selects starting or stopping of A/D conversion. Holds a value of 1 during A/D conversion. The ADST bit can be set to 1 by software, a timer conversion start trigger, or the A/D external trigger input pin (ADTRG). Bit 5 ADST Description 0 A/D conversion stopped 1 • Single mode: A/D conversion is started.
Section 16 A/D Converter (8 Analog Input Channel Version) Group Selection Channel Selection Description CH2 CH1 CH0 0 0 0 AN0 (Initial value) AN0 1 AN1 AN0, AN1 0 AN2 AN0 to AN2 1 AN3 AN0 to AN3 0 AN4 AN4 1 AN5 AN4, AN5 0 AN6 AN4 to AN6 1 AN7 AN4 to AN7 1 1 0 1 16.2.
Section 16 A/D Converter (8 Analog Input Channel Version) Bits 5, 4, 1, and 0—Reserved: These bits cannot be modified and are always read as 1. Bit 3—Clock Select 1 (CKS1): Used together with the CKS bit in ADCSR to set the A/D conversion time. See the description of the CKS bit for details. Bit 2—Channel Select 3 (CH3): Reserved. A value of 1 must be written to this bit. 16.2.
Section 16 A/D Converter (8 Analog Input Channel Version) 16.3 Interface to Bus Master ADDRA to ADDRD are 16-bit registers, and the data bus to the bus master is 8 bits wide. Therefore, in accesses by the bus master, the upper byte is accessed directly, but the lower byte is accessed via a temporary register (TEMP). A data read from ADDR is performed as follows. When the upper byte is read, the upper byte value is transferred to the CPU and the lower byte value is transferred to TEMP.
Section 16 A/D Converter (8 Analog Input Channel Version) 16.4 Operation The A/D converter operates by successive approximations with 10-bit resolution. It has two operating modes: single mode and scan mode. 16.4.1 Single Mode (SCAN = 0) Single mode is selected when A/D conversion is to be performed on a single channel only. A/D conversion is started when the ADST bit is set to 1 by software or by external trigger input.
Section 16 A/D Converter (8 Analog Input Channel Version) Set* ADIE ADST A/D conversion starts Set* Set* Clear* Clear* ADF State of channel 0 (AN0) Idle State of channel 1 (AN1) Idle State of channel 2 (AN2) Idle State of channel 3 (AN3) Idle A/D conversion 1 Idle A/D conversion 2 Idle ADDRA ADDRB Read conversion result A/D conversion result 1 Read conversion result A/D conversion result 2 ADDRC ADDRD Note: * Vertical arrows ( ) indicate instructions executed by software.
Section 16 A/D Converter (8 Analog Input Channel Version) 16.4.2 Scan Mode (SCAN = 1) Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the ADST bit is set to 1 by software, or by timer or external trigger input, A/D conversion starts on the first channel in the group (AN0). When two or more channels are selected, after conversion of the first channel ends, conversion of the second channel (AN1) starts immediately.
Section 16 A/D Converter (8 Analog Input Channel Version) Continuous A/D conversion Clear*1 Set*1 ADST Clear*1 ADF State of channel 0 (AN0) State of channel 1 (AN1) State of channel 2 (AN2) A/D conversion time Idle Idle A/D conversion 1 Idle Idle A/D conversion 2 Idle Idle A/D conversion 4 A/D conversion 5 *2 Idle A/D conversion 3 State of channel 3 (AN3) Idle Idle Transfer A/D conversion result 1 ADDRA ADDRB A/D conversion result 4 A/D conversion result 2 ADDRC A/D conversion result
Section 16 A/D Converter (8 Analog Input Channel Version) 16.4.3 Input Sampling and A/D Conversion Time The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog input at a time tD after the ADST bit is set to 1, then starts conversion. Figure 16.5 shows the A/D conversion timing. Table 16.4 indicates the A/D conversion time. As indicated in figure 16.5, the A/D conversion time includes tD and the input sampling time.
Section 16 A/D Converter (8 Analog Input Channel Version) Table 16.4 A/D Conversion Time (Single Mode) CKS1 = 0 CKS1 = 1 CKS = 0 CKS = 1 CKS = 0 CKS = 1 Item Symbol Min Typ Max Min Typ Max Min Typ Max Min Typ Max A/D conversion start delay tD 18 — 4 — 5 10 — 17 6 — 9 Input sampling time tSPL — 127 — — 15 — — 63 — — 31 — A/D conversion time tCONV 515 — 67 — 68 259 — 266 131 — 33 530 134 Note: Values in the table are the number of states. Table 16.
Section 16 A/D Converter (8 Analog Input Channel Version) φ ADTRG Internal trigger signal ADST A/D conversion Figure 16.6 External Trigger Input Timing 16.5 Interrupts The A/D converter generates an A/D conversion end interrupt (ADI) at the end of A/D conversion. ADI interrupt requests can be enabled or disabled by means of the ADIE bit in ADCSR. The DTC or DMAC* can be activated by an ADI interrupt.
Section 16 A/D Converter (8 Analog Input Channel Version) 16.6 Usage Notes The following points should be noted when using the A/D converter. Setting Range of Analog Power Supply and Other Pins 1. Analog input voltage range The voltage applied to analog input pins ANn during A/D conversion should be in the range AVSS ≤ ANn ≤ Vref. 2. Relation between AVCC, AVSS and VCC, VSS As the relationship between AVCC, AVSS and VCC, VSS, set AVSS = VSS.
Section 16 A/D Converter (8 Analog Input Channel Version) frequently, as in scan mode, if the current charged and discharged by the capacitance of the sample-and-hold circuit in the A/D converter exceeds the current input via the input impedance (Rin), an error will arise in the analog input pin voltage. Careful consideration is therefore required when deciding the circuit constants. AVCC Vref 100 Ω Rin* 2 *1 AN0 to AN7 *1 0.1 μF Notes: AVSS Values are reference values. 1. 10 μF 0.01 μF 2.
Section 16 A/D Converter (8 Analog Input Channel Version) • Full-scale error The deviation of the analog input voltage value from the ideal A/D conversion characteristic when the digital output changes from B'1111111110 to B'1111111111. (See figure 16.9.) • Quantization error The deviation inherent in the A/D converter, given by 1/2 LSB. (See figure 16.8.) • Nonlinearity error The error with respect to the ideal A/D conversion characteristic between the zero voltage and the full-scale voltage.
Section 16 A/D Converter (8 Analog Input Channel Version) Full-scale error Digital output Ideal A/D conversion characteristic Nonlinearity error Actual A/D conversion characteristic FS Offset error Analog input voltage Figure 16.9 A/D Conversion Precision Definitions (2) Permissible Signal Source Impedance: The chip’s analog input is designed so that conversion precision is guaranteed for an input signal for which the signal source impedance is 5 kΩ or less.
Section 16 A/D Converter (8 Analog Input Channel Version) Influences on Absolute Precision: Adding capacitance results in coupling with GND, and therefore noise in GND may adversely affect absolute precision. Be sure to make the connection to an electrically stable GND such as AVSS. Care is also required to insure that filter circuits do not communicate with digital signals on the mounting board, so acting as antennas. Chip Sensor output impedance Max.
Section 17 D/A Converter Section 17 D/A Converter 17.1 Overview The chip includes an 8-bit resolution D/A converter with from two analog signal output channels. 17.1.1 Features D/A converter features are listed below. • 8-bit resolution • Two output channels • Maximum conversion time of 10 µs (with 20 pF load) • Output voltage of 0 V to Vref • D/A output hold function in software standby mode • Module stop mode can be set ⎯ As the initial setting, D/A converter operation is halted.
Section 17 D/A Converter 17.1.2 Block Diagram Figure 17.1 shows a block diagram of the D/A converter. Internal data bus Bus interface Module data bus Vref DACR 8-bit D/A converter DADR1 DA1 DADR0 AVCC DA0 AVSS Control circuit Legend: DACR: D/A control register DADR0, 1: D/A data registers 0, 1 Figure 17.1 Block Diagram of D/A Converter Rev.6.00 Sep.
Section 17 D/A Converter 17.1.3 Pin Configuration Table 17.1 summarizes the input and output pins of the D/A converter. Table 17.1 Pin Configuration Pin Name Symbol I/O Function Analog power pin AVCC Input Analog power source Analog ground pin AVSS Input Analog ground and reference voltage Analog output pin 0 DA0 Output Channel 0 analog output Analog output pin 1 DA1 Output Channel 1 analog output Reference voltage pin Vref Input Analog reference voltage 17.1.
Section 17 D/A Converter 17.2 Register Descriptions 17.2.1 D/A Data Registers 0, 1 (DADR0, DADR1) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W DADR0, DADR1 are 8-bit readable/writable registers that store data for conversion. Whenever output is enabled, the values in DADR0 and DADR1 are converted and output from the analog output pins. DADR0 and DADR1 are each initialized to H'00 by a reset and in hardware standby mode. 17.2.
Section 17 D/A Converter Bit 6—D/A Output Enable 0 (DAOE0): Controls D/A conversion and analog output. Bit 6 DAOE0 Description 0 Analog output DA0 is disabled 1 Channel 0 D/A conversion is enabled; analog output DA0 is enabled (Initial value) Bit 5—D/A Enable (DAE): Used together with the DAOE0 and DAOE1 bits to control D/A conversion. When the DAE bit is cleared to 0, channel 0 and 1 D/A conversions are controlled independently.
Section 17 D/A Converter 17.2.3 Module Stop Control Register (MSTPCR) MSTPCRH Bit MSTPCRL : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR is a 16-bit readable/writable register that performs module stop mode control.
Section 17 D/A Converter [2] Set the DAOE0 bit in DACR01 to 1. D/A conversion is started and the DA0 pin becomes an output pin. The conversion result is output after the conversion time has elapsed. The output value is expressed by the following formula: DADR contents 256 × Vref The conversion results are output continuously until DADR0 is written to again or the DAOE0 bit is cleared to 0. [3] If DADR0 is written to again, the new data is immediately converted.
Section 17 D/A Converter Rev.6.00 Sep.
Section 18 RAM Section 18 RAM 18.1 Overview The H8S/2329B and H8S/2324S have 32 kbytes of on-chip high-speed static RAM, the H8S/2328 (H8S/2328B in flash memory version), H8S/2327, H8S/2326, H8S/2323, and H8S/2322R have 8 kbytes, and the H8S/2321 and H8S/2320 have 4 kbytes. The RAM is connected to the CPU by a 16-bit data bus, enabling one-state access by the CPU to both byte data and word data. This makes it possible to perform fast word data transfer.
Section 18 RAM 18.1.2 Register Configuration The on-chip RAM is controlled by SYSCR. Table 18.1 shows the address and initial value of SYSCR. Table 18.1 RAM Register Name Abbreviation R/W Initial Value Address* System control register SYSCR R/W H'01 H'FF39 Note: * Lower 16 bits of the address. 18.2 Register Descriptions 18.2.
Section 18 RAM 18.3 Operation When the RAME bit is set to 1, accesses to addresses H'FFDC00 to H'FFFBFF are directed to the on-chip RAM. When the RAME bit is cleared to 0, the off-chip address space is accessed. Since the on-chip RAM is connected to the CPU by an internal 16-bit data bus, it can be written to and read in byte or word units. Each type of access can be performed in one state. Even addresses use the upper 8 bits, and odd addresses use the lower 8 bits.
Section 18 RAM Rev.6.00 Sep.
Section 19 ROM Section 19 ROM 19.1 Overview The Series has 512, 384, or 256 kbytes of on-chip flash memory, or 256, 128, or 32 kbytes of onchip mask ROM. The ROM is connected to the bus master via a 16-bit data bus, enabling both byte and word data to be accessed in one state. Instruction fetching is thus speeded up, and processing speed increased. The on-chip ROM is enabled and disabled by means of the mode pins (MD2 to MD0) and the EAE bit in BCRL.
Section 19 ROM 19.1.2 Register Configuration The operating mode of the chip is controlled by the mode pins and the BCRL register. The ROMrelated registers are shown in table 19.1. Table 19.1 ROM Registers Register Name Abbreviation R/W Initial Value Address* Mode control register MDCR R/W Undefined H'FF3B Bus controller register BCRL R/W Undefined H'FED5 Note: * Lower 16 bits of the address. 19.2 Register Descriptions 19.2.
Section 19 ROM 19.2.2 Bit Bus Control Register L (BCRL) : Initial value : R/W : 7 6 5 4 3 2 1 0 BRLE BREQOE EAE — DDS — WDBE WAITE 0 0 1 1 1 1 0 0 R/W R/W R/W R/W R/W R/W R/W R/W Enabling or disabling of part of the on-chip ROM area in the chip can be selected by means of the EAE bit in BCRL. For details of the other bits in BCRL, see section 6.2.5, Bus Control Register L (BCRL).
Section 19 ROM Table 19.
Section 19 ROM 2. Note that in the mode 10 and mode 11 boot modes, the on-chip ROM that can be used immediately after all flash memory is erased by the boot program is the 64-kbyte area from H'000000 to H'00FFFF. 3. Apart from the fact that flash memory can be erased and programmed, operation is the same as in advanced expanded mode with on-chip ROM enabled. 4. Apart from the fact that flash memory can be erased and programmed, operation is the same as in advanced single-chip mode. 5.
Section 19 ROM 19.4 Overview of Flash Memory (H8S/2329B F-ZTAT) 19.4.1 Features The H8S/2329B F-ZTAT has 384 kbytes of on-chip flash memory. The features of the flash memory are summarized below. • Four flash memory operating modes ⎯ Program mode ⎯ Erase mode ⎯ Program-verify mode ⎯ Erase-verify mode • Programming/erase methods The flash memory is programmed 128 bytes at a time. Erasing is performed by block erase (in single-block units).
Section 19 ROM • PROM mode Flash memory can be programmed/erased in PROM mode, using a PROM programmer, as well as in on-board programming mode. 19.4.
Section 19 ROM 19.4.3 Flash Memory Operating Modes Mode Transitions: When the mode pins are set in the reset state and a reset-start is executed, the chip enters one of the operating modes shown in figure 19.3. In user mode, flash memory can be read but not programmed or erased. Flash memory can be programmed and erased in boot mode, user program mode, and PROM mode.
Section 19 ROM 19.4.4 On-Board Programming Modes • Boot mode 1. Initial state The old program version or data remains written in the flash memory. The user should prepare the programming control program and new application program beforehand in the host. 2. Programming control program transfer When boot mode is entered, the boot program in the chip (originally incorporated in the chip) is started and the programming control program in the host is transferred to RAM via SCI communication.
Section 19 ROM • User program mode 1. Initial state (1) The program that will transfer the programming/erase control program to on-chip RAM should be written into the flash memory by the user beforehand. (2) The programming/erase control program should be prepared in the host or in the flash memory. 2. Programming/erase control program transfer Executes the transfer program in the flash memory, and transfers the programming/erase control program to RAM.
Section 19 ROM 19.4.5 Flash Memory Emulation in RAM Reading Overlap RAM Data in User Mode and User Program Mode: Emulation should be performed in user mode or user program mode. When the emulation block set in RAMER is accessed while the emulation function is being executed, data written in the overlap RAM is read. SCI Flash memory RAM Emulation block Overlap RAM (emulation is performed on data written in RAM) Application program Execution state Figure 19.
Section 19 ROM Writing Overlap RAM Data in User Program Mode: When overlap RAM data is confirmed, the RAMS bit is cleared, RAM overlap is released, and writes should actually be performed to the flash memory. When the programming control program is transferred to RAM, ensure that the transfer destination and the overlap RAM do not overlap, as this will cause data in the overlap RAM to be rewritten.
Section 19 ROM 19.4.7 Block Configuration The flash memory is divided into five 64-kbyte blocks, one 32-kbyte block, and eight 4-kbyte blocks. Address H'00000 4 kbytes × 8 32 kbytes 64 kbytes 384 kbytes 64 kbytes 64 kbytes 64 kbytes 64 kbytes Address H'5FFFF Figure 19.8 Flash Memory Block Configuration Rev.6.00 Sep.
Section 19 ROM 19.4.8 Pin Configuration The flash memory is controlled by means of the pins shown in table 19.5. Table 19.
Section 19 ROM 19.4.9 Register Configuration The registers used to control the on-chip flash memory when enabled are shown in table 19.6. In order to access the FLMCR1, FLMCR2, EBR1, and EBR2 registers, the FLSHE bit must be set to 1 in SYSCR2 (except RAMER). Table 19.
Section 19 ROM 19.5 Register Descriptions 19.5.1 Flash Memory Control Register 1 (FLMCR1) Bit : 7 6 5 4 3 2 1 0 FWE SWE ESU PSU EV PV E P Initial value : 1 0 0 0 0 0 0 0 R/W R R/W R/W R/W R/W R/W R/W R/W : FLMCR1 is an 8-bit register used for flash memory operating mode control. Program-verify mode or erase-verify mode is entered by setting SWE to 1, then setting the EV or PV bit.
Section 19 ROM Bit 5—Erase Setup Bit (ESU): Prepares for a transition to erase mode. Do not set the SWE, PSU, EV, PV, E, or P bit at the same time. Bit 5 ESU Description 0 Erase setup cleared 1 Erase setup (Initial value) [Setting condition] When SWE = 1 Bit 4—Program Setup Bit (PSU): Prepares for a transition to program mode. Do not set the SWE, ESU, EV, PV, E, or P bit at the same time.
Section 19 ROM Bit 2—Program-Verify (PV): Selects program-verify mode transition or clearing. Do not set the SWE, ESU, PSU, EV, E, or P bit at the same time. Bit 2 PV Description 0 Program-verify mode cleared 1 Transition to program-verify mode (Initial value) [Setting condition] When SWE = 1 Bit 1—Erase (E): Selects erase mode transition or clearing. Do not set the SWE, ESU, PSU, EV, PV, or P bit at the same time.
Section 19 ROM 19.5.2 Bit Flash Memory Control Register 2 (FLMCR2) : 7 6 5 4 3 2 1 0 FLER — — — — — — — Initial value : 0 0 0 0 0 0 0 0 R/W R — — — — — — — : FLMCR2 is an 8-bit register that controls the flash memory operating modes. FLMCR2 is initialized to H'00 by a reset, and in hardware standby mode and software standby mode. When on-chip flash memory is disabled, a read will return H'00 and writes are invalid.
Section 19 ROM 19.5.3 Bit Erase Block Register 1 (EBR1) : EBR1 Initial value : R/W : 7 6 5 4 3 2 1 0 EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W EBR1 is an 8-bit register that specifies the flash memory erase area block by block. EBR1 is initialized to H'00 by a reset, in hardware standby mode and software standby mode, and the SWE bit in FLMCR1 is not set. When a bit in EBR1 is set, the corresponding block can be erased.
Section 19 ROM Table 19.
Section 19 ROM Bit 3—Flash Memory Control Register Enable (FLSHE): Controls CPU access to the flash memory control registers (FLMCR1, FLMCR2, EBR1, and EBR2). Writing 1 to the FLSHE bit enables the flash memory control registers to be read and written to. Clearing FLSHE to 0 designates these registers as unselected (the register contents are retained).
Section 19 ROM Bit 3—RAM Select (RAMS): Specifies selection or non-selection of flash memory emulation in RAM. When RAMS = 1, all flash memory blocks are program/erase-protected.
Section 19 ROM 19.6 On-Board Programming Modes When pins are set to on-board programming mode, program/erase/verify operations can be performed on the on-chip flash memory. There are two on-board programming modes: boot mode and user program mode. The pin settings for transition to each of these modes are shown in table 19.9. For a diagram of the transitions to the various flash memory modes, see figure 19.3. Table 19.
Section 19 ROM 19.6.1 Boot Mode When boot mode is used, the flash memory programming control program must be prepared in the host beforehand. The channel 1 SCI to be used is set to asynchronous mode. When a reset-start is executed after the H8S/2329B F-ZTAT chip’s pins have been set to boot mode, the boot program built into the chip is started and the programming control program prepared in the host is serially transmitted to the chip via the SCI.
Section 19 ROM Start Set pins to boot mode and execute reset-start Host transfers data (H'00) continuously at prescribed bit rate Chip measures low period of H'00 data transmitted by host Chip calculates bit rate and sets value in bit rate register After bit rate adjustment, chip transmits one H'00 data byte to host to indicate end of adjustment Host confirms normal reception of bit rate adjustment end indication (H'00), and transmits one H'55 data byte After receiving H'55, chip transmits one H'AA data by
Section 19 ROM Automatic SCI Bit Rate Adjustment: When boot mode is initiated, the H8S/2329B F-ZTAT chip measures the low period of the asynchronous SCI communication data (H'00) transmitted continuously from the host. The SCI transmit/receive format should be set as follows: 8-bit data, 1 stop bit, no parity. The chip calculates the bit rate of the transmission from the host from the measured low period, and transmits one H'00 byte to the host to indicate the end of bit rate adjustment.
Section 19 ROM H'FF7C00 H'FF83FF Boot program area* (2 kbytes) Programming control program area (30 kbytes) H'FFFBFF Note: * The boot program area cannot be used until a transition is made to the execution state for the programming control program transferred to RAM. Note that the boot program remains stored in this area after a branch is made to the programming control program. Figure 19.
Section 19 ROM • The contents of the CPU’s internal general registers are undefined at this time, so these registers must be initialized immediately after branching to the programming control program. In particular, since the stack pointer (SP) is used implicitly in subroutine calls, etc., a stack area must be specified for use by the programming control program. • Initial settings must also be made for the other on-chip registers. • Boot mode can be entered by making the pin settings shown in table 19.
Section 19 ROM Figure 19.13 shows the procedure for executing the program/erase control program when transferred to on-chip RAM.
Section 19 ROM 19.7 Programming/Erasing Flash Memory In the on-board programming modes, flash memory programming and erasing is performed by software, using the CPU. There are four flash memory operating modes: program mode, erase mode, program-verify mode, and erase-verify mode. Transitions to these modes can be made by setting the PSU, ESU, P, E, PV, and EV bits in FLMCR1. The flash memory cannot be read while being programmed or erased.
Section 19 ROM elapse of (y) µs or more, the operating mode is switched to program mode by setting the P bit in FLMCR1. The time during which the P bit is set is the flash memory programming time. Set the programming time according to the table in the programming flowchart. 19.7.2 Program-Verify Mode In program-verify mode, the data written in program mode is read to check whether it has been correctly written in the flash memory.
Section 19 ROM Start of programming Write pulse application subroutine Sub-routine write pulse Start Enable WDT Set SWE bit in FLMCR1 Wait (x) μs *6 Store 128-byte program data in program data area and reprogram data area *4 Set PSU bit in FLMCR1 Wait (y) μs *6 Perform programming in the erased state. Do not perform additional programming on previously programmed addresses.
Section 19 ROM 19.7.3 Erase Mode Flash memory erasing should be performed block by block following the procedure shown in the erase/erase-verify flowchart (single-block erase) shown in figure 19.15. For the wait times (x, y, z, α, ß, γ, ε, η, θ) after bits are set or cleared in flash memory control register 1 (FLMCR1) and the maximum number of programming operations (N), see section 22.2.6, Flash Memory Characteristics.
Section 19 ROM Start *1 Set SWE bit in FLMCR1 Wait (x) μs *2 n=1 Set EBR1, EBR2 *4 Enable WDT Set ESU bit in FLMCR1 Wait (y) μs *2 Start of erase Set E bit in FLMCR1 Wait (z) ms *2 Clear E bit in FLMCR1 n←n+1 Halt erase Wait (α) μs *2 Clear ESU bit in FLMCR1 Wait (β) μs *2 Disable WDT Set EV bit in FLMCR1 *2 Wait (γ) μs Set block start address to verify address H'FF dummy write to verify address Increment address Wait (ε) μs *2 Read verify data *3 Verify data = all 1? NG OK NG L
Section 19 ROM 19.8 Flash Memory Protection There are three kinds of flash memory program/erase protection: hardware protection, software protection, and error protection. 19.8.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted. Settings in flash memory control registers 1 and 2 (FLMCR1, FLMCR2) and erase block registers 1 and 2 (EBR1, EBR2) are reset (see table 19.11). Table 19.
Section 19 ROM Table 19.12 Software Protection Functions Item Description Program Erase SWE bit protection • Clearing the SWE bit to 0 in FLMCR1 sets the program/erase-protected state for all blocks. Yes Yes • (Execute in on-chip RAM or external memory.) • Erase protection can be set for individual blocks by settings in erase block registers 1 and 2 (EBR1, EBR2). — Yes • Setting EBR1 and EBR2 to H'00 places all blocks in the erase-protected state.
Section 19 ROM Error protection is released only by a reset and in hardware standby mode. Figure 19.16 shows the flash memory state transition diagram.
Section 19 ROM 19.9 Flash Memory Emulation in RAM 19.9.1 Emulation in RAM Making a setting in the RAM emulation register (RAMER) enables part of RAM to be overlapped onto the flash memory area so that data to be written to flash memory can be emulated in RAM in real time. After the RAMER setting has been made, accesses can be made from the flash memory area or the RAM area overlapping flash memory. Emulation can be performed in user mode and user program mode. Figure 19.
Section 19 ROM 19.9.2 RAM Overlap An example in which flash memory block area EB1 is overlapped is shown below. This area can be accessed from both the RAM area and flash memory area H'00000 EB0 H'01000 EB1 H'02000 EB2 H'03000 EB3 H'04000 EB4 H'05000 EB5 H'06000 EB6 H'07000 EB7 H'08000 H'FFDC00 H'FFEBFF Flash memory EB8 to EB13 On-chip RAM H'FFFBFF H'5FFFF Figure 19.18 Example of RAM Overlap Operation Example in which Flash Memory Block Area EB1 is Overlapped 1.
Section 19 ROM a transition to program mode or erase mode. When actually programming a flash memory area, the RAMS bit should be cleared to 0. 2. A RAM area cannot be erased by execution of software in accordance with the erase algorithm while flash memory emulation in RAM is being used. 3. Block area EB0 includes the vector table. When performing RAM emulation, the vector table is needed by the overlap RAM. 19.
Section 19 ROM 19.11 Flash Memory PROM Mode 19.11.1 PROM Mode Setting Programs and data can be written and erased in PROM mode as well as in the on-board programming modes. In PROM mode, the on-chip ROM can be freely programmed using a PROM programmer that supports the Renesas microcomputer device type with 512-kbyte on-chip flash memory (FZTAT512V3A). Flash memory read mode, auto-program mode, auto-erase mode, and status read mode are supported with this device type.
Section 19 ROM H8S/2329B F-ZTAT Socket Adapter (40-Pin Conversion) HN27C4096HG (40 Pins) TFP-120 FP-128B Pin Name Pin No.
Section 19 ROM 19.11.3 PROM Mode Operation Table 19.14 shows how the different operating modes are set when using PROM mode, and table 19.15 lists the commands used in PROM mode. Details of each mode are given below. Memory Read Mode: Memory read mode supports byte reads. Auto-Program Mode: Auto-program mode supports programming of 128 bytes at a time. Status polling is used to confirm the end of auto-programming. Auto-Erase Mode: Auto-erase mode supports automatic erasing of the entire flash memory.
Section 19 ROM Table 19.15 PROM Mode Commands 1st Cycle 2nd Cycle Command Name Number of Cycles Mode Address Data Mode Address Data Memory read mode 1+n Write X H'00 Read RA Dout Auto-program mode 129 Write X H'40 Write PA Din Auto-erase mode 2 Write X H'20 Write X H'20 Status read mode 2 Write X H'71 Write X H'71 Legend: RA: Read address PA: Program address Notes: 1.
Section 19 ROM Table 19.16 AC Characteristics in Memory Read Mode Conditions: VCC = 3.3 V ±0.
Section 19 ROM Table 19.17 AC Characteristics when Entering Another Mode from Memory Read Mode Conditions: VCC = 3.3 V ±0.
Section 19 ROM Table 19.18 AC Characteristics in Memory Read Mode Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C Item Symbol Min Max Unit Access time tacc — 20 µs CE output delay time tce — 150 ns OE output delay time toe — 150 ns Output disable delay time tdf — 100 ns Data output hold time toh 5 — ns A18 to A0 Address stable CE VIL OE VIL WE VIH Address stable tacc tacc toh toh I/O7 to I/O0 Figure 19.
Section 19 ROM 19.11.5 Auto-Program Mode • In auto-program mode, 128 bytes are programmed simultaneously. For this purpose, 128 consecutive byte data transfers should be performed. • A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses. • The lower 7 bits of the transfer address must be held low. If an invalid address is input, memory programming will be started but a programming error will occur.
Section 19 ROM AC Characteristics Table 19.19 AC Characteristics in Auto-Program Mode Conditions: VCC = 3.3 V ±0.
Section 19 ROM 19.11.6 Auto-Erase Mode • Auto-erase mode supports only total memory erasing. • Do not perform a command write during auto-erasing. • Confirm normal end of auto-erasing by checking I/O6. Alternatively, status read mode can also be used for this purpose (the I/O7 status polling pin is used to identify the end of an auto-erase operation). • Status polling I/O6 and I/O7 pin information is retained until the next command write.
Section 19 ROM A18 to A0 tnxtc tceh tnxtc tces CE OE WE tf twep tds tspa tests tr terase tdh I/O7 Erase end identification signal I/O6 Erase normal end confirmation signal H'20 I/O5 to I/O0 H'00 H'20 Figure 19.26 Auto-Erase Mode Timing Waveforms 19.11.7 Status Read Mode • Status read mode is used to identify what type of abnormal end has occurred. Use this mode when an abnormal end occurs in auto-program mode or auto-erase mode.
Section 19 ROM A18 to A0 tceh tnxtc tces tces tceh tnxtc tnxtc CE tce OE WE tf twep tr tdh tds twep tf tds H'71 I/O7 to I/O0 toe tr tdf tdh H'71 Note: I/O3 and I/O2 are undefined. Figure 19.27 Status Read Mode Timing Waveforms Table 19.
Section 19 ROM 19.11.8 Status Polling • The I/O7 status polling flag indicates the operating status in auto-program or auto-erase mode. • The I/O6 status polling flag indicates a normal or abnormal end in auto-program or auto-erase mode. Table 19.23 Status Polling Output Truth Table Pin Names Internal Operation in Progress Abnormal End — Normal End I/O7 0 1 0 1 I/O6 0 0 1 1 I/O0 to I/O5 0 0 0 0 19.11.
Section 19 ROM 19.11.10 Notes on Memory Programming • When programming addresses which have previously been programmed, carry out autoerasing before auto-programming. • When performing programming using PROM mode on a chip that has been programmed/erased in an on-board programming mode, auto-erasing is recommended before carrying out auto-programming. Notes: 1. The flash memory is initially in the erased state when the device is shipped by Renesas Technology.
Section 19 ROM Do not set or clear the SWE bit during execution of a program in flash memory: Wait for at least 100 µs after clearing the SWE bit before executing a program or reading data in flash memory. When the SWE bit is set, data in flash memory can be rewritten, but when SWE = 1, flash memory can only be read in program-verify or erase-verify mode. Access flash memory only for verify operations (verification during programming/erasing).
Section 19 ROM 19.13 Overview of Flash Memory (H8S/2328B F-ZTAT) 19.13.1 Features The H8S/2328B F-ZTAT has 256 kbytes of on-chip flash memory. The features of the flash memory are summarized below. • Four flash memory operating modes ⎯ Program mode ⎯ Erase mode ⎯ Program-verify mode ⎯ Erase-verify mode • Programming/erase methods The flash memory is programmed 128 bytes at a time. Erasing is performed by block erase (in single-block units).
Section 19 ROM • PROM mode Flash memory can be programmed/erased in PROM mode, using a PROM programmer, as well as in on-board programming mode. 19.13.
Section 19 ROM 19.13.3 Flash Memory Operating Modes Mode Transitions: When the mode pins and the FWE pin are set in the reset state and a resetstart is executed, the chip enters one of the operating modes shown in figure 19.30. In user mode, flash memory can be read but not programmed or erased. Flash memory can be programmed and erased in boot mode, user program mode, and PROM mode.
Section 19 ROM 19.13.4 On-Board Programming Modes • Boot mode 1. Initial state The old program version or data remains written in the flash memory. The user should prepare the programming control program and new application program beforehand in the host. 2. Programming control program transfer When boot mode is entered, the boot program in the chip (originally incorporated in the chip) is started and the programming control program in the host is transferred to RAM via SCI communication.
Section 19 ROM • User program mode 1. Initial state (1) The FWE assessment program that confirms that the FWE pin has been driven high, and (2) the program that will transfer the programming/ erase control program to on-chip RAM should be written into the flash memory by the user beforehand. (3) The programming/erase control program should be prepared in the host or in the flash memory. 2.
Section 19 ROM 19.13.5 Flash Memory Emulation in RAM Reading Overlap RAM Data in User Mode and User Program Mode: Emulation should be performed in user mode or user program mode. When the emulation block set in RAMER is accessed while the emulation function is being executed, data written in the overlap RAM is read. SCI Flash memory RAM Emulation block Overlap RAM (emulation is performed on data written in RAM) Application program Execution state Figure 19.
Section 19 ROM Writing Overlap RAM Data in User Program Mode: When overlap RAM data is confirmed, the RAMS bit is cleared, RAM overlap is released, and writes should actually be performed to the flash memory. When the programming control program is transferred to RAM, ensure that the transfer destination and the overlap RAM do not overlap, as this will cause data in the overlap RAM to be rewritten.
Section 19 ROM 19.13.7 Block Configuration On-chip 256-kbyte flash memory is divided into three 64-kbyte blocks, one 32-kbyte block, and eight 4-kbyte blocks. Address H'00000 4 kbytes × 8 32 kbytes 256 kbytes 64 kbytes 64 kbytes 64 kbytes Address H'3FFFF Figure 19.35 Flash Memory Block Configuration Rev.6.00 Sep.
Section 19 ROM 19.13.8 Pin Configuration The flash memory is controlled by means of the pins shown in tables 19.26. Table 19.
Section 19 ROM 19.13.9 Register Configuration The registers used to control the on-chip flash memory when enabled are shown in table 19.27. In order to access the FLMCR1, FLMCR2, EBR1, and EBR2 registers, the FLSHE bit must be set to 1 in SYSCR2 (except RAMER). Table 19.
Section 19 ROM 19.14 Register Descriptions 19.14.1 Flash Memory Control Register 1 (FLMCR1) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 FWE SWE ESU PSU EV PV E P 1/0 0 0 0 0 0 0 0 R R/W R/W R/W R/W R/W R/W R/W FLMCR1 is an 8-bit register used for flash memory operating mode control. Program-verify mode or erase-verify mode is entered by setting SWE to 1 when FWE = 1, then setting the EV or PV bit.
Section 19 ROM Bit 6 SWE Description 0 Writes disabled 1 Writes enabled (Initial value) [Setting condition] When FWE = 1 Bit 5—Erase Setup Bit (ESU): Prepares for a transition to erase mode. Do not set the SWE, PSU, EV, PV, E, or P bit at the same time. Bit 5 ESU Description 0 Erase setup cleared 1 Erase setup (Initial value) [Setting condition] When FWE = 1 and SWE = 1 Bit 4—Program Setup Bit (PSU): Prepares for a transition to program mode.
Section 19 ROM Bit 2—Program-Verify (PV): Selects program-verify mode transition or clearing. Do not set the SWE, ESU, PSU, EV, E, or P bit at the same time. Bit 2 PV Description 0 Program-verify mode cleared 1 Transition to program-verify mode (Initial value) [Setting condition] When FWE = 1 and SWE = 1 Bit 1—Erase (E): Selects erase mode transition or clearing. Do not set the SWE, ESU, PSU, EV, PV, or P bit at the same time.
Section 19 ROM 19.14.2 Flash Memory Control Register 2 (FLMCR2) Bit : 7 6 5 4 3 2 1 0 FLER — — — — — — — Initial value : 0 0 0 0 0 0 0 0 R/W R — — — — — — — : FLMCR2 is an 8-bit register that controls the flash memory operating modes. FLMCR2 is initialized to H'00 by a reset, and in hardware standby mode and software standby mode. When on-chip flash memory is disabled, a read will return H'00 and writes are invalid.
Section 19 ROM 19.14.3 Erase Block Register 1 (EBR1) Bit : EBR1 Initial value : R/W : 7 6 5 4 3 2 1 0 EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W EBR1 is an 8-bit register that specifies the flash memory erase area block by block.
Section 19 ROM Table 19.
Section 19 ROM Bit 3—Flash Memory Control Register Enable (FLSHE): Controls CPU access to the flash memory control registers (FLMCR1, FLMCR2, EBR1, and EBR2). Writing 1 to the FLSHE bit enables the flash memory control registers to be read and written to. Clearing FLSHE to 0 designates these registers as unselected (the register contents are retained).
Section 19 ROM Bit 3—RAM Select (RAMS): Specifies selection or non-selection of flash memory emulation in RAM. When RAMS = 1, all flash memory blocks are program/erase-protected.
Section 19 ROM 19.15 On-Board Programming Modes When pins are set to on-board programming mode, program/erase/verify operations can be performed on the on-chip flash memory. There are two on-board programming modes: boot mode and user program mode. The pin settings for transition to each of these modes are shown in table 19.30. For a diagram of the transitions to the various flash memory modes, see figure 19.31. Table 19.
Section 19 ROM Chip Flash memory Host Write data reception Verify data transmission RxD1 SCI1 TxD1 Figure 19.36 System Configuration in Boot Mode Rev.6.00 Sep.
Section 19 ROM Start Set pins to boot mode and execute reset-start Host transfers data (H'00) continuously at prescribed bit rate Chip measures low period of H'00 data transmitted by host Chip calculates bit rate and sets value in bit rate register After bit rate adjustment, chip transmits one H'00 data byte to host to indicate end of adjustment Host confirms normal reception of bit rate adjustment end indication (H'00), and transmits one H'55 data byte After receiving H'55, chip transmits one H'AA data by
Section 19 ROM Automatic SCI Bit Rate Adjustment: When boot mode is initiated, the H8S/2328B F-ZTAT chip measures the low period of the asynchronous SCI communication data (H'00) transmitted continuously from the host. The SCI transmit/receive format should be set as follows: 8-bit data, 1 stop bit, no parity. The chip calculates the bit rate of the transmission from the host from the measured low period, and transmits one H'00 byte to the host to indicate the end of bit rate adjustment.
Section 19 ROM On-Chip RAM Area Divisions in Boot Mode: In boot mode, the 2-kbyte area from H'FFDC00 to H'FFE3FF is reserved for use by the boot program, as shown in figure 19.39. The area to which the programming control program is transferred is H'FFE400 to H'FFFBFF. The boot program area can be used when the programming control program transferred into RAM enters the execution state. A stack area should be set up as required.
Section 19 ROM • Before branching to the programming control program (RAM area H'FFE400 to H'FFFBFF), the chip terminates transmit and receive operations by the on-chip SCI (channel 1) (by clearing the RE and TE bits in SCR to 0), but the adjusted bit rate value remains set in BRR. The transmit data output pin, TxD1, goes to the high-level output state (P31DDR = 1, P31DR = 1).
Section 19 ROM 19.15.2 User Program Mode When set to user program mode, the chip can program and erase its flash memory by executing a user program/erase control program. Therefore, on-board reprogramming of the on-chip flash memory can be carried out by providing on-board means of FWE control and supply of programming data, and storing a program/erase control program in part of the program area as necessary.
Section 19 ROM Write the FWE assessment program and transfer program (and the program/erase control program if necessary) beforehand MD2, MD1, MD0 = 110, 111 Reset-start Transfer program/erase control program to RAM Branch to program/erase control program in RAM area FWE = high* Execute program/erase control program (flash memory rewriting) Clear FWE* Branch to flash memory application program Notes: Do not apply a constant high level to the FWE pin.
Section 19 ROM 19.16 Programming/Erasing Flash Memory In the on-board programming modes, flash memory programming and erasing is performed by software, using the CPU. There are four flash memory operating modes: program mode, erase mode, program-verify mode, and erase-verify mode. Transition to these modes can be made for the on-chip ROM area by setting the PSU, ESU, P, E, PV, and EV bits in FLMCR1. The flash memory cannot be read while being programmed or erased.
Section 19 ROM Next, the watchdog timer is set to prevent overprogramming in the event of program runaway, etc. Set a value greater than (y + z2 + α + β) µs as the WDT overflow period. After this, preparation for program mode (program setup) is carried out by setting the PSU bit in FLMCR1, and after the elapse of (y) µs or more, the operating mode is switched to program mode by setting the P bit in FLMCR1. The time during which the P bit is set is the flash memory programming time.
Section 19 ROM Start of programming Write pulse application subroutine Sub-routine write pulse Start Enable WDT Set SWE bit in FLMCR1 Wait (x) μs *6 Store 128-byte program data in program data area and reprogram data area *4 Set PSU bit in FLMCR1 Wait (y) μs *6 Perform programming in the erased state. Do not perform additional programming on previously programmed addresses.
Section 19 ROM 19.16.3 Erase Mode Flash memory erasing should be performed block by block following the procedure shown in the erase/erase-verify flowchart (single-block erase) shown in figure 19.43. For the wait times (x, y, z, α, ß, γ, ε, η, θ) after bits are set or cleared in flash memory control register 1 (FLMCR1) and the maximum number of programming operations (N), see section 22.2.6, Flash Memory Characteristics.
Section 19 ROM Start *1 Set SWE bit in FLMCR1 Wait (x) μs *2 n=1 Set EBR1, EBR2 *4 Enable WDT Set ESU bit in FLMCR1 Wait (y) μs *2 Start of erase Set E bit in FLMCR1 Wait (z) ms *2 Clear E bit in FLMCR1 n←n+1 Halt erase Wait (α) μs *2 Clear ESU bit in FLMCR1 Wait (β) μs *2 Disable WDT Set EV bit in FLMCR1 *2 Wait (γ) μs Set block start address to verify address H'FF dummy write to verify address Wait (ε) μs *2 Read verify data Increment address Verify data = all 1? *3 NG OK NG L
Section 19 ROM 19.17 Flash Memory Protection There are three kinds of flash memory program/erase protection: hardware protection, software protection, and error protection. 19.17.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted. Settings in flash memory control registers 1 and 2 (FLMCR1, FLMCR2) and erase block registers 1 and 2 (EBR1, EBR2) are reset (see table 19.10). Table 19.
Section 19 ROM Table 19.33 Software Protection Functions Item Description Program Erase SWE bit protection • Clearing the SWE bit to 0 in FLMCR1 sets the program/erase-protected state for all blocks Yes Yes • (Execute in on-chip RAM or external memory.) • Erase protection can be set for individual blocks by settings in erase block registers 1 and 2 (EBR1, EBR2). — Yes • Setting EBR1 and EBR2 to H'00 places all blocks in the erase-protected state.
Section 19 ROM Error protection is released only by a reset and in hardware standby mode. Figure 19.43 shows the flash memory state transition diagram.
Section 19 ROM 19.18 Flash Memory Emulation in RAM 19.18.1 Emulation in RAM Making a setting in the RAM emulation register (RAMER) enables part of RAM to be overlapped onto the flash memory area so that data to be written to flash memory can be emulated in RAM in real time. After the RAMER setting has been made, accesses can be made from the flash memory area or the RAM area overlapping flash memory. Emulation can be performed in user mode and user program mode. Figure 19.
Section 19 ROM 19.18.2 RAM Overlap An example in which flash memory block area EB1 is overlapped is shown below. This area can be accessed from both the RAM area and flash memory area H'00000 EB0 H'01000 EB1 H'02000 EB2 H'03000 EB3 H'04000 EB4 H'05000 EB5 H'06000 EB6 H'07000 EB7 H'08000 H'FFDC00 H'FFEBFF Flash memory EB8 to EB11 On-chip RAM H'FFFBFF H'3FFFF Figure 19.45 Example of RAM Overlap Operation Example in which Flash Memory Block Area EB1 is Overlapped 1.
Section 19 ROM 2. A RAM area cannot be erased by execution of software in accordance with the erase algorithm while flash memory emulation in RAM is being used. 3. Block area EB0 includes the vector table. When performing RAM emulation, the vector table is needed by the overlap RAM. 19.
Section 19 ROM 19.20 Flash Memory PROM Mode 19.20.1 PROM Mode Setting Programs and data can be written and erased in PROM mode as well as in the on-board programming modes. In PROM mode, the on-chip ROM can be freely programmed using a PROM programmer that supports the Renesas microcomputer device type with 256-kbyte on-chip flash memory (FZTAT256V3A). Flash memory read mode, auto-program mode, auto-erase mode, and status read mode are supported with this device type.
Section 19 ROM 19.20.2 Socket Adapters and Memory Map In PROM mode, a socket adapter is connected to the chip as shown in figure 19.47. Figure 19.46 shows the on-chip ROM memory map and figure 19.47 shows the socket adapter pin assignments. MCU mode address PROM mode address H'00000 H'00000000 On-chip ROM space 256 kbytes H'0003FFFF H'3FFFF Figure 19.46 Memory Map in PROM Mode Rev.6.00 Sep.
Section 19 ROM H8S/2328B F-ZTAT Socket Adapter (40-Pin Conversion) HN27C4096HG (40 Pins) TFP-120 FP-128B Pin Name Pin No.
Section 19 ROM 19.20.3 PROM Mode Operation Table 19.35 shows how the different operating modes are set when using PROM mode, and table 19.36 lists the commands used in PROM mode. Details of each mode are given below. Memory Read Mode: Memory read mode supports byte reads. Auto-Program Mode: Auto-program mode supports programming of 128 bytes at a time. Status polling is used to confirm the end of auto-programming. Auto-Erase Mode: Auto-erase mode supports automatic erasing of the entire flash memory.
Section 19 ROM Table 19.36 PROM Mode Commands 1st Cycle 2nd Cycle Command Name Number of Cycles Mode Address Data Mode Address Data Memory read mode 1+n Write X H'00 Read RA Dout Auto-program mode 129 Write X H'40 Write PA Din Auto-erase mode 2 Write X H'20 Write X H'20 Status read mode 2 Write X H'71 Write X H'71 Legend: RA: Read address PA: Program address Notes: 1.
Section 19 ROM Table 19.37 AC Characteristics in Memory Read Mode Conditions: VCC = 3.3 V ±0.
Section 19 ROM Table 19.38 AC Characteristics when Entering Another Mode from Memory Read Mode Conditions: VCC = 3.3 V ±0.
Section 19 ROM Table 19.39 AC Characteristics in Memory Read Mode Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C Item Symbol Min Max Unit Access time tacc — 20 µs CE output delay time tce — 150 ns OE output delay time toe — 150 ns Output disable delay time tdf — 100 ns Data output hold time toh 5 — ns A18 to A0 Address stable CE VIL OE VIL WE VIH Address stable tacc tacc toh toh I/O7 to I/O0 Figure 19.
Section 19 ROM 19.20.5 Auto-Program Mode • In auto-program mode, 128 bytes are programmed simultaneously. For this purpose, 128 consecutive byte data transfers should be performed. • A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses. • The lower 7 bits of the transfer address must be held low. If an invalid address is input, memory programming will be started but a programming error will occur.
Section 19 ROM AC Characteristics Table 19.40 AC Characteristics in Auto-Program Mode Conditions: VCC = 3.3 V ±0.
Section 19 ROM FWE tpnh Address stable A18 to A0 tpns tces tceh tnxtc tnxtc CE OE tf twep tas tr WE tah twsts tspa Data transfer 1 byte to 128 bytes tds tdh twrite I/O7 Programming operation end identification signal I/O6 Programming normal end identification signal H'40 I/O5 to I/O0 H'00 Figure 19.52 Auto-Program Mode Timing Waveforms 19.20.6 Auto-Erase Mode • Auto-erase mode supports only total memory erasing. • Do not perform a command write during auto-erasing.
Section 19 ROM AC Characteristics Table 19.41 AC Characteristics in Auto-Erase Mode Conditions: VCC = 3.3 V ±0.
Section 19 ROM 19.20.7 Status Read Mode • Status read mode is used to identify what type of abnormal end has occurred. Use this mode when an abnormal end occurs in auto-program mode or auto-erase mode. • The return code is retained until a command write for other than status read mode is performed. Table 19.42 AC Characteristics in Status Read Mode Conditions: VCC = 3.3 V ±0.
Section 19 ROM Table 19.
Section 19 ROM 19.20.9 PROM Mode Transition Time Commands cannot be accepted during the oscillation stabilization period or the PROM mode setup period. After the PROM mode setup time, a transition is made to memory read mode. Table 19.
Section 19 ROM 19.20.10 Notes on Memory Programming • When programming addresses which have previously been programmed, carry out autoerasing before auto-programming. • When performing programming using PROM mode on a chip that has been programmed/erased in an on-board programming mode, auto-erasing is recommended before carrying out auto-programming. Notes: 1. The flash memory is initially in the erased state when the device is shipped by Renesas Technology.
Section 19 ROM The following points must be observed concerning FWE application and disconnection to prevent unintentional programming or erasing of flash memory: • Apply FWE when the VCC voltage has stabilized within its rated voltage range. • Apply FWE when oscillation has stabilized (after the elapse of the oscillation stabilization time). • In boot mode, apply and disconnect FWE during a reset. • In user program mode, FWE can be switched between high and low level regardless of the reset state.
Section 19 ROM Do not use interrupts while flash memory is being programmed or erased: All interrupt requests, including NMI, should be disabled during FWE application to give priority to program/erase operations. Do not perform additional programming. Erase the memory before reprogramming: In onboard programming, perform only one programming operation on a 128-byte programming unit block. In PROM mode, too, perform only one programming operation on a 128-byte programming unit block.
Section 19 ROM Wait time: x Programming/ erasing possible Wait time: 100 μs φ Min 0 μs tOSC1 VCC tMDS*3 FWE Min 0 μs MD2 to MD0*1 tMDS*3 RES SWE set SWE cleared SWE bit Period during which flash memory access is prohibited (x: Wait time after setting SWE bit)*2 Period during which flash memory can be programmed (Execution of program in flash memory prohibited, and data reads other than verify operations prohibited) Notes: 1.
Section 19 ROM Wait time: x Programming/ erasing possible Wait time: 100 μs φ Min 0 μs tOSC1 VCC FWE MD2 to MD0*1 tMDS*3 RES SWE set SWE cleared SWE bit Period during which flash memory access is prohibited (x: Wait time after setting SWE bit)*2 Period during which flash memory can be programmed (Execution of program in flash memory prohibited, and data reads other than verify operations prohibited) Notes: 1.
Wait time: 100 μs Wait time: x Programming/erasing possible Wait time: 100 μs Wait time: x Programming/erasing possible Wait time: 100 μs Wait time: x Programming/erasing possible Wait time: 100 μs Wait time: x Programming/erasing possible Section 19 ROM φ tOSC1 VCC Min 0 μs FWE tMDS tMDS*2 MD2 to MD0 tMDS tRESW RES SWE bit SWE set Mode change*1 SWE cleared Boot mode Mode User change*1 mode User program mode User mode User program mode Period during which flash memory access is prohib
Section 19 ROM 19.22 Overview of Flash Memory (H8S/2326 F-ZTAT) 19.22.1 Features The H8S/2326 F-ZTAT has 512 kbytes of on-chip flash memory. The features of the flash memory are summarized below. • Four flash memory operating modes ⎯ Program mode ⎯ Erase mode ⎯ Program-verify mode ⎯ Erase-verify mode • Programming/erase methods The flash memory is programmed 128 bytes at a time. Erasing is performed by block erase (in single-block units).
Section 19 ROM • PROM mode Flash memory can be programmed/erased in PROM mode, using a PROM programmer, as well as in on-board programming mode. 19.22.
Section 19 ROM 19.22.3 Flash Memory Operating Modes Mode Transitions: When the mode pins and the FWE pin are set in the reset state and a resetstart is executed, the chip enters one of the operating modes shown in figure 19.60. In user mode, flash memory can be read but not programmed or erased. Flash memory can be programmed and erased in boot mode, user program mode, and PROM mode.
Section 19 ROM 19.22.4 On-Board Programming Modes • Boot mode 1. Initial state The old program version or data remains written in the flash memory. The user should prepare the programming control program and new application program beforehand in the host. 2. Programming control program transfer When boot mode is entered, the boot program in the chip (originally incorporated in the chip) is started and the programming control program in the host is transferred to RAM via SCI communication.
Section 19 ROM • User program mode 1. Initial state (1) The FWE assessment program that confirms that the FWE pin has been driven high, and (2) the program that will transfer the programming/ erase control program to on-chip RAM should be written into the flash memory by the user beforehand. (3) The programming/erase control program should be prepared in the host or in the flash memory. 2.
Section 19 ROM 19.22.5 Flash Memory Emulation in RAM Reading Overlap RAM Data in User Mode and User Program Mode: Emulation should be performed in user mode or user program mode. When the emulation block set in RAMER is accessed while the emulation function is being executed, data written in the overlap RAM is read. SCI Flash memory RAM Emulation block Overlap RAM (emulation is performed on data written in RAM) Application program Execution state Figure 19.
Section 19 ROM Writing Overlap RAM Data in User Program Mode: When overlap RAM data is confirmed, the RAMS bit is cleared, RAM overlap is released, and writes should actually be performed to the flash memory. When the programming control program is transferred to RAM, ensure that the transfer destination and the overlap RAM do not overlap, as this will cause data in the overlap RAM to be rewritten.
Section 19 ROM 19.22.7 Block Configuration On-chip 512-kbyte flash memory is divided into seven 64-kbyte blocks, one 32-kbyte block, and eight 4-kbyte blocks. Address H'000000 4 kbytes × 8 32 kbytes 64 kbytes 512 kbytes 64 kbytes 64 kbytes 64 kbytes 64 kbytes 64 kbytes 64 kbytes Address H'07FFFF Figure 19.65 Flash Memory Block Configuration Rev.6.00 Sep.
Section 19 ROM 19.22.8 Pin Configuration The flash memory is controlled by means of the pins shown in tables 19.47. Table 19.
Section 19 ROM 19.22.9 Register Configuration The registers used to control the on-chip flash memory when enabled are shown in table 19.48. In order to access the FLMCR1, FLMCR2, EBR1, and EBR2 registers, the FLSHE bit must be set to 1 in SYSCR2 (except RAMER). Table 19.
Section 19 ROM 19.23 Register Descriptions 19.23.1 Flash Memory Control Register 1 (FLMCR1) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 FWE SWE1 ESU1 PSU1 EV1 PV1 E1 P1 1/0 0 0 0 0 0 0 0 R R/W R/W R/W R/W R/W R/W R/W FLMCR1 is an 8-bit register used for flash memory operating mode control. Program-verify mode or erase-verify mode for addresses H'000000 to H'03FFFF is entered by setting SWE1 to 1 when FWE = 1, then setting the EV1 or PV1 bit.
Section 19 ROM Bit 6 SWE1 Description 0 Writes disabled 1 Writes enabled (Initial value) [Setting condition] When FWE = 1 Bit 5—Erase Setup Bit 1 (ESU1): Prepares for a transition to erase mode for addresses H'000000 to H'03FFFF. Do not set the SWE1, PSU1, EV1, PV1, E1, or P1 bit at the same time.
Section 19 ROM Bit 2—Program-Verify 1 (PV1): Selects program-verify mode transition or clearing for addresses H'000000 to H'03FFFF. Do not set the SWE1, ESU1, PSU1, EV1, E1, or P1 bit at the same time. Bit 2 PV1 Description 0 Program-verify mode cleared 1 Transition to program-verify mode (Initial value) [Setting condition] When FWE = 1, SWE1 = 1 Bit 1—Erase 1 (E1): Selects erase mode transition or clearing for addresses H'000000 to H'03FFFF.
Section 19 ROM 19.23.2 Flash Memory Control Register 2 (FLMCR2) Bit : 7 6 5 4 3 2 1 0 FLER SWE2 ESU2 PSU2 EV2 PV2 E2 P2 Initial value : 0 0 0 0 0 0 0 0 R/W R R/W R/W R/W R/W R/W R/W R/W : FLMCR2 is an 8-bit register used for flash memory operating mode control. Program-verify mode or erase-verify mode for addresses H'040000 to H'07FFFF is entered by setting SWE2 to 1 when FWE = 1, then setting the EV2 or PV2 bit.
Section 19 ROM Bit 6—Software Write Enable Bit 2 (SWE2): Enables or disables flash memory programming and erasing for addresses H'040000 to H'07FFFF. This bit should be set when setting bits 5 to 0 in FLMCR2, and EBR2 bits 7 to 4. When SWE2 = 1, the flash memory can only be read in program-verify or erase-verify mode.
Section 19 ROM Bit 3—Erase-Verify 2 (EV2): Selects erase-verify mode transition or clearing for addresses H'040000 to H'07FFFF. Do not set the SWE2, ESU2, PSU2, PV2, E2, or P2 bit at the same time. Bit 3 EV2 Description 0 Erase-verify mode cleared 1 Transition to erase-verify mode (Initial value) [Setting condition] When FWE = 1, SWE2 = 1 Bit 2—Program-Verify 2 (PV2): Selects program-verify mode transition or clearing for addresses H'040000 to H'07FFFF.
Section 19 ROM Bit 0—Program 2 (P2): Selects program mode transition or clearing for H'040000 to H'07FFFF. Do not set the SWE2, PSU2, ESU2, EV2, PV2, or E2 bit at the same time. Bit 0 P2 Description 0 Program mode cleared 1 Transition to program mode (Initial value) [Setting condition] When FWE = 1, SWE2 = 1, and PSU2 = 1 19.23.
Section 19 ROM 19.23.4 Bit Erase Block Registers 2 (EBR2) : EBR2 Initial value : R/W : 7 6 5 4 3 2 1 0 EB15 EB14 EB13 EB12 EB11 EB10 EB9 EB8 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W EBR2 is an 8-bit register that specifies the flash memory erase area block by block.
Section 19 ROM Table 19.
Section 19 ROM Bit 3—Flash Memory Control Register Enable (FLSHE): Controls CPU access to the flash memory control registers (FLMCR1, FLMCR2, EBR1, and EBR2). Writing 1 to the FLSHE bit enables the flash memory control registers to be read and written to. Clearing FLSHE to 0 designates these registers as unselected (the register contents are retained).
Section 19 ROM Bit 3—RAM Select (RAMS): Specifies selection or non-selection of flash memory emulation in RAM. When RAMS = 1, all flash memory blocks are program/erase-protected.
Section 19 ROM 19.24 On-Board Programming Modes When pins are set to on-board programming mode, program/erase/verify operations can be performed on the on-chip flash memory. There are two on-board programming modes: boot mode and user program mode. The pin settings for transition to each of these modes are shown in table 19.51. For a diagram of the transitions to the various flash memory modes, see figure 19.59. Table 19.
Section 19 ROM Chip Flash memory Host Write data reception Verify data transmission RxD1 SCI1 On-chip RAM TxD1 Figure 19.66 System Configuration in Boot Mode Rev.6.00 Sep.
Section 19 ROM Start Set pins to boot mode and execute reset-start Host transfers data (H'00) continuously at prescribed bit rate Chip measures low period of H'00 data transmitted by host Chip calculates bit rate and sets value in bit rate register After bit rate adjustment, chip transmits one H'00 data byte to host to indicate end of adjustment Host confirms normal reception of bit rate adjustment end indication (H'00), and transmits one H'55 data byte After receiving H'55, chip transmits one H'AA data by
Section 19 ROM Automatic SCI Bit Rate Adjustment: When boot mode is initiated, the H8S/2326 F-ZTAT chip measures the low period of the asynchronous SCI communication data (H'00) transmitted continuously from the host. The SCI transmit/receive format should be set as follows: 8-bit data, 1 stop bit, no parity. The chip calculates the bit rate of the transmission from the host from the measured low period, and transmits one H'00 byte to the host to indicate the end of bit rate adjustment.
Section 19 ROM On-Chip RAM Area Divisions in Boot Mode: In boot mode, the 2-kbyte area from H'FFDC00 to H'FFE3FF is reserved for use by the boot program, as shown in figure 19.69. The area to which the programming control program is transferred is H'FFE400 to H'FFFBFF. The boot program area can be used when the programming control program transferred into RAM enters the execution state. A stack area should be set up as required.
Section 19 ROM • The RxD1 and TxD1 pins should be pulled up on the board. • Before branching to the programming control program (RAM area H'FFE400 to H'FFFBFF), the chip terminates transmit and receive operations by the on-chip SCI (channel 1) (by clearing the RE and TE bits in SCR to 0), but the adjusted bit rate value remains set in BRR. The transmit data output pin, TxD1, goes to the high-level output state (P31DDR = 1, P31DR = 1).
Section 19 ROM 19.24.2 User Program Mode When set to user program mode, the chip can program and erase its flash memory by executing a user program/erase control program. Therefore, on-board programming of the on-chip flash memory can be carried out by providing ahead of time an on-board FWE control means to supply programming data, and storing a program/erase control program in part of the program area if necessary.
Section 19 ROM Write FWE assessment program and transfer program (and programming/erase control program if necessary) beforehand MD2, MD1, MD0 = 101 or 111 Reset start Transfer programming/erase control program to RAM Branch to programming/erase control program in RAM area FWE = high* Execute programming/erase control program (flash memory rewriting) Clear FWE* Branch to application program in flash memory Notes: Do not apply a constant high level to the FWE pin.
Section 19 ROM 19.25 Programming/Erasing Flash Memory In the on-board programming modes, flash memory programming and erasing is performed by software, using the CPU. There are four flash memory operating modes: program mode, erase mode, program-verify mode, and erase-verify mode.
Section 19 ROM Following the elapse of (x) µs or more after the SWEn bit is set to 1 in flash memory control register n (FLMCRn), 128-byte program data is stored in the program data area and reprogram data area, and the 128-byte data in the reprogram data area is written consecutively to the write addresses. The lower 8 bits of the first address written to must be H'00 or H'80. 128 consecutive byte data transfers are performed. The program address and program data are latched in the flash memory.
Section 19 ROM Start of programming Write pulse application subroutine Sub-routine write pulse Start Enable WDT Set SWE1 (2) bit in FLMCR1 (2) Wait (x) μs *6 Store 128-byte program data in program data area and reprogram data area *4 Set PSU1 (2) bit in FLMCR1 (2) Wait (y) μs *6 Perform programming in the erased state. Do not perform additional programming on previously programmed addresses.
Section 19 ROM 19.25.3 Erase Mode (n = 1 for addresses H'000000 to H'03FFFF and n = 2 for addresses H'040000 to H'07FFFF) Flash memory erasing should be performed block by block following the procedure shown in the erase/erase-verify flowchart (single-block erase) shown in figure 19.71. For the wait times (x, y, z, α, ß, γ, ε, η, θ) after bits are set or cleared in flash memory control register n (FLMCRn) and the maximum number of programming operations (N), see section 22.2.
Section 19 ROM 19.25.4 Erase-Verify Mode (n = 1 for addresses H'000000 to H'03FFFF and n = 2 for addresses H'040000 to H'07FFFF) In erase-verify mode, data is read after memory has been erased to check whether it has been correctly erased.
Section 19 ROM Start *1 Set SWE1 (2) bit in FLMCR1 (2) Wait (x) μs *2 n=1 Set EBR1, EBR2 *4 Enable WDT Set ESU1 (2) bit in FLMCR1 (2) Wait (y) μs *2 Start of erase Set E1 (2) bit in FLMCR1 (2) Wait (z) ms *2 Clear E1 (2) bit in FLMCR1(2) n←n+1 Halt erase Wait (α) μs *2 Clear ESU1 (2) bit in FLMCR1 (2) Wait (β) μs *2 Disable WDT Set EV1 (2) bit in FLMCR1 (2) *2 Wait (γ) μs Set block start address to verify address H'FF dummy write to verify address Wait (ε) μs *2 Read verify data Incr
Section 19 ROM 19.26 Flash Memory Protection There are three kinds of flash memory program/erase protection: hardware protection, software protection, and error protection. 19.26.1 Hardware Protection Hardware protection refers to a state in which programming/erasing of flash memory is forcibly disabled or aborted. Settings in flash memory control registers 1 and 2 (FLMCR1, FLMCR2) and erase block registers 1 and 2 (EBR1, EBR2) are reset (see table 19.53). Table 19.
Section 19 ROM Table 19.
Section 19 ROM FLER bit setting conditions are as follows: • When flash memory is read during programming/erasing (including a vector read or instruction fetch) • Immediately after exception handling (excluding a reset) during programming/erasing • When a SLEEP instruction (including software standby) is executed during programming/erasing • When a bus master other than the CPU (the DMAC or DTC) has control of the bus during programming/erasing Error protection is released only by a reset and in hardware s
Section 19 ROM 19.27 Flash Memory Emulation in RAM 19.27.1 Emulation in RAM Making a setting in the RAM emulation register (RAMER) enables part of RAM to be overlapped onto the flash memory area so that data to be written to flash memory can be emulated in RAM in real time. After the RAMER setting has been made, accesses can be made from the flash memory area or the RAM area overlapping flash memory. Emulation can be performed in user mode and user program mode. Figure 19.
Section 19 ROM 19.27.2 RAM Overlap An example in which flash memory block area EB1 is overlapped is shown below. This area can be accessed from both the RAM area and flash memory area H'000000 EB0 H'001000 EB1 H'002000 EB2 H'030000 EB3 H'004000 EB4 H'005000 EB5 H'006000 EB6 H'007000 EB7 H'008000 H'FFDC00 H'FFEBFF Flash memory EB8 to EB15 On-chip RAM H'FFFBFF H'07FFFF Figure 19.75 Example of RAM Overlap Operation Example in which Flash Memory Block Area EB1 is Overlapped 1.
Section 19 ROM the P2 or E2 bit in FLMCR2 will not cause a transition to program mode or erase mode. When actually programming a flash memory area, the RAMS bit should be cleared to 0. 2. A RAM area cannot be erased by execution of software in accordance with the erase algorithm while flash memory emulation in RAM is being used. 3. Block area EB0 includes the vector table. When performing RAM emulation, the vector table is needed by the overlap RAM. 19.
Section 19 ROM 19.29 Flash Memory PROM Mode 19.29.1 PROM Mode Setting Programs and data can be written and erased in PROM mode as well as in the on-board programming modes. In PROM mode, the on-chip ROM can be freely programmed using a PROM programmer that supports the Renesas microcomputer device type with 512-kbyte on-chip flash memory (FZTAT512V3A). Flash memory read mode, auto-program mode, auto-erase mode, and status read mode are supported with this device type.
Section 19 ROM 19.29.2 Socket Adapters and Memory Map In PROM mode, a socket adapter is connected to the chip as shown in figure 19.77. Figure 19.76 shows the on-chip ROM memory map and figure 19.77 shows the socket adapter pin assignments. MCU mode address PROM mode address H'00000 H'00000000 On-chip ROM space 512 kbytes H'0007FFFF H'7FFFF Figure 19.76 Memory Map in PROM Mode Rev.6.00 Sep.
Section 19 ROM H8S/2326 F-ZTAT Socket Adapter (40-Pin Conversion) HN27C4096HG (40 Pins) TFP-120 FP-128B Pin Name Pin No.
Section 19 ROM 19.29.3 PROM Mode Operation Table 19.56 shows how the different operating modes are set when using PROM mode, and table 19.57 lists the commands used in PROM mode. Details of each mode are given below. Memory Read Mode: Memory read mode supports byte reads. Auto-Program Mode: Auto-program mode supports programming of 128 bytes at a time. Status polling is used to confirm the end of auto-programming. Auto-Erase Mode: Auto-erase mode supports automatic erasing of the entire flash memory.
Section 19 ROM Table 19.57 PROM Mode Commands 1st Cycle 2nd Cycle Command Name Number of Cycles Mode Address Data Mode Address Data Memory read mode 1+n Write X H'00 Read RA Dout Auto-program mode 129 Write X H'40 Write PA Din Auto-erase mode 2 Write X H'20 Write X H'20 Status read mode 2 Write X H'71 Write X H'71 Legend: RA: Read address PA: Program address Notes: 1.
Section 19 ROM Table 19.58 AC Characteristics in Memory Read Mode Conditions: VCC = 3.3 V ±0.
Section 19 ROM Table 19.59 AC Characteristics when Entering Another Mode from Memory Read Mode Conditions: VCC = 3.3 V ±0.
Section 19 ROM Table 19.60 AC Characteristics in Memory Read Mode Conditions: VCC = 3.3 V ±0.3 V, VSS = 0 V, Ta = 25°C ±5°C Item Symbol Min Max Unit Access time tacc — 20 µs CE output delay time tce — 150 ns OE output delay time toe — 150 ns Output disable delay time tdf — 100 ns Data output hold time toh 5 — ns A18 to A0 Address stable CE VIL OE VIL WE VIH Address stable tacc tacc toh toh I/O7 to I/O0 Figure 19.
Section 19 ROM 19.29.5 Auto-Program Mode • In auto-program mode, 128 bytes are programmed simultaneously. For this purpose, 128 consecutive byte data transfers should be performed. • A 128-byte data transfer must be performed even if writing fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses. • The lower 7 bits of the transfer address must be held low. If an invalid address is input, memory programming will be started but a programming error will occur.
Section 19 ROM AC Characteristics Table 19.61 AC Characteristics in Auto-Program Mode Conditions: VCC = 3.3 V ±0.
Section 19 ROM FWE tpnh Address stable A18 to A0 tpns tces tceh tnxtc tnxtc CE OE tf twep tas tr WE tah twsts tspa Data transfer 1 byte to 128 bytes tds tdh twrite I/O7 Programming operation end identification signal I/O6 Programming normal end identification signal H'40 I/O5 to I/O0 H'00 Figure 19.82 Auto-Program Mode Timing Waveforms 19.29.6 Auto-Erase Mode • Auto-erase mode supports only total memory erasing. • Do not perform a command write during auto-erasing.
Section 19 ROM AC Characteristics Table 19.62 AC Characteristics in Auto-Erase Mode Conditions: VCC = 3.3 V ±0.
Section 19 ROM tenh FWE A18 to A0 tens tces tnxtc tceh tnxtc CE OE WE tf twep tests tr tds tspa terase tdh I/O7 Erase end identification signal I/O6 Erase normal end confirmation signal H'20 I/O5 to I/O0 H'20 H'00 Figure 19.83 Auto-Erase Mode Timing Waveforms 19.29.7 Status Read Mode • Status read mode is used to identify what type of abnormal end has occurred. Use this mode when an abnormal end occurs in auto-program mode or auto-erase mode.
Section 19 ROM Table 19.63 AC Characteristics in Status Read Mode Conditions: VCC = 3.3 V ±0.
Section 19 ROM Table 19.
Section 19 ROM Table 19.66 Command Wait State Transition Time Specifications Item Symbol Min Max Unit Standby release (oscillation stabilization time) tosc1 30 — ms PROM mode setup time tbmv 10 — ms VCC hold time tdwn 0 — ms tosc1 tbmv Memory read mode Command wait state Command wait state Auto-program mode Auto-erase mode Normal/ abnormal end identification tdwn VCC RES FWE Note: Except in auto-program mode and auto-erase mode, drive the FWE input pin low. Figure 19.
Section 19 ROM 19.30 Flash Memory Programming and Erasing Precautions Precautions concerning the use of on-board programming mode, the RAM emulation function, and PROM mode are summarized below. Use the specified voltages and timing for programming and erasing: Applied voltages in excess of the rating can permanently damage the device. Use a PROM programmer that supports the Renesas microcomputer device type with 512-kbyte on-chip flash memory (FZTAT512V3A).
Section 19 ROM Do not apply a constant high level to the FWE pin: Apply a high level to the FWE pin only when programming or erasing flash memory. A system configuration in which a high level is constantly applied to the FWE pin should be avoided. Also, while a high level is applied to the FWE pin, the watchdog timer should be activated to prevent overprogramming or overerasing due to program runaway, etc.
Section 19 ROM Do not touch the socket adapter or chip during programming: Touching either of these can cause contact faults and write errors.
Section 19 ROM Wait time: x Programming/ erasing possible Wait time: 100 μs φ Min 0 μs tOSC1 VCC FWE MD2 to MD0*1 tMDS*3 RES SWE set SWE cleared SWE bit Period during which flash memory access is prohibited (x: Wait time after setting SWE bit)*2 Period during which flash memory can be programmed (Execution of program in flash memory prohibited, and data reads other than verify operations prohibited) Notes: 1.
Wait time: 100 μs Wait time: x Programming/erasing possible Wait time: 100 μs Wait time: x Programming/erasing possible Wait time: 100 μs Wait time: x Programming/erasing possible Wait time: 100 μs Wait time: x Programming/erasing possible Section 19 ROM φ tOSC1 VCC Min 0 μs FWE tMDS tMDS*2 MD2 to MD0 tMDS tRESW RES SWE bit SWE set Mode change*1 SWE cleared Boot mode Mode User change*1 mode User program mode User mode User program mode Period during which flash memory access is prohib
Section 20 Clock Pulse Generator Section 20 Clock Pulse Generator 20.1 Overview The chip has an on-chip clock pulse generator (CPG) that generates the system clock (φ), the bus master clock, and internal clocks. The clock pulse generator consists of an oscillator circuit, a duty adjustment circuit, a mediumspeed clock divider, and a bus master clock selection circuit.
Section 20 Clock Pulse Generator 20.1.2 Register Configuration The clock pulse generator is controlled by SCKCR. Table 20.1 shows the register configuration. Table 20.1 Clock Pulse Generator Register Name Abbreviation R/W Initial Value Address* System clock control register SCKCR R/W H'00 H'FF3A Note: * Lower 16 bits of the address. 20.2 Register Descriptions 20.2.
Section 20 Clock Pulse Generator Bit 5—Division Ratio Select (DIV): When the DIV bit is set to 1, the medium-speed mode is disabled and a clock obtained using the division ratio set with bits SCK2 to SCK0 is supplied to the entire chip. In this way, the current dissipation within the chip is reduced in proportion to the division ratio. As the frequency of φ changes, the following points must be noted.
Section 20 Clock Pulse Generator Bit 2 SCK2 Bit 1 SCK1 Bit 0 SCK0 0 0 1 1 0 1 20.
Section 20 Clock Pulse Generator Crystal Resonator: Figure 20.3 shows the equivalent circuit of the crystal resonator. Use a crystal resonator that has the characteristics shown in table 20.3 and the same resonance frequency as the system clock (φ). CL L Rs XTAL EXTAL AT-cut parallel-resonance type C0 Figure 20.3 Crystal Resonator Equivalent Circuit Table 20.
Section 20 Clock Pulse Generator 20.3.2 External Clock Input Circuit Configuration: An external clock signal can be input as shown in the examples in figure 20.5. If the XTAL pin is left open, make sure that stray capacitance is no more than 10 pF. In example (b), make sure that the external clock is held high in standby mode. EXTAL External clock input XTAL Open (a) XTAL pin left open EXTAL External clock input XTAL (b) Complementary clock input at XTAL pin Figure 20.
Section 20 Clock Pulse Generator Table 20.4 External Clock Input Conditions VCC = 2.7 V to 3.6 V VCC = 3.0 V to 3.6 V Item Symbol Min Max Min Max Unit Test Conditions External clock input low pulse width tEXL 20 — 10 — ns Figure 20.6 External clock input high pulse width tEXH 20 — 10 — ns External clock rise time tEXr — 5 — 5 ns External clock fall time tEXf — 5 — 5 ns Clock low pulse width level tCL Clock high pulse width tCH level 0.4 0.6 0.4 0.
Section 20 Clock Pulse Generator 20.4 Duty Adjustment Circuit When the oscillator frequency is 5 MHz or higher, the duty adjustment circuit adjusts the duty cycle of the clock signal from the oscillator to generate the system clock (φ). 20.5 Medium-Speed Clock Divider The medium-speed clock divider divides the system clock to generate φ/2, φ/4, φ/8, φ/16, and φ/32. 20.
Section 21 Power-Down Modes Section 21 Power-Down Modes 21.1 Overview In addition to the normal program execution state, the chip has five power-down modes in which operation of the CPU and oscillator is halted and power dissipation is reduced. Low-power operation can be achieved by individually controlling the CPU, on-chip supporting modules, and so on. The chip operating modes are as follows: 1. High-speed mode 2. Medium-speed mode 3. Sleep mode 4. Module stop mode 5. Software standby mode 6.
Section 21 Power-Down Modes Table 21.
Section 21 Power-Down Modes 21.2 Register Descriptions 21.2.1 Standby Control Register (SBYCR) Bit : Initial value : R/W : 7 6 5 4 3 2 1 0 SSBY STS2 STS1 STS0 OPE — — IRQ37S 0 0 0 0 1 0 0 0 R/W R/W R/W R/W R/W — — R/W SBYCR is an 8-bit readable/writable register that performs software standby mode control. SBYCR is initialized to H'08 by a reset and in hardware standby mode. It is not initialized in software standby mode.
Section 21 Power-Down Modes Bit 6 STS2 Bit 5 STS1 Bit 4 STS0 Description 0 0 0 Standby time = 8192 states 1 Standby time = 16384 states 1 0 Standby time = 32768 states 1 Standby time = 65536 states 0 Standby time = 131072 states 1 Standby time = 262144 states 0 Reserved 1 Standby time = 16 states* 1 0 1 (Initial value) Note: * Not available in the F-ZTAT versions.
Section 21 Power-Down Modes 21.2.
Section 21 Power-Down Modes • The division ratio can be changed while the chip is operating. The clock output from the φ pin will also change when the division ratio is changed. The frequency of the clock output from the φ pin in this case will be as follows: φ = EXTAL × n Where: EXTAL: Crystal resonator or external clock frequency Division ratio (n = φ/2, φ/4, or φ/8) n: • Do not set the DIV bit and bits SCK2 to SCK0 simultaneously. First set the DIV bit, then bits SCK2 to SCK0.
Section 21 Power-Down Modes 21.2.3 Module Stop Control Register (MSTPCR) MSTPCRH Bit MSTPCRL : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 R/W : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W MSTPCR is a 16-bit readable/writable register that performs module stop mode control. MSTPCR is initialized to H'3FFF by a reset and in hardware standby mode. It is not initialized in software standby mode.
Section 21 Power-Down Modes If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, a transition is made to software standby mode. When software standby mode is cleared by an external interrupt, medium-speed mode is restored. When the RES pin is driven low, a transition is made to the reset state, and medium-speed mode is cleared. The same applies in the case of a reset caused by overflow of the watchdog timer.
Section 21 Power-Down Modes 21.5 Module Stop Mode 21.5.1 Module Stop Mode Module stop mode can be set for individual on-chip supporting modules. When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of the bus cycle and a transition is made to module stop mode. The CPU continues operating independently. Table 21.3 shows MSTP bits and the corresponding on-chip supporting modules.
Section 21 Power-Down Modes Table 21.
Section 21 Power-Down Modes 21.6 Software Standby Mode 21.6.1 Software Standby Mode If a SLEEP instruction is executed when the SSBY bit in SBYCR is set to 1, software standby mode is entered. In this mode, the CPU, on-chip supporting modules, and oscillator all stop. However, the contents of the CPU’s internal registers, RAM data, and the states of on-chip supporting modules other than the SCI and A/D converter, and I/O ports, are retained.
Section 21 Power-Down Modes 21.6.3 Setting Oscillation Stabilization Time after Clearing Software Standby Mode Bits STS2 to STS0 in SBYCR should be set as described below. Using a Crystal Oscillator: Set bits STS2 to STS0 so that the standby time is at least 8 ms (the oscillation stabilization time). Table 21.4 shows the standby times for different operating frequencies and settings of bits STS2 to STS0. Table 21.
Section 21 Power-Down Modes Software standby mode is then cleared at the rising edge on the NMI pin. Oscillator φ NMI NMIEG SSBY NMI exception handling NMIEG=1 SSBY=1 Software standby mode (power-down mode) Oscillation stabilization time tOSC2 NMI exception handling SLEEP instruction Figure 21.2 Software Standby Mode Application Example 21.6.5 Usage Notes I/O Port Status: In software standby mode, I/O port states are retained.
Section 21 Power-Down Modes 21.7 Hardware Standby Mode 21.7.1 Hardware Standby Mode When the STBY pin is driven low, a transition is made to hardware standby mode from any mode. In hardware standby mode, all functions enter the reset state and stop operation, resulting in a significant reduction in power dissipation. As long as the prescribed voltage is supplied, on-chip RAM data is retained. I/O ports are set to the high-impedance state.
Section 21 Power-Down Modes Oscillator RES STBY Oscillation stabilization time Reset exception handling Figure 21.3 Hardware Standby Mode Timing 21.8 φ Clock Output Disabling Function Output of the φ clock can be controlled by means of the PSTOP bit in SCKCR, and DDR for the corresponding port. When the PSTOP bit is set to 1, the φ clock stops at the end of the bus cycle, and φ output goes high. φ clock output is enabled when the PSTOP bit is cleared to 0.
Section 21 Power-Down Modes Rev.6.00 Sep.
Section 22 Electrical Characteristics Section 22 Electrical Characteristics 22.1 Electrical Characteristics of Mask ROM Version (H8S/2328, H8S/2327, H8S/2323) and ROMless Version (H8S/2324S, H8S/2322R, H8S/2321, H8S/2320) 22.1.1 Absolute Maximum Ratings Table 22.1 lists the absolute maximum ratings. Table 22.1 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage VCC –0.3 to +4.6 V Input voltage (except port 4) Vin –0.3 to VCC +0.3 V Input voltage (port 4) Vin –0.
Section 22 Electrical Characteristics 22.1.2 DC Characteristics Table 22.2 DC Characteristics (H8S/2328, H8S/2327, H8S/2323) Conditions: VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V*1, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (widerange specifications) Item Symbol Schmitt Ports 1, 2, trigger input P6 to P6 4 7 voltage PA4 to PA7 VT – VT + Test Conditions Min Typ Max Unit VCC × 0.2 — — V — — VCC × 0.7 V VCC × 0.
Section 22 Electrical Characteristics Item Symbol Test Conditions Min Typ Max Unit Three-state Ports 1, 2, 3, 5, 6, A | ITSI | leakage to G current (off state) — — 1.0 μA Vin = 0.5 V to VCC – 0.5 V Input pull-up Ports A to E MOS current –Ip 10 — 300 μA VCC = 2.7 V to 3.6 V, Vin = 0 V Input RES capacitance NMI Cin — — 30 pF Vin = 0 V — — 30 pF f = 1 MHz — — 15 pF Ta = 25°C — 40 (3.0 V) 80 mA f = 20 MHz — 55 (3.
Section 22 Electrical Characteristics Table 22.3 DC Characteristics (H8S/2324S, H8S/2322R, H8S/2321, H8S/2320) Conditions: VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V*1, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (widerange specifications) Item Symbol Ports 1, 2, Schmitt trigger input P6 to P6 4 7 voltage PA4 to PA7 VT – VT + + VT – VT – Min Typ Max Unit VCC × 0.2 — — V — — VCC × 0.7 V VCC × 0.06 — — VCC × 0.9 VCC + 0.
Section 22 Electrical Characteristics Test Conditions Item Symbol Min Typ Max Unit Input pull-up Ports A to E MOS current –Ip 10 — 300 μA VCC = 2.7 V to 3.6 V, Vin = 0 V Input RES capacitance NMI Cin — — 30 pF Vin = 0 V — — 30 pF f = 1 MHz — — 15 pF Ta = 25°C — 30 (3.0 V) 66 mA f = 20 MHz — 42 (3.3 V) 82 mA f = 25 MHz — 22 (3.0 V) 51 mA f = 20 MHz — 31 (3.3 V) 64 mA f = 25 MHz — 0.01 10 μA Ta ≤ 50°C — — 80 μA 50°C < Ta — 0.2 (3.0 V) 2.
Section 22 Electrical Characteristics Table 22.4 Permissible Output Currents Conditions: VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (wide-range specifications) Item Symbol Min Typ Max Unit Permissible output low current (per pin) All output pins IOL — — 2.
Section 22 Electrical Characteristics (1) Clock Timing Table 22.5 Clock Timing Condition A: VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, φ = 2 MHz to 20 MHz, Ta = –20°C to 75°C (regular specifications), Ta = –40°C to 85°C (wide-range specifications) Condition B: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.
Section 22 Electrical Characteristics tcyc tCH tCf φ tCL tCr Figure 22.2 System Clock Timing EXTAL tDEXT tDEXT VCC STBY NMI tOSC1 RES φ Figure 22.3 Oscillation Stabilization Timing Rev.6.00 Sep.
Section 22 Electrical Characteristics (2) Control Signal Timing Table 22.6 Control Signal Timing Condition A: VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, φ = 2 MHz to 20 MHz, Ta = –20°C to 75°C (regular specifications), Ta = –40°C to 85°C (wide-range specifications) Condition B: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.
Section 22 Electrical Characteristics φ tRESS tRESS RES tRESW Figure 22.4 Reset Input Timing φ tNMIS tNMIH NMI tNMIW IRQ tIRQW tIRQS tIRQH IRQ edge input tIRQS IRQ level input Figure 22.5 Interrupt Input Timing Rev.6.00 Sep.
Section 22 Electrical Characteristics (3) Bus Timing Table 22.7 Bus Timing Condition A: VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, φ = 2 MHz to 20 MHz, Ta = –20°C to 75°C (regular specifications), Ta = –40°C to 85°C (wide-range specifications) Condition B: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.
Section 22 Electrical Characteristics Condition A Condition B Item Symbol Min Max Min Max Unit Test Conditions WR delay time 1 tWRD1 — 20 — 15 ns WR delay time 2 tWRD2 — 20 — 15 ns Figures 22.6 to 22.13 WR pulse width 1 tWSW1 1.0 × tcyc – 20 — 1.0 × tcyc – 15 — ns WR pulse width 2 tWSW2 1.5 × tcyc – 20 — 1.5 × tcyc – 15 — ns Write data delay time tWDD — 30 — 20 ns Write data setup time tWDS 0.5 × tcyc – 20 — 0.
Section 22 Electrical Characteristics T1 T2 φ tAD A23 to A0 tCSD1 tAS tAH CS7 to CS0 tASD tASD AS tRSD1 tACC2 RD (read) tRDS tRDH tACC3 tAS tRSD2 D15 to D0 (read) tWRD2 HWR, LWR (write) tWRD2 tAS tWDD tWSW1 tAH tWDH D15 to D0 (write) Figure 22.6 Basic Bus Timing (2-State Access) Rev.6.00 Sep.
Section 22 Electrical Characteristics T1 T2 T3 φ tAD A23 to A0 tCSD1 tAH tAS CS7 to CS0 tASD tASD AS tRSD1 RD (read) tACC4 tRSD2 tAS tRDS tRDH tACC5 D15 to D0 (read) tWRD1 HWR, LWR (write) tWDD tWDS tWRD2 tWSW2 D15 to D0 (write) Figure 22.7 Basic Bus Timing (3-State Access) Rev.6.00 Sep.
Section 22 Electrical Characteristics T1 T2 Tw tWTS tWTH tWTS tWTH T3 φ A23 to A0 CS7 to CS0 AS RD (read) D15 to D0 (read) HWR, LWR (write) D15 to D0 (write) WAIT Figure 22.8 Basic Bus Timing (3-State Access, 1 Wait) Rev.6.00 Sep.
Section 22 Electrical Characteristics Tp Tr Tc1 Tc2 φ tAD tAD A23 to A0 tAS tAH tPCH tCSD3 tACC4 CS5 to CS2 (RAS) tCSD2 tCASD tCASD tACC6 CAS tRDS tRDH tACC3 D15 to D0 (read) tWRD2 tWRD2 HWR, (WE) (write) tWDD tWCS tWDS tWCH tWDH D15 to D0 (write) Figure 22.9 DRAM Bus Timing (Not Supported in the H8S/2321) Rev.6.00 Sep.
Section 22 Electrical Characteristics TRp TRr TRc1 TRc2 φ tCSD2 CS5 to CS2 (RAS) tCSD1 tCSR tCASD tCASD CAS Figure 22.10 CAS-Before-RAS Refresh Timing (Not Supported in the H8S/2321) TRp TRr TRc TRc φ tCSD2 tCSD2 CS5 to CS2 (RAS) tCASD tCASD CAS Figure 22.11 Self-Refresh Timing (Not Supported in the H8S/2321) Rev.6.00 Sep.
Section 22 Electrical Characteristics T1 T2 or T3 T1 T2 φ tAD A23 to A0 tAH tAS CS0 tASD tASD AS tRSD2 RD (read) tACC3 D15 to D0 (read) Figure 22.12 Burst ROM Access Timing (2-State Access) Rev.6.00 Sep.
Section 22 Electrical Characteristics T1 T2 or T3 T1 φ tAD A23 to A0 CS0 AS tRSD2 RD (read) tACC1 tRDS tRDH D15 to D0 (read) Figure 22.13 Burst ROM Access Timing (1-State Access) Rev.6.00 Sep.
Section 22 Electrical Characteristics φ tBRQS tBRQS BREQ tBACD tBACD BACK A23 to A0, CS7 to CS0, AS, RD, HWR, LWR, CAS tBZD tBZD Figure 22.14 External Bus Release Timing φ tBRQOD tBRQOD BREQO Figure 22.15 External Bus Request Output Timing Rev.6.00 Sep.
Section 22 Electrical Characteristics (4) DMAC Timing Note: The DMAC is not supported in the H8S/2321. Table 22.8 DMAC Timing Condition A: VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, φ = 2 MHz to 20 MHz, Ta = –20°C to 75°C (regular specifications), Ta = –40°C to 85°C (wide-range specifications) Condition B: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.
Section 22 Electrical Characteristics T1 T2 φ A23 to A0 CS7 to CS0 AS RD (read) D15 to D0 (read) HWR, LWR (write) D15 to D0 (write) tDACD1 tDACD2 DACK0, DACK1 Figure 22.16 DMAC Single Address Transfer Timing (2-State Access) Rev.6.00 Sep.
Section 22 Electrical Characteristics T1 T2 T3 φ A23 to A0 CS7 to CS0 AS RD (read) D15 to D0 (read) HWR, LWR (write) D15 to D0 (write) tDACD1 tDACD2 DACK0, DACK1 Figure 22.17 DMAC Single Address Transfer Timing (3-State Access) Rev.6.00 Sep.
Section 22 Electrical Characteristics T1 T2 or T3 φ tTED tTED TEND0, TEND1 Figure 22.18 DMAC TEND Output Timing φ tDRQS tDRQH DREQ0, DREQ1 Figure 22.19 DMAC DREQ Input Timing Rev.6.00 Sep.
Section 22 Electrical Characteristics (5) Timing of On-Chip Supporting Modules Table 22.9 Timing of On-Chip Supporting Modules Condition A: VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, φ = 2 MHz to 20 MHz, Ta = –20°C to 75°C (regular specifications), Ta = –40°C to 85°C (wide-range specifications) Condition B: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.
Section 22 Electrical Characteristics Condition A Item SCI A/D converter Input clock cycle Asynchronous Condition B Test Symbol Min Max Min Max Unit Conditions tScyc 4 — 4 — tcyc Figure 22.28 6 — 6 — Synchronous Input clock pulse width tSCKW 0.4 0.6 0.4 0.6 tScyc Input clock rise time tSCKr — 1.5 — 1.5 tcyc Input clock fall time tSCKf — 1.5 — 1.
Section 22 Electrical Characteristics φ tTOCD Output compare output* tTICS Input capture input* Note: * TIOCA0 to TIOCA5, TIOCB0 to TIOCB5, TIOCC0, TIOCC3, TIOCD0, TIOCD3 Figure 22.22 TPU Input/Output Timing φ tTCKS tTCKS TCLKA to TCLKD tTCKWL tTCKWH Figure 22.23 TPU Clock Input Timing φ tTMOD TMO0, TMO1 Figure 22.24 8-Bit Timer Output Timing Rev.6.00 Sep.
Section 22 Electrical Characteristics φ tTMCS tTMCS TMCI0, TMCI1 tTMCWL tTMCWH Figure 22.25 8-Bit Timer Clock Input Timing φ tTMRS TMRI0, TMRI1 Figure 22.26 8-Bit Timer Reset Input Timing φ tWOVD tWOVD WDTOVF Figure 22.27 WDT Output Timing tSCKW tSCKr tSCKf SCK0 to SCK2 tScyc Figure 22.28 SCK Clock Input Timing Rev.6.00 Sep.
Section 22 Electrical Characteristics SCK0 to SCK2 tTXD TxD0 to TxD2 (transmit data) tRXS tRXH RxD0 to RxD2 (receive data) Figure 22.29 SCI Input/Output Timing (Synchronous Mode) φ tTRGS ADTRG Figure 22.30 A/D Converter External Trigger Input Timing Rev.6.00 Sep.
Section 22 Electrical Characteristics 22.1.4 A/D Conversion Characteristics Table 22.10 A/D Conversion Characteristics Condition A: VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, φ = 2 MHz to 20 MHz, Ta = –20°C to 75°C (regular specifications), Ta = –40°C to 85°C (wide-range specifications) Condition B: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.
Section 22 Electrical Characteristics 22.1.5 D/A Conversion Characteristics Table 22.11 D/A Conversion Characteristics Condition A: VCC = 2.7 V to 3.6 V, AVCC = 2.7 V to 3.6 V, Vref = 2.7 V to AVCC, VSS = AVSS = 0 V, φ = 2 MHz to 20 MHz, Ta = –20°C to 75°C (regular specifications), Ta = –40°C to 85°C (wide-range specifications) Condition B: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.
Section 22 Electrical Characteristics 22.2 Electrical Characteristics of F-ZTAT (H8S/2329B F-ZTAT, H8S/2329E F-ZTAT, H8S/2328B F-ZTAT, H8S/2326 F-ZTAT) 22.2.1 Absolute Maximum Ratings Table 22.12 Absolute Maximum Ratings Item Symbol Value Unit Power supply voltage 2 3 Input voltage (FWE* , EMLE* ) VCC –0.3 to +4.3 V Vin –0.3 to VCC +0.3 V Input voltage (except port 4) Vin –0.3 to VCC +0.3 V Input voltage (port 4) Vin –0.3 to AVCC +0.3 V Reference power supply voltage Vref –0.
Section 22 Electrical Characteristics 22.2.2 DC Characteristics Table 22.13 DC Characteristics Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V*1, Ta = –20°C to +75°C (regular specifications), Ta = –40°C to +85°C (widerange specifications) Item Schmitt trigger input voltage Symbol Ports 1, 2, P64 to P67 PA4 to PA7 VT – VT + + VT – VT – Min Typ Max Test Unit Conditions VCC × 0.2 — — V — — VCC × 0.7 V VCC × 0.07 — — VCC × 0.9 VCC + 0.
Section 22 Electrical Characteristics Item Three-state leakage current (off state) Symbol Ports 1, 2, 3, 5, 6, A | ITSI | to G Min Typ Max Test Unit Conditions — — 1.0 μA Vin = 0.5 V to VCC – 0.5 V Input pull-up Ports A to E MOS current –Ip 10 — 300 μA VCC = 3.0 V to 3.6 V, Vin = 0 V Input RES capacitance NMI Cin — — 30 pF Vin = 0 V — — 30 pF f = 1 MHz — — 15 pF Ta = 25°C — 55 (3.3 V) 100 mA f = 25 MHz — 44 (3.
Section 22 Electrical Characteristics Table 22.14 Permissible Output Currents Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, Ta = –20 to +75°C (regular specifications), Ta = –40 to +85°C (wide-range specifications) Item Symbol Min Typ Max Unit Permissible output low current (per pin) All output pins IOL — — 2.
Section 22 Electrical Characteristics 22.2.3 AC Characteristics (1) Clock Timing Table 22.15 Clock Timing Condition B: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 2 MHz to 25 MHz, Ta = –20°C to 75°C (regular specifications), Ta = –40°C to 85°C (wide-range specifications) Condition B Item Symbol Min Max Unit Test Conditions Clock cycle time tcyc 40 500 ns Figure 22.
Section 22 Electrical Characteristics (2) Control Signal Timing Table 22.16 Control Signal Timing Condition B: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 2 MHz to 25 MHz, Ta = –20°C to 75°C (regular specifications), Ta = –40°C to 85°C (wide-range specifications) Condition B Item Symbol Min Max Unit Test Conditions RES setup time tRESS 200 — ns Figure 22.
Section 22 Electrical Characteristics (3) Bus Timing Table 22.17 Bus Timing Condition B: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 2 MHz to 25 MHz, Ta = –20°C to 75°C (regular specifications), Ta = –40°C to 85°C (wide-range specifications) Condition B Item Symbol Min Max Unit Test Conditions Address delay time tAD — 20 ns Figures 22.6 to 22.13 Address setup time tAS 0.5 × tcyc – 15 — ns Address hold time tAH 0.
Section 22 Electrical Characteristics Condition B Item Symbol Min Max Unit Test Conditions CAS setup time tCSR 0.5 × tcyc – 8 — ns Figure 22.10 WAIT setup time tWTS 25 — ns Figure 22.8 WAIT hold time tWTH 5 — ns BREQ setup time tBRQS 30 — ns BACK delay time tBACD — 15 ns Bus floating time tBZD — 40 ns BREQO delay time tBRQOD — 25 ns Figure 22.14 Figure 22.15 (4) DMAC Timing Table 22.18 DMAC Timing Condition B: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.
Section 22 Electrical Characteristics (5) Timing of On-Chip Supporting Modules Table 22.19 Timing of On-Chip Supporting Modules Condition B: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 2 MHz to 25 MHz, Ta = –20°C to 75°C (regular specifications), Ta = –40°C to 85°C (wide-range specifications) Condition B Item I/O ports Symbol Min Max Unit Test Conditions Output data delay time tPWD — 40 ns Figure 22.
Section 22 Electrical Characteristics 22.2.4 A/D Conversion Characteristics Table 22.20 A/D Conversion Characteristics Condition B: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 2 MHz to 25 MHz, Ta = –20°C to 75°C (regular specifications), Ta = –40°C to 85°C (wide-range specifications) Condition B Item Min Typ Max Unit Resolution 10 10 10 Bits Conversion time 10.
Section 22 Electrical Characteristics 22.2.5 D/A Conversion Characteristics Table 22.21 D/A Conversion Characteristics Condition B: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V, φ = 2 MHz to 25 MHz, Ta = –20°C to 75°C (regular specifications), Ta = –40°C to 85°C (wide-range specifications) Condition B Item Min Typ Max Unit Resolution 8 8 8 Bits Conversion time — — 10 μs 20 pF capacitive load Absolute accuracy — ±2.0 ±3.
Section 22 Electrical Characteristics 22.2.6 Flash Memory Characteristics Table 22.22 Flash Memory Characteristics Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.
Section 22 Electrical Characteristics Notes: 1. Follow the program/erase algorithms when making the time settings. 2. Programming time per 128 bytes. (In the H8S/2329B and H8S/2328B, indicates the total time during which the P bit is set in flash memory control register 1 (FLMCR1). In the H8S/2326, indicates the total time during which the P1 bit and P2 bit in flash memory control registers 1 and 2 (FLMCR1, FLMCR2) are set. Does not include the program-verify time.) 3. Time to erase one block.
Appendix A Instruction Set Appendix A Instruction Set A.
Appendix A Instruction Set Condition Code Notation Symbol Changes according to the result of the instruction * Undetermined (no guaranteed value) 0 Always cleared to 0 1 Always set to 1 — Not affected by execution of the instruction Rev.6.00 Sep.
MOV Operand Size B MOV.B @aa:16,Rd MOV.B @aa:32,Rd W 4 W MOV.W @ERs,Rd MOV.B Rs,@aa:32 W B MOV.B Rs,@aa:16 MOV.W Rs,Rd B MOV.B Rs,@aa:8 MOV.W #xx:16,Rd B B MOV.B Rs,@-ERd B B MOV.B @aa:8,Rd MOV.B Rs,@(d:32,ERd) B MOV.B @ERs+,Rd B B MOV.B @(d:32,ERs),Rd MOV.B Rs,@(d:16,ERd) B MOV.B @(d:16,ERs),Rd B B MOV.B @ERs,Rd MOV.B Rs,@ERd B B MOV.B Rs,Rd B 2 2 2 2 2 2 8 4 8 4 2 2 6 4 2 6 4 2 #xx Rn @ERn @(d,ERn) @–ERn/@ERn+ @aa @(d,PC) MOV.
MOV Rev.6.00 Sep. 27, 2007 Page 982 of 1268 REJ09B0220-0600 W W W L 6 L L L L MOV.W Rs,@(d:32,ERd) MOV.W Rs,@-ERd MOV.W Rs,@aa:16 MOV.W Rs,@aa:32 MOV.L #xx:32,ERd MOV.L ERs,ERd MOV.L @ERs,ERd MOV.L @(d:16,ERs),ERd MOV.L @(d:32,ERs),ERd L W MOV.W Rs,@(d:16,ERd) MOV.L @aa:32,ERd W MOV.W Rs,@ERd L W MOV.W @aa:32,Rd L W MOV.W @aa:16,Rd MOV.L @aa:16,ERd W MOV.W @ERs+,Rd MOV.L @ERs+,ERd W W MOV.
— — — — — — — — — — — — — — @SP→Rn16,SP+2→SP @SP→ERn32,SP+4→SP SP-2→SP,Rn16→@SP SP-4→SP,ERn32→@SP (@SP→ERn32,SP+4→SP) [2] [2] Cannot be used in the chip Cannot be used in the chip MOVFPE @aa:16,Rd MOVTPE Rs,@aa:16 MOVFPE MOVTPE 4 Repeated for each register saved (SP-4→SP,ERn32→@SP) Repeated for each register restored L STM (ERm-ERn),@-SP — — — — — — 7/9/11 [1] 7/9/11 [1] 5 3 STM 4 0 — 0 — L 4 2 LDM @SP+,(ERm-ERn) 5 3 6 LDM 0 — 0 — 5 L PUSH 4 2 0 — — — ERs32→@aa:32 0
B L L L B W W L L B B W 4 ADDS #1,ERd ADDS #2,ERd ADDS #4,ERd INC.B Rd INC.W #1,Rd INC.W #2,Rd INC.L #1,ERd INC.L #2,ERd DAA Rd SUB.B Rs,Rd SUB.W #xx:16,Rd DAA SUB INC ADDS ADDX ADDX Rs,Rd ADD.L #xx:32,ERd L L 6 ADD.W Rs,Rd B 2 W ADD.W #xx:16,Rd ADDX #xx:8,Rd B W 4 ADD.B Rs,Rd B 2 Operand Size ADD.B #xx:8,Rd 2 2 2 2 2 2 2 2 2 2 2 2 2 2 #xx Rn @ERn @(d,ERn) @–ERn/@ERn+ ADD.
B W B W DAS Rd MULXU.B Rs,Rd MULXU.W Rs,ERd MULXS.B Rs,Rd MULXS.W Rs,ERd MULXU MULXS L B DEC.L #2,ERd L L SUBS #4,ERd DEC.L #1,ERd L SUBS #2,ERd W L SUBS #1,ERd DEC.W #2,Rd B SUBX Rs,Rd B B 2 SUBX #xx:8,Rd W L SUB.L ERs,ERd DEC.W #1,Rd L 6 SUB.L #xx:32,ERd DEC.B Rd W SUB.
Rev.6.00 Sep. 27, 2007 Page 986 of 1268 REJ09B0220-0600 EXTU NEG CMP DIVXS L W L EXTU.W Rd EXTU.L ERd W NEG.W Rd NEG.L ERd L B L 6 CMP.L #xx:32,ERd NEG.B Rd W CMP.W Rs,Rd CMP.L ERs,ERd B B 2 CMP.B #xx:8,Rd W 4 W DIVXS.W Rs,ERd CMP.W #xx:16,Rd B DIVXS.B Rs,Rd CMP.B Rs,Rd W DIVXU.W Rs,ERd 2 2 2 2 2 2 2 2 4 4 2 2 B DIVXU.
LDMAC ERs,MACH LDMAC STMAC MACL,ERd STMAC MACH,ERd LDMAC ERs,MACL CLRMAC CLRMAC STMAC Cannot be used in the chip MAC @ERn+, @ERm+ MAC 4 B TAS @ERd*3 TAS 2 L EXTS.L ERd Operand Size #xx Rn @ERn 2 @(d,ERn) @–ERn/@ERn+ W @aa @(d,PC) @@aa — EXTS.W Rd EXTS Mnemonic ( of @ERd) @ERd-0→CCR set, (1)→ ( of ERd32) ( of ERd32)→ ( of Rd16) ( of Rd16)→ Operation Advanced I H N Z V C — — — — — — No.
Rev.6.00 Sep. 27, 2007 Page 988 of 1268 REJ09B0220-0600 NOT XOR OR AND L NOT.L ERd L XOR.L ERs,ERd B L 6 XOR.L #xx:32,ERd W W XOR.W Rs,Rd NOT.W Rd W 4 XOR.W #xx:16,Rd NOT.B Rd B L OR.L ERs,ERd B 2 L 6 OR.L #xx:32,ERd XOR.B Rs,Rd W XOR.B #xx:8,Rd W 4 OR.W Rs,Rd L AND.L ERs,ERd OR.W #xx:16,Rd L 6 AND.L #xx:32,ERd B W AND.W Rs,Rd OR.B Rs,Rd W 4 AND.W #xx:16,Rd B 2 B OR.B #xx:8,Rd B 2 AND.
SHLL SHAR SHAL B B W W L L SHLL.W Rd SHLL.W #2,Rd SHLL.L ERd SHLL.L #2,ERd L SHAR.L #2,ERd SHLL.B #2,Rd L SHAR.L ERd SHLL.B Rd W SHAR.W #2,Rd W SHAL.L #2,ERd SHAR.W Rd L L SHAL.L ERd B W SHAL.W #2,Rd SHAR.B #2,Rd W SHAL.W Rd B B SHAR.B Rd B SHAL.B #2,Rd 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Operand Size #xx Rn @ERn SHAL.
Rev.6.00 Sep. 27, 2007 Page 990 of 1268 REJ09B0220-0600 ROTXR ROTXL SHLR B W W L L ROTXR.W Rd ROTXR.W #2,Rd ROTXR.L ERd ROTXR.L #2,ERd L ROTXL.L #2,ERd B L ROTXL.L ERd ROTXR.B #2,Rd W ROTXL.W #2,Rd ROTXR.B Rd W ROTXL.W Rd SHLR.L #2,ERd B L SHLR.L ERd ROTXL.B #2,Rd L SHLR.W #2,Rd B W SHLR.W Rd ROTXL.B Rd B W SHLR.B #2,Rd B 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 Operand Size #xx Rn @ERn @(d,ERn) @–ERn/@ERn+ @aa @(d,PC) @@aa — SHLR.
ROTR ROTL W L L ROTL.W #2,Rd ROTL.L ERd ROTL.L #2,ERd B W W L L ROTR.B #2,Rd ROTR.W Rd ROTR.W #2,Rd ROTR.L ERd ROTR.L #2,ERd B W ROTL.W Rd ROTR.B Rd B B ROTL.B #2,Rd 2 2 2 2 2 2 2 2 2 2 2 2 MSB C — — — — — — — — 1 — — — — — — — — — — — LSB LSB — MSB C — — — — — — — — 0 0 0 0 0 0 0 0 0 0 0 0 I H N Z V C ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ ↔ Operand Size #xx Rn @ERn @(d,ERn) @–ERn/@ERn+ @aa @(d,PC) @@aa — ROTL.
Rev.6.00 Sep.
BTST B B B B B B BNOT Rn,@aa:32 BTST #xx:3,Rd BTST #xx:3,@ERd BTST #xx:3,@aa:8 BTST #xx:3,@aa:16 B BNOT Rn,Rd BNOT Rn,@aa:16 B BNOT #xx:3,@aa:32 B B BNOT #xx:3,@aa:16 B B BNOT #xx:3,@aa:8 BNOT Rn,@aa:8 B BNOT #xx:3,@ERd BNOT Rn,@ERd B BNOT #xx:3,Rd B BCLR Rn,@aa:32 BNOT 2 2 2 4 4 4 6 4 8 6 4 8 6 4 8 Operand Size #xx Rn @ERn @(d,ERn) @–ERn/@ERn+ @aa @(d,PC) @@aa — BCLR Mnemonic 6 — — — — — — — — — — — — — — — — — — ¬ (#xx:3 of Rd8)→Z ¬ (#xx:3 of @ERd)→Z ¬ (#x
Rev.6.00 Sep.
BOR BIAND BAND BIST BST B B B B B B B B B B B B B B B B B BIST #xx:3,@ERd BIST #xx:3,@aa:8 BIST #xx:3,@aa:16 BIST #xx:3,@aa:32 BAND #xx:3,Rd BAND #xx:3,@ERd BAND #xx:3,@aa:8 BAND #xx:3,@aa:16 BAND #xx:3,@aa:32 BIAND #xx:3,Rd BIAND #xx:3,@ERd BIAND #xx:3,@aa:8 BIAND #xx:3,@aa:16 BIAND #xx:3,@aa:32 BOR #xx:3,Rd BOR #xx:3,@ERd B BIST #xx:3,Rd B BST #xx:3,@aa:32 2 2 2 2 4 4 4 4 8 6 4 8 6 4 8 6 4 8 6 Operand Size #xx Rn @ERn @(d,ERn) @–ERn/@ERn+ @aa @(d,PC) @@aa — BS
Rev.6.00 Sep.
Bcc — — — — — — — — — — — — — — — — — BRA d:16(BT d:16) BRN d:8(BF d:8) BRN d:16(BF d:16) BHI d:8 BHI d:16 BLS d:8 BLS d:16 BCC d:B(BHS d:8) BCC d:16(BHS d:16) BCS d:8(BLO d:8) BCS d:16(BLO d:16) BNE d:8 BNE d:16 BEQ d:8 BEQ d:16 BVC d:8 BVC d:16 — BRA d:8(BT d:8) Mnemonic Addressing Mode/ Instruction Length (Bytes) 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 4 2 Operand Size #xx Rn @ERn @(d,ERn) @–ERn/@ERn+ @aa @(d,PC) @@aa — (6) Branch Instructions Branching Condition else n
Bcc Rev.6.00 Sep.
RTS JSR BSR JMP Operand Size — — — — — — — — — Mnemonic JMP @ERn JMP @aa:24 JMP @@aa:8 BSR d:8 BSR d:16 JSR @ERn JSR @aa:24 JSR @@aa:8 RTS #xx Rn @ERn @(d,ERn) @–ERn/@ERn+ 2 2 4 4 4 2 2 2 — — — — — — — — — — — — PC→@-SP,PC←aa:24 PC→@-SP,PC←@aa:8 — — — — — — — — — — — — — — — — — — PC→@-SP,PC←PC+d:8 — — — — — — — — — — — — PC←@aa:8 PC→@-SP,PC←ERn — — — — — — PC→@-SP,PC←PC+d:16 — — — — — — PC←aa:24 I H N Z V C Condition Code PC←ERn Operation 2 PC←@SP+ @aa @(d,PC) @@aa
W W W W W W W W W W LDC @(d:16,ERs),EXR LDC @(d:32,ERs),CCR LDC @(d:32,ERs),EXR LDC @ERs+,CCR LDC @ERs+,EXR LDC @aa:16,CCR LDC @aa:16,EXR LDC @aa:32,CCR LDC @aa:32,EXR W LDC @ERs,EXR LDC @(d:16,ERs),CCR W B 4 LDC #xx:8,EXR LDC @ERs,CCR B 2 LDC #xx:8,CCR LDC B — SLEEP SLEEP B — RTE RTE LDC Rs,EXR — Mnemonic LDC Rs,CCR Operand Size TRAPA #xx:2 2 2 4 4 10 10 6 6 4 4 #xx Rn @ERn @(d,ERn) @–ERn/@ERn+ TRAPA @aa @(d,PC) @@aa — 8 8 6 6 Operation 8 [9] 3 3 — — — —
NOP XORC ORC ANDC W W B 2 B 4 B 2 B 4 B 2 B 4 — STC EXR,@aa:32 ANDC #xx:8,CCR ANDC #xx:8,EXR ORC #xx:8,CCR ORC #xx:8,EXR XORC #xx:8,CCR XORC #xx:8,EXR NOP 10 10 6 4 8 8 6 4 4 EXR→@(d:32,ERd) ERd32-2→ERd32,CCR→@ERd — — — — — — ERd32-2→ERd32,EXR→@ERd 2 1 — — — — — — — — — — — — EXR⊕#xx:8→EXR 1 2 1 — — — — — — CCR∨#xx:8→CCR CCR⊕#xx:8→CCR 2 EXR∨#xx:8→EXR 1 EXR→@aa:32 — — — — — — — — — — — — — — — — — — CCR→@aa:32 EXR∧#xx:8→EXR 5 5 — — — — — — EXR→@aa:16 CCR∧#xx:8→CCR
Rev.6.00 Sep. 27, 2007 Page 1002 of 1268 REJ09B0220-0600 Notes: 1. 2. 3. [1] [2] [3] [4] [5] [6] [7] [8] [9] EEPMOV — EEPMOV.W — — — — — — 4 if R4 0 Repeat @ER5→@ER6 ER5+1→ER5 ER6+1→ER6 R4-1→R4 Until R4=0 else next; I H N Z V C — — — — — — 4 if R4L 0 Repeat @ER5→@ER6 ER5+1→ER5 ER6+1→ER6 R4L-1→R4L Until R4L=0 else next; Operation Condition Code 4+2n *2 4+2n *2 Advanced No.
Appendix A Instruction Set A.2 Instruction Codes Table A.2 shows the instruction codes. Rev.6.00 Sep.
Rev.6.00 Sep. 27, 2007 Page 1004 of 1268 REJ09B0220-0600 Bcc BAND ANDC AND ADDX 0 5 4 5 — — — BRN d:8 (BF d:8) BRN d:16 (BF d:16) 6 B BAND #xx:3,@aa:32 BRA d:16 (BT d:16) 6 B BAND #xx:3,@aa:16 4 7 B BAND #xx:3,@aa:8 — 7 B BAND #xx:3,@ERd BRA d:8 (BT d:8) 7 B 0 BAND #xx:3,Rd 0 0 L AND.L ERs,ERd B 7 L AND.L #xx:32,ERd B 6 W AND.W Rs,Rd ANDC #xx:8,EXR 7 AND.W #xx:16,Rd ANDC #xx:8,CCR 1 B W AND.B Rs,Rd E B B ADDX Rs,Rd AND.
Bcc Instruction — — — BGT d:16 BLE d:8 BLE d:16 — BPL d:8 — — BVS d:16 — — BVS d:8 BGT d:8 — BVC d:16 BLT d:16 — BVC d:8 — — BEQ d:16 — — BEQ d:8 BLT d:8 — BNE d:16 BGE d:16 — BNE d:8 — — BCS d:16 (BLO d:16) — — BCS d:8 (BLO d:8) BGE d:8 — BCC d:16 (BHS d:16) BMI d:16 — BCC d:8 (BHS d:8) — — BLS d:16 — — BLS d:8 BMI d:8 — BHI d:16 BPL d:16 — Size BHI d:8 Mnemonic 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 5 4 8 F
Rev.6.00 Sep.
BNOT BLD BIXOR BIST Instruction B B B B B B B B BNOT #xx:3,@aa:8 BNOT #xx:3,@aa:16 BNOT #xx:3,@aa:32 BNOT Rn,Rd BNOT Rn,@ERd BNOT Rn,@aa:8 BNOT Rn,@aa:16 BNOT Rn,@aa:32 B B BLD #xx:3,@aa:32 BNOT #xx:3,@ERd B BLD #xx:3,@aa:16 B B BNOT #xx:3,Rd B BLD #xx:3,@aa:8 B BIXOR #xx:3,@aa:32 BLD #xx:3,@ERd B BIXOR #xx:3,@aa:16 B B BLD #xx:3,Rd B B BIST #xx:3,@aa:32 BIXOR #xx:3,@aa:8 B BIST #xx:3,@aa:16 BIXOR #xx:3,@ERd B BIST #xx:3,@aa:8 B B BIST #xx:3,@ERd BIXOR #xx:3,Rd
Rev.6.00 Sep.
L CMP.L ERs,ERd L DEC.L #2,ERd — — DIVXU.W Rs,ERd EEPMOV.W B W DIVXU.B Rs,Rd W L DEC.L #1,ERd DIVXS.W Rs,ERd W DEC.W #2,Rd B W DEC.W #1,Rd DIVXS.B Rs,Rd B DEC.B Rd EEPMOV EEPMOV.B DIVXU DIVXS DEC B B L CMP.L #xx:32,ERd DAS Rd W CMP.W Rs,Rd DAA Rd W CMP.W #xx:16,Rd DAS B DAA B CMP.B Rs,Rd B BXOR #xx:3,@aa:32 CMP.
Rev.6.00 Sep. 27, 2007 Page 1010 of 1268 REJ09B0220-0600 LDC JSR JMP INC EXTU EXTS Instruction B W W W W W W W W W W LDC @ERs,EXR LDC @(d:16,ERs),CCR LDC @(d:16,ERs),EXR LDC @(d:32,ERs),CCR LDC @(d:32,ERs),EXR LDC @ERs+,CCR LDC @ERs+,EXR LDC @aa:16,CCR LDC @aa:16,EXR B LDC Rs,CCR LDC @ERs,CCR B LDC Rs,EXR B — JSR @@aa:8 LDC #xx:8,EXR — JSR @aa:24 LDC #xx:8,CCR — JSR @ERn — JMP @@aa:8 INC.L #2,ERd — L INC.L #1,ERd JMP @aa:24 L INC.W #2,Rd — W INC.
B B B W W W W W MOV.B Rs,@aa:8 MOV.B Rs,@aa :16 MOV.B Rs,@aa:32 MOV.W #xx:16,Rd MOV.W Rs,Rd MOV.W @ERs,Rd MOV.W @(d:16,ERs),Rd MOV.W @(d:32,ERs),Rd B MOV.B @aa:32,Rd B B MOV.B @aa:16,Rd MOV.B Rs,@-ERd B MOV.B @aa:8,Rd B B MOV.B @ERs+,Rd B B MOV.B @(d:32,ERs),Rd MOV.B Rs,@(d:32,ERd) B MOV.B @(d:16,ERs),Rd MOV.B Rs,@(d:16,ERd) B MOV.B @ERs,Rd B B MOV.B Rs,Rd MOV.B Rs,@ERd B MOV.B #xx:8,Rd MOV L — MAC @ERn+,@ERm+ LDMAC ERs,MACL L LDM.L @SP+, (ERn-ERn+3) L L LDM.
Rev.6.00 Sep. 27, 2007 Page 1012 of 1268 REJ09B0220-0600 W L L L L L L L L L L L L L L MOV.W Rs,@aa:32 MOV.L #xx:32,Rd MOV.L ERs,ERd MOV.L @ERs,ERd MOV.L @(d:16,ERs),ERd MOV.L @(d:32,ERs),ERd MOV.L @ERs+,ERd MOV.L @aa:16 ,ERd MOV.L @aa:32 ,ERd MOV.L ERs,@ERd MOV.L ERs,@(d:16,ERd) MOV.L ERs,@(d:32,ERd)*1 MOV.L ERs,@-ERd MOV.L ERs,@aa:16 MOV.L ERs,@aa:32 MULXU B W MULXU.B Rs,Rd MULXU.W Rs,ERd B W MOV.W Rs,@aa:16 W W MOV.W Rs,@-ERd MULXS.W Rs,ERd W MOV.W Rs,@(d:32,ERd) B W MOV.
ROTL PUSH POP ORC 1 1 1 1 1 B W W L L ROTL.B #2, Rd ROTL.W Rd ROTL.W #2, Rd ROTL.L ERd ROTL.L #2, ERd 1 0 L B PUSH.L ERn ROTL.B Rd 6 0 L W POP.L ERn PUSH.W Rn 6 W POP.W Rn 0 0 L OR.L ERs,ERd 0 7 L OR.L #xx:32,ERd B 6 W OR.W Rs,Rd B 7 W OR.W #xx:16,Rd ORC #xx:8,EXR 1 B ORC #xx:8,CCR C B OR.B Rs,Rd 1 L NOT.L ERd OR.B #xx:8,Rd 1 W NOT.W Rd OR 1 0 B — NOT.B Rd 1 L NEG.L ERd NOP 1 W NEG.
Rev.6.00 Sep. 27, 2007 Page 1014 of 1268 REJ09B0220-0600 B SHAL.B Rd B W W L L SHAL.B #2, Rd SHAL.W Rd SHAL.W #2, Rd SHAL.L ERd SHAL.L #2, ERd — SHAL L ROTXR.L #2, ERd RTS L ROTXR.L ERd RTS W ROTXR.W #2, Rd — W ROTXR.W Rd RTE B L ROTXL.L #2, ERd ROTXR.B #2, Rd L ROTXL.L ERd B W ROTXL.W #2, Rd ROTXR.B Rd W ROTXL.W Rd ROTR.L #2, ERd B L ROTR.L ERd ROTXL.B #2, Rd L ROTR.W #2, Rd B W ROTR.W Rd ROTXL.B Rd B W ROTR.B #2, Rd B Size ROTR.
W L SHLR.W #2, Rd SHLR.L ERd 0 0 0 0 0 0 W STC.W CCR,@(d:16,ERd) W STC.W EXR,@(d:16,ERd) W STC.W CCR,@(d:32,ERd) W STC.W EXR,@(d:32,ERd) W W W STC.W EXR,@ERd STC.W CCR,@-ERd STC.W EXR,@-ERd 0 0 0 B W STC.W CCR,@ERd 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 2 2 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1st byte STC.B EXR,Rd B STC.B CCR,Rd STC — SLEEP L W SHLR.W Rd SHLR.L #2, ERd B L SHLL.L #2, ERd SHLR.B #2, Rd L SHLL.
Rev.6.00 Sep. 27, 2007 Page 1016 of 1268 REJ09B0220-0600 L SUBS #4,ERd B B B W W L L TAS @ERd*2 TRAPA #x:2 XOR.B #xx:8,Rd XOR.B Rs,Rd XOR.W #xx:16,Rd XOR.W Rs,Rd XOR.L #xx:32,ERd XOR.L ERs,ERd TRAPA XOR — B SUBX Rs,Rd B L SUBX #xx:8,Rd L SUBS #2,ERd L SUBS #1,ERd L L STMAC MACL,ERd SUB.L ERs,ERd L STMAC MACH,ERd SUB.L #xx:32,ERd L STM.L (ERn-ERn+3), @-SP W L STM.L (ERn-ERn+2), @-SP SUB.W Rs,Rd L STM.L(ERn-ERn+1), @-SP W W STC.W EXR,@aa:32 SUB.W #xx:16,Rd W STC.
B B XORC #xx:8,EXR Size XORC #xx:8,CCR Mnemonic 0 0 1 5 1st byte 4 IMM 1 2nd byte 0 5 3rd byte IMM 4th byte 7th byte 8th byte 9th byte 10th byte General Register ER0 ER1 • • • ER7 Register Field 000 001 • • • 111 Address Register 32-Bit Register 0000 0001 • • • 0111 1000 1001 • • • 1111 R0 R1 • • • R7 E0 E1 • • • E7 General Register 16-Bit Register Register Field 0000 0001 • • • 0111 1000 1001 • • • 1111 Register Field R0H R1H • • • R7H R0L R1L • • • R7L General Register 8-Bi
Rev.6.00 Sep. 27, 2007 Page 1018 of 1268 REJ09B0220-0600 1 2 3 BL BHI BLS XOR BSR BCS AND RTE BNE AND 7 BST TRAPA BEQ MOV AND D E MOV OR XOR C CMP SUBX B F SUB ADD BVS 9 Table A.3(2) MOV Table A.3(2) A Note: * Cannot be used in the chip. 8 BVC MOV.B Table A.3(2) LDC BIST BXOR BAND BOR BLD BIXOR BIAND BIOR BILD OR RTS BCC XOR 6 ANDC ADDX BTST DIVXU OR 5 XORC 9 BCLR MULXU 4 ORC Table A.3(2) Table A.3(2) JMP BPL Table A.3(2) Table A.
1 LDM MOV INC ADDS DAA 01 0A 0B 0F BH 0 ROTXR 12 13 SUBS DAS BRA MOV MOV MOV 1B 1F 58 6A 79 7A ADD BCC AND AND XOR XOR OR SUB CMP BNE MAC* 6 OR BCS DEC EXTU INC 5 SUB Table * A.3(4) MOVFPE BLS ROTXR ROTXL SHLR SHLL STC 4 LDC CMP MOV Table A.3(4) ADD BHI NOT STM 3 BL 2nd byte BH BRN 2 Note: * Cannot be used in the chip.
Rev.6.00 Sep. 27, 2007 Page 1020 of 1268 REJ09B0220-0600 *1 *1 *2 7Faa7 BSET BSET BSET BSET MULXS 0 BNOT BNOT BNOT BNOT DIVXS 1 AL BCLR BCLR BCLR BCLR MULXS 2 BH 3 BTST BTST BTST BTST XOR 5 DH AND 6 DL 4th byte 7 BXOR BAND BLD BOR BIXOR BIAND BILD BIOR BST BIST BXOR BAND BLD BOR BIXOR BIAND BILD BIOR BST BIST OR 4 CL 3rd byte CH DIVXS BL 2nd byte Notes: 1. r is the register specification field. 2. aa is the absolute address specification.
EL AH BSET 0 BNOT BNOT 1 AL 1st byte BSET 1 0 BCLR 2 BH 3 3 6 DL 7 EH EL 5th byte 5 DH 6 DL 4th byte 7 EH EL 5th byte BOR BXOR BAND BLD BIOR BIXOR BIAND BILD BST BIST 4 CL 3rd byte CH BTST BL 5 DH 4th byte BOR BXOR BAND BLD BIOR BIXOR BIAND BILD BST BIST 4 CL 3rd byte CH BTST BL 2nd byte BCLR 2 BH 2nd byte Note: * aa is the absolute address specification. 6A38aaaaaaaa7* 6A38aaaaaaaa6* 6A30aaaaaaaa7* 6A30aaaaaaaa6* AHALBHBL ...
Appendix A Instruction Set A.4 Number of States Required for Instruction Execution The tables in this section can be used to calculate the number of states required for instruction execution by the CPU. Table A.5 indicates the number of instruction fetch, data read/write, and other cycles occurring in each instruction. Table A.4 indicates the number of states required for each cycle.
Appendix A Instruction Set Table A.
Appendix A Instruction Set Table A.5 Number of Cycles in Instruction Execution Branch Instruction Address Fetch Read Byte Stack Data Operation Access Word Data Access Internal Operation K M N Instruction Mnemonic I ADD ADD.B #xx:8,Rd 1 ADD.B Rs,Rd 1 ADD.W #xx:16,Rd 2 ADD.W Rs,Rd 1 ADD.L #xx:32,ERd 3 ADD.L ERs,ERd 1 ADDS ADDS #1/2/4,ERd 1 ADDX ADDX #xx:8,Rd 1 ADDX Rs,Rd 1 AND.B #xx:8,Rd 1 AND ANDC BAND Bcc AND.B Rs,Rd 1 AND.W #xx:16,Rd 2 AND.W Rs,Rd 1 AND.
Appendix A Instruction Set Branch Instruction Address Fetch Read Byte Stack Data Operation Access Word Data Access Internal Operation K M N Instruction Mnemonic I Bcc BVS d:8 2 BCLR BPL d:8 2 BMI d:8 2 BGE d:8 2 BLT d:8 2 BGT d:8 2 BLE d:8 2 J L BRA d:16 (BT d:16) 2 1 BRN d:16 (BF d:16) 2 1 BHI d:16 2 1 BLS d:16 2 1 BCC d:16 (BHS d:16) 2 1 BCS d:16 (BLO d:16) 2 1 BNE d:16 2 1 BEQ d:16 2 1 BVC d:16 2 1 BVS d:16 2 1 BPL d:16 2 1 BMI d:16 2 1 BGE
Appendix A Instruction Set Branch Instruction Address Fetch Read Byte Stack Data Operation Access Word Data Access Internal Operation K M N Instruction Mnemonic I BIAND BIAND #xx:3,Rd 1 BILD BIOR BIST BIXOR BLD J L BIAND #xx:3,@ERd 2 1 BIAND #xx:3,@aa:8 2 1 BIAND #xx:3,@aa:16 3 1 BIAND #xx:3,@aa:32 4 1 BILD #xx:3,Rd 1 BILD #xx:3,@ERd 2 1 BILD #xx:3,@aa:8 2 1 BILD #xx:3,@aa:16 3 1 BILD #xx:3,@aa:32 4 1 BIOR #xx:8,Rd 1 BIOR #xx:8,@ERd 2 1 BIOR #xx:8,@aa:8 2
Appendix A Instruction Set Branch Instruction Address Fetch Read Byte Stack Data Operation Access Word Data Access Internal Operation K M N Instruction Mnemonic I BNOT BNOT #xx:3,Rd 1 BOR BSET BSR BST J L BNOT #xx:3,@ERd 2 2 BNOT #xx:3,@aa:8 2 2 BNOT #xx:3,@aa:16 3 2 BNOT #xx:3,@aa:32 4 2 BNOT Rn,Rd 1 BNOT Rn,@ERd 2 2 BNOT Rn,@aa:8 2 2 BNOT Rn,@aa:16 3 2 BNOT Rn,@aa:32 4 2 BOR #xx:3,Rd 1 BOR #xx:3,@ERd 2 1 BOR #xx:3,@aa:8 2 1 BOR #xx:3,@aa:16 3 1 BOR #
Appendix A Instruction Set Branch Instruction Address Fetch Read Byte Stack Data Operation Access Word Data Access Internal Operation K M N Instruction Mnemonic I BTST BTST #xx:3,Rd 1 BXOR J BTST #xx:3,@ERd 2 1 BTST #xx:3,@aa:8 2 1 BTST #xx:3,@aa:16 3 1 BTST #xx:3,@aa:32 4 1 BTST Rn,Rd 1 BTST Rn,@ERd 2 2 1 BTST Rn,@aa:16 3 1 BTST Rn,@aa:32 4 1 BXOR #xx:3,Rd 1 BXOR #xx:3,@ERd 2 1 BXOR #xx:3,@aa:8 2 1 BXOR #xx:3,@aa:16 3 1 BXOR #xx:3,@aa:32 4 1 CLRMAC Canno
Appendix A Instruction Set Branch Instruction Address Fetch Read Byte Stack Data Operation Access Word Data Access Internal Operation K M N Instruction Mnemonic I EEPMOV EEPMOV.B 2 2n+2* EEPMOV.W 2 2n+2* EXTS EXTS.W Rd 1 EXTS.L ERd 1 EXTU EXTU.W Rd 1 EXTU.L ERd 1 INC INC.B Rd 1 INC.W #1/2,Rd 1 INC.
Appendix A Instruction Set Branch Instruction Address Fetch Read Word Data Access Internal Operation K M N Instruction Mnemonic I LDM LDM.L @SP+, (ERn-ERn+1) 2 4 1 LDM.L @SP+, (ERn-ERn+2) 2 6 1 LDM.L @SP+, (ERn-ERn+3) 2 8 1 LDMAC ERs,MACH Cannot be used in the chip LDMAC J Byte Stack Data Operation Access L LDMAC ERs,MACL MAC MAC @ERn+,@ERm+ Cannot be used in the chip MOV MOV.B #xx:8,Rd 1 MOV.B Rs,Rd 1 MOV.B @ERs,Rd 1 1 MOV.B @(d:16,ERs),Rd 2 1 MOV.
Appendix A Instruction Set Branch Instruction Address Fetch Read Byte Stack Data Operation Access Word Data Access Internal Operation K M N Instruction Mnemonic I MOV MOV.W Rs,@(d:16,ERd) 2 1 MOV.W Rs,@(d:32,ERd) 4 1 MOV.W Rs,@-ERd 1 1 MOV.W Rs,@aa:16 2 1 MOV.W Rs,@aa:32 3 1 MOV.L #xx:32,ERd 3 MOV.L ERs,ERd 1 J L MOV.L @ERs,ERd 2 2 MOV.L @(d:16,ERs),ERd 3 2 MOV.L @(d:32,ERs),ERd 5 2 MOV.L @ERs+,ERd 2 2 MOV.L @aa:16,ERd 3 2 MOV.L @aa:32,ERd 4 2 1 1 MOV.
Appendix A Instruction Set Branch Instruction Address Fetch Read Byte Stack Data Operation Access Word Data Access Internal Operation K M N 1 1 Instruction Mnemonic I OR OR.B #xx:8,Rd 1 OR.B Rs,Rd 1 OR.W #xx:16,Rd 2 OR.W Rs,Rd 1 OR.L #xx:32,ERd 3 ORC OR.L ERs,ERd 2 ORC #xx:8,CCR 1 J L ORC #xx:8,EXR 2 POP POP.W Rn 1 POP.L ERn 2 2 1 PUSH PUSH.W Rn 1 1 1 PUSH.L ERn 2 2 1 ROTL.B Rd 1 ROTL.B #2,Rd 1 ROTL.W Rd 1 ROTL ROTR ROTXL ROTL.W #2,Rd 1 ROTL.
Appendix A Instruction Set Branch Instruction Address Fetch Read Byte Stack Data Operation Access Word Data Access Internal Operation K M N Instruction Mnemonic I ROTXR ROTXR.B Rd 1 ROTXR.B #2,Rd 1 ROTXR.W Rd 1 ROTXR.W #2,Rd 1 ROTXR.L ERd 1 J L ROTXR.L #2,ERd 1 RTE RTE 2 2/3* 1 RTS RTS 2 2 1 SHAL SHAL.B Rd 1 SHAL.B #2,Rd 1 SHAL.W Rd 1 SHAR SHLL SHLR SLEEP Advanced SHAL.W #2,Rd 1 SHAL.L ERd 1 SHAL.L #2,ERd 1 SHAR.B Rd 1 SHAR.B #2,Rd 1 SHAR.
Appendix A Instruction Set Branch Instruction Address Fetch Read Byte Stack Data Operation Access Word Data Access Internal Operation K M N Instruction Mnemonic I STC STC.B CCR,Rd 1 STC.B EXR,Rd 1 STC.W CCR,@ERd 2 STC.W EXR,@ERd J L 1 2 1 STC.W CCR,@(d:16,ERd) 3 1 STC.W EXR,@(d:16,ERd) 3 1 STC.W CCR,@(d:32,ERd) 5 1 STC.W EXR,@(d:32,ERd) 5 1 STC.W CCR,@-ERd 2 1 1 STC.W EXR,@-ERd 2 1 1 STC.W CCR,@aa:16 3 1 STC.W EXR,@aa:16 3 1 STC.W CCR,@aa:32 4 1 STC.
Appendix A Instruction Set Branch Instruction Address Fetch Read Byte Stack Data Operation Access Word Data Access Internal Operation K M N Instruction Mnemonic I XOR XOR.B #xx:8,Rd 1 XORC XOR.B Rs,Rd 1 XOR.W #xx:16,Rd 2 XOR.W Rs,Rd 1 XOR.L #xx:32,ERd 3 XOR.L ERs,ERd 2 XORC #xx:8,CCR 1 XORC #xx:8,EXR 2 J L Notes: 1. 2 when EXR is invalid, 3 when EXR is valid. 2. When n bytes of data are transferred. 3.
Appendix A Instruction Set A.5 Bus States during Instruction Execution Table A.6 indicates the types of cycles that occur during instruction execution by the CPU. See table A.4 for the number of states per cycle.
Appendix A Instruction Set Figure A.1 shows timing waveforms for the address bus and the RD, HWR, and LWR signals during execution of the above instruction with an 8-bit bus, using three-state access with no wait states. φ Address bus RD HWR, LWR High R:W 2nd Fetching 3rd byte of instruction Fetching 4th byte of instruction Internal operation R:W EA Fetching 1st byte of instruction at jump address Fetching 2nd byte of instruction at jump address Figure A.
Instruction ADD.B #xx:8,Rd ADD.B Rs,Rd ADD.W #xx:16,Rd ADD.W Rs,Rd ADD.L #xx:32,ERd ADD.L ERs,ERd ADDS #1/2/4,ERd ADDX #xx:8,Rd ADDX Rs,Rd AND.B #xx:8,Rd AND.B Rs,Rd AND.W #xx:16,Rd AND.W Rs,Rd AND.L #xx:32,ERd AND.
1 R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd Instruction BLE d:8 BRA d:16 (BT d:16) BRN d:16 (BF d:16) BHI d:16 BLS d:16 BCC d:16 (BHS d:16) BCS d:16 (BLO d:16) BNE d:16 BEQ d:16 BVC d:16 BVS d:16 BPL d:16 BMI d:16 BGE d:16 BLT d:16 BGT d:16 BLE d:16 BCLR #xx:3,Rd BCLR #xx:3,@ERd BCLR #xx:3,@aa:8 BCLR #xx:3,@aa:16 R:B:M EA R:B:M EA R:W 3rd 2 R:W EA
Instruction BCLR #xx:3,@aa:32 BCLR Rn,Rd BCLR Rn,@ERd BCLR Rn,@aa:8 BCLR Rn,@aa:16 BCLR Rn,@aa:32 BIAND #xx:3,Rd BIAND #xx:3,@ERd BIAND #xx:3,@aa:8 BIAND #xx:3,@aa:16 BIAND #xx:3,@aa:32 BILD #xx:3,Rd BILD #xx:3,@ERd BILD #xx:3,@aa:8 BILD #xx:3,@aa:16 BILD #xx:3,@aa:32 BIOR #xx:3,Rd BIOR #xx:3,@ERd BIOR #xx:3,@aa:8 BIOR #xx:3,@aa:16 BIOR #xx:3,@aa:32 BIST #xx:3,Rd BIST #xx:3,@ERd BIST #xx:3,@aa:8 BIST #xx:3,@aa:16 BIST #xx:3,@aa:32 BIXOR #xx:3,Rd BIXOR #xx:3,@ERd BIXOR #xx:3,@aa:8 BIXOR #xx:3,@aa:16 BIXOR #x
1 R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd Instruction BNOT #xx:3,@ERd BNOT #xx:3,@aa:8 BNOT #xx:3,@aa:16 BNOT #xx:3,@aa:32 BNOT Rn,Rd BNOT Rn,@ERd BNOT Rn,@aa:8 BNOT Rn,@aa:16 BNOT Rn,@aa:32 BOR #xx:3,Rd BOR #xx:3,@ERd BOR #xx:3,@aa:8 BOR #xx:3,@aa:16 BOR #xx:3,@aa:32 BSET #xx:3
R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT CMP.B #xx:8,Rd CMP.B Rs,Rd CMP.W #xx:16,Rd CMP.W Rs,Rd CMP.L #xx:32,ERd CMP.L ERs,ERd DAA Rd DAS Rd DEC.B Rd DEC.W #1/2,Rd DEC.L #1/2,ERd DIVXS.B Rs,Rd DIVXS.W Rs,ERd DIVXU.B Rs,Rd DIVXU.W Rs,ERd EEPMOV.B EEPMOV.W EXTS.W Rd EXTS.L ERd EXTU.W Rd EXTU.L ERd INC.B Rd Rev.6.00 Sep.
1 R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd R:W 2nd LDC @ERs+,EXR LDC @aa:16,CCR LDC @aa:16,EXR LDC @aa:32,CCR LDC @aa:32,EXR LDM.
R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT MAC @ERn+,@ERm+ MOV.B #xx:8,Rd MOV.B Rs,Rd MOV.B @ERs,Rd MOV.B @(d:16,ERs),Rd MOV.B @(d:32,ERs),Rd MOV.B @ERs+,Rd MOV.B @aa:8,Rd MOV.B @aa:16,Rd MOV.B @aa:32,Rd MOV.B Rs,@ERd MOV.B Rs,@(d:16,ERd) MOV.B Rs,@(d:32,ERd) MOV.B Rs,@–ERd MOV.B Rs,@aa:8 MOV.B Rs,@aa:16 MOV.B Rs,@aa:32 MOV.
MOV.L ERs,@aa:16 MOV.L ERs,@aa:32 MOVFPE @aa:16,Rd MOVTPE Rs,@aa:16 MULXS.B Rs,Rd MULXS.W Rs,ERd MULXU.B Rs,Rd MULXU.W Rs,ERd NEG.B Rd NEG.W Rd NEG.L ERd NOP NOT.B Rd NOT.W Rd NOT.L ERd OR.B #xx:8,Rd OR.B Rs,Rd MOV.L @aa:16,ERd MOV.L @aa:32,ERd MOV.L ERs,@ERd MOV.L ERs,@(d:16,ERd) MOV.L ERs,@(d:32,ERd) MOV.L ERs,@–ERd R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W 2nd MOV.W Rs,@aa:16 MOV.W Rs,@aa:32 MOV.L #xx:32,ERd MOV.L ERs,ERd MOV.L @ERs,ERd MOV.L @(d:16,ERs),ERd MOV.
1 R:W 2nd R:W NEXT R:W 2nd R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT Instruction OR.W #xx:16,Rd OR.W Rs,Rd OR.L #xx:32,ERd OR.L ERs,ERd ORC #xx:8,CCR ORC #xx:8,EXR POP.W Rn POP.L ERn PUSH.W Rn PUSH.L ERn ROTL.B Rd ROTL.B #2,Rd ROTL.W Rd ROTL.W #2,Rd ROTL.L ERd ROTL.
R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W 2nd R:W 2nd R:W NEXT R:W NEXT R:W 3rd Internal operation:M W:W EA W:W EA R:W NEXT R:W:M stack (H) R:W stack (L) Advanced R:W NEXT SHAL.B Rd SHAL.B #2,Rd SHAL.W Rd SHAL.W #2,Rd SHAL.L ERd SHAL.L #2,ERd SHAR.B Rd SHAR.B #2,Rd SHAR.W Rd SHAR.W #2,Rd SHAR.
R:W NEXT R:W 2nd R:W NEXT R:W 2nd R:W NEXT R:W NEXT R:W NEXT R:W NEXT R:W 2nd R:W NEXT Rev.6.00 Sep. 27, 2007 Page 1048 of 1268 REJ09B0220-0600 R:W NEXT R:W NEXT R:W 2nd R:W NEXT R:W 2nd XOR.B #xx8,Rd XOR.B Rs,Rd XOR.W #xx:16,Rd XOR.W Rs,Rd XOR.
R:W*6 1 R:W 2nd R:W NEXT R:W 2nd R:W VEC 3 4 Internal operation, R:W*5 1 state Internal operation, W:W stack (L) W:W stack (H) 1 state R:W NEXT R:W VEC+2 2 R:W NEXT W:W stack (EXR) 5 R:W:M VEC 6 R:W VEC+2 7 9 Internal operation, R:W*7 1 state 8 Notes: 1. EAs is the contents of ER5. EAd is the contents of ER6. 2. EAs is the contents of ER5. EAd is the contents of ER6. Both registers are incremented by 1 after execution of the instruction. n is the initial value of R4L or R4.
Appendix A Instruction Set A.6 Condition Code Modification This section indicates the effect of each CPU instruction on the condition code. The notation used in the table is defined below.
Appendix A Instruction Set Table A.7 Instruction Condition Code Modification H N Z V C Definition H = Sm–4 · Dm–4 + Dm–4 · Rm–4 + Sm–4 · Rm–4 ADD N = Rm Z = Rm · Rm–1 · ...... · R0 V = Sm · Dm · Rm + Sm · Dm · Rm C = Sm · Dm + Dm · Rm + Sm · Rm ADDS — — — — — H = Sm–4 · Dm–4 + Dm–4 · Rm–4 + Sm–4 · Rm–4 ADDX N = Rm Z = Z' · Rm · ...... · R0 V = Sm · Dm · Rm + Sm · Dm · Rm C = Sm · Dm + Dm · Rm + Sm · Rm AND — 0 — N = Rm Z = Rm · Rm–1 · ......
Appendix A Instruction Set Instruction H N Z V C Definition CLRMAC Cannot be used in the chip CMP H = Sm–4 · Dm–4 + Dm–4 · Rm–4 + Sm–4 · Rm–4 N = Rm Z = Rm · Rm–1 · ...... · R0 V = Sm · Dm · Rm + Sm · Dm · Rm C = Sm · Dm + Dm · Rm + Sm · Rm DAA * N = Rm * Z = Rm · Rm–1 · ...... · R0 C: decimal arithmetic carry DAS * N = Rm * Z = Rm · Rm–1 · ...... · R0 C: decimal arithmetic borrow DEC — — N = Rm Z = Rm · Rm–1 · ......
Appendix A Instruction Set Instruction H MOV — N Z V C Definition 0 — N = Rm Z = Rm · Rm–1 · ...... · R0 MOVFPE Cannot be used in the chip MOVTPE MULXS — — — N = R2m Z = R2m · R2m–1 · ...... · R0 MULXU — — — — — NEG H = Dm–4 + Rm–4 N = Rm Z = Rm · Rm–1 · ...... · R0 V = Dm · Rm C = Dm + Rm NOP — — — — — NOT — 0 — N = Rm Z = Rm · Rm–1 · ...... · R0 OR — 0 — N = Rm Z = Rm · Rm–1 · ...... · R0 ORC Stores the corresponding bits of the result.
Appendix A Instruction Set Instruction H ROTXL — N Z V C 0 Definition N = Rm Z = Rm · Rm–1 · ...... · R0 C = Dm (1-bit shift) or C = Dm–1 (2-bit shift) ROTXR — 0 N = Rm Z = Rm · Rm–1 · ...... · R0 C = D0 (1-bit shift) or C = D1 (2-bit shift) RTE Stores the corresponding bits of the result. RTS — — — — — SHAL — N = Rm Z = Rm · Rm–1 · ......
Appendix A Instruction Set Instruction H N Z V C Definition H = Sm–4 · Dm–4 + Dm–4 · Rm–4 + Sm–4 · Rm–4 SUB N = Rm Z = Rm · Rm–1 · ...... · R0 V = Sm · Dm · Rm + Sm · Dm · Rm C = Sm · Dm + Dm · Rm + Sm · Rm SUBS — — — — — H = Sm–4 · Dm–4 + Dm–4 · Rm–4 + Sm–4 · Rm–4 SUBX N = Rm Z = Z' · Rm · ...... · R0 V = Sm · Dm · Rm + Sm · Dm · Rm C = Sm · Dm + Dm · Rm + Sm · Rm TAS — 0 — N = Dm Z = Dm · Dm–1 · ...... · D0 TRAPA — — — — — XOR — 0 — N = Rm Z = Rm · Rm–1 · ......
Appendix B Internal I/O Registers Appendix B Internal I/O Registers B.
Appendix B Internal I/O Registers Bit 0 Module Name Data Bus Width TPSC0 TPU4 16 bits TPU5 16 bits Address Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 H'FE90 TCR4 — CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 H'FE91 TMDR4 — — — — MD3 MD2 MD1 MD0 H'FE92 TIOR4 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 H'FE94 TIER4 TTGE — TCIEU TCIEV — — TGIEB TGIEA H'FE95 TSR4 TCFD — TCFU TCFV — — TGFB TGFA H'FE96 TCNT4 H'FE97 H'FE98 TGR4A H'FE99 H'FE9A
Appendix B Internal I/O Registers Address Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H'FEC4 IPRA — IPR6 IPR5 IPR4 — IPR2 IPR1 IPR0 H'FEC5 IPRB — IPR6 IPR5 IPR4 — IPR2 IPR1 IPR0 H'FEC6 IPRC — IPR6 IPR5 IPR4 — IPR2 IPR1 IPR0 H'FEC7 IPRD — IPR6 IPR5 IPR4 — IPR2 IPR1 IPR0 H'FEC8 IPRE — IPR6 IPR5 I PR4 — IPR2 IPR1 IPR0 H'FEC9 IPRF — IPR6 IPR5 IPR4 — IPR2 IPR1 IPR0 H'FECA IPRG — IPR6 IPR5 IPR4 — IPR2 IPR1 IPR0 H'FE
Appendix B Internal I/O Registers Data Bus Width Address Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module Name H'FEF0 MAR1AH — — — — — — — — DMAC* — — — — — — — — H'FF00 DMAWER — — — — WE1B WE1A WE0B WE0A H'FF01 DMATCR — TEE1 TEE0 — — — — H'FF02 DMACR0A DTSZ DTID RPE DTDIR DTF3 DTF2 DTF1 DTF0 Short address mode DTSZ SAID SAIDE BLKDIR BLKE — — — Full address mode DMACR0B DTSZ DTID RPE DTDIR DTF3 DTF2 DTF1 DTF0 Sho
Appendix B Internal I/O Registers Address Register Name Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 H'FF06 DMABCRH FAE1 FAE0 SAE1 SAE0 DTA1B DTA1A DTA0B DTA0A Short address mode FAE1 FAE0 — — DTA1 — DTA0 — Full address mode DTE1A DTE0B DTE0A DTIE1B DTIE1A DTIE0B DTIE0A Short address mode DTE1 DTME0 DTE0 DTIE1B DTIE1A DTIE0B DTIE0A Full address mode H'FF07 Bit 7 DMABCRL DTE1B DTME1 H'FF2C ISCRH H'FF2D ISCRL Module Name Data Bus Width IRQ7SCB IRQ7SCA IRQ6SC
Appendix B Internal I/O Registers Bit 0 Module Name Data Bus Width P10 Ports 8 bits Address Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 H'FF50 PORT1 P17 P16 P15 P14 P13 P12 P11 H'FF51 PORT2 P27 P26 P25 P24 P23 P22 P21 P20 H'FF52 PORT3 — — P35 P34 P33 P32 P31 P30 H'FF53 PORT4 P47 P46 P45 P44 P43 P42 P41 P40 H'FF54 PORT5 — — — — P53 P52 P51 P50 H'FF55 PORT6 P67 P66 P65 P64 P63 P62 P61 P60 H'FF59 PORTA PA7 PA6 PA5 PA4
Appendix B Internal I/O Registers Address Register Name H'FF78 SMR0 H'FF79 BRR0 H'FF7A SCR0 H'FF7B TDR0 H'FF7C SSR0 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 C/A/ 7 GM* CHR/ 8 BLK* PE O/E STOP/ MP/ CKS1 9 10 BCP1* BCP0* Bit 2 Bit 1 Bit 0 CKS0 TIE RIE TE RE MPIE TEIE CKE1 CKE0 TDRE RDRF ORER FER/ ERS*11 PER TEND MPB MPBT SINV — SMIF H'FF7D RDR0 H'FF7E SCMR0 — — — — SDIR H'FF80 SMR1 C/A/ GM*7 CHR/ BLK*8 PE O/E STOP/ MP/ CKS1 BCP1*9 BCP0*10 CKS0 H'FF81 BRR1 TI
Appendix B Internal I/O Registers Bit 0 Module Name Data Bus Width — Ports 8 bits CKS0 8-bit timer channel 0, 1 16 bits WDT 16 bits TPU 16 bits Address Register Name Bit 7 Bit 3 Bit 2 Bit 1 H'FFAC PFCR2 WAITPS BREQOPS CS167E CS25E ASOD — — H'FFB0 TCR0 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 H'FFB1 TCR1 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 H'FFB2 TCSR0 CMFB CMFA OVF ADTE OS3 OS2 OS1 OS0 H'FFB3 TCSR1 CMFB CMFA OVF — OS3 OS2 OS1 OS0 H'FFB4
Appendix B Internal I/O Registers Bit 0 Module Name Data Bus Width TPSC0 TPU0 16 bits TPU1 16 bits TPU2 16 bits Address Register Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 H'FFD0 TCR0 CCLR2 CCLR1 CCLR0 CKEG1 CKEG0 TPSC2 TPSC1 H'FFD1 TMDR0 — — BFB BFA MD3 MD2 MD1 MD0 H'FFD2 TIOR0H IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 H'FFD3 TIOR0L IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0 H'FFD4 TIER0 TTGE — — TCIEV TGIED TGIEC TGIEB TGIEA H'FFD5 TSR0
Appendix B Internal I/O Registers 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. Reserved bit in the H8S/2321. Reserved in the H8S/2321. Valid only in F-ZTAT versions. The DMAC is not supported in the H8S/2321. If the pulse output group 2 and pulse output group 3 output triggers are the same according to the PCR setting, the NDRH address will be H'FF4C, and if different, the address of NDRH for group 2 will be H'FF4E, and that for group 3 will be H'FF4C.
Appendix B Internal I/O Registers B.
Appendix B Internal I/O Registers Module Register Abbreviation R/W DTC DTC mode register A MRA DTC mode register B DMAC0 7 DMAC1* 3 1 Initial Value Address* 4 —* 4 —* Undefined MRB —* 3 —* DTC source address register SAR 3 —* Undefined DTC destination address register DAR 3 Undefined DTC transfer count register A CRA —* 3 —* DTC transfer count register B CRB —* 3 Undefined DTC enable register DTCER R/W H'00 H'FF30 to H'FF35 DTC vector register DTVECR R/W H'00 H'FF37
Appendix B Internal I/O Registers 1 Module Register Abbreviation R/W Initial Value Address* TPU0 Timer control register 0 TCR0 R/W H'00 H'FFD0 Timer mode register 0 TMDR0 R/W H'C0 H'FFD1 Timer I/O control register 0H TIOR0H R/W H'00 H'FFD2 Timer I/O control register 0L TIOR0L R/W H'00 H'FFD3 Timer interrupt enable register 0 TIER0 R/W H'FFD4 Timer status register 0 TSR0 H'40 2 * R/(W) H'C0 Timer counter 0 TCNT0 R/W H'FFD6 TPU1 TPU2 H'0000 H'FFD5 Timer general registe
Appendix B Internal I/O Registers 1 Module Register Abbreviation R/W Initial Value Address* TPU3 Timer control register 3 TCR3 R/W H'00 H'FE80 Timer mode register 3 TMDR3 R/W H'C0 H'FE81 Timer I/O control register 3H TIOR3H R/W H'00 H'FE82 Timer I/O control register 3L TIOR3L R/W H'00 H'FE83 Timer interrupt enable register 3 TIER3 R/W H'FE84 Timer status register 3 TSR3 H'40 2 * R/(W) H'C0 Timer counter 3 TCNT3 R/W H'0000 H'FE86 TPU4 TPU5 ALL TPU channels H'FE85 Tim
Appendix B Internal I/O Registers 1 Module Register Abbreviation R/W Initial Value Address* PPG PPG output control register PCR R/W H'FF H'FF46 PPG output mode register PMR R/W H'F0 H'FF47 8-bit timer 0 8-bit timer 1 Both 8-bit timer channels Next data enable register H NDERH R/W H'00 H'FF48 Next data enable register L NDERL R/W H'00 H'FF49 Output data register H PODRH H'FF4A Output data register L PODRL R/(W)* H'00 8 R/(W)* H'00 Next data register H NDRH R/W H'00 Next
Appendix B Internal I/O Registers Module Register Abbreviation R/W WDT Timer control/status register TCSR 1 Initial Value Address* 12 R/(W)* H'18 H'FFBC: 11 Write* H'FFBC: Read Timer counter TCNT R/W H'00 H'FFBC: 8 Write* H'FFBD: Read Reset control/status register RSTCSR 12 R/(W)* H'1F H'FFBE: 11 Write* H'FFBF: Read SCI0 SCI1 SCI2 Serial mode register 0 SMR0 R/W H'00 H'FF78 Bit rate register 0 BRR0 R/W H'FF H'FF79 Serial control register 0 SCR0 R/W H'00 H'FF7A Transmit
Appendix B Internal I/O Registers 1 Module Register Abbreviation R/W Initial Value Address* All SCI channels Module stop control register MSTPCR R/W H'3FFF H'FF3C SMCI0 Serial mode register 0 SMR0 R/W H'00 H'FF78 Bit rate register 0 BRR0 R/W H'FF H'FF79 Serial control register 0 SCR0 R/W H'00 H'FF7A Transmit data register 0 TDR0 R/W H'FF7B Serial status register 0 SSR0 H'FF 2 * R/(W) H'84 SMCI1 SMCI2 All SMCI channels H'FF7C Receive data register 0 RDR0 R H'00 H'FF7
Appendix B Internal I/O Registers 1 Module Register Abbreviation R/W Initial Value Address* ADC A/D data register AH ADDRAH R H'00 H'FF90 A/D data register AL ADDRAL R H'00 H'FF91 A/D data register BH ADDRBH R H'00 H'FF92 A/D data register BL ADDRBL R H'00 H'FF93 A/D data register CH ADDRCH R H'00 H'FF94 A/D data register CL ADDRCL R H'00 H'FF95 A/D data register DH ADDRDH R H'00 H'FF96 A/D data register DL ADDRDL R H'00 H'FF97 A/D control/status register ADCSR
Appendix B Internal I/O Registers 1 Module Register Abbreviation R/W Initial Value Address* Port 1 Port 1 data direction register P1DDR W H'00 H'FEB0 Port 1 data register P1DR R/W H'00 H'FF60 Port 1 register PORT1 R Undefined H'FF50 Port 2 data direction register P2DDR W H'00 H'FEB1 Port 2 data register P2DR R/W H'00 H'FF61 Port 2 register PORT2 R Undefined H'FF51 Port 3 data direction register P3DDR W H'00 H'FEB2 Port 3 data register P3DR R/W H'00 H'FF62 Port 3
Appendix B Internal I/O Registers 1 Module Register Abbreviation R/W Initial Value Address* Port C Port C data direction register PCDDR W H'00 H'FEBB Port C data register PCDR R/W H'00 H'FF6B Port C register PORTC Port D Port E Port F Port G Notes: 1. 2. 3. 4. 5. 6. 7. 8.
Appendix B Internal I/O Registers 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. If the pulse output group 2 and pulse output group 3 output triggers are the same according to the PCR setting, the NDRH address will be H'FF4C, and if different, the address of NDRH for group 2 will be H'FF4E, and that for group 3 will be H'FF4C.
Appendix B Internal I/O Registers B.
Appendix B Internal I/O Registers MRB—DTC Mode Register B Bit DTC 7 6 5 4 3 2 1 0 CHNE DISEL CHNS — — — — — : Initial value : H'F800—H'FBFF Undefined Undefined Undefined Undefined Undefined Undefined Undefined Undefined Read/Write : — — — — — — — — Reserved Only 0 should be written to these bits DTC Chain Transfer Select DTC Interrupt Select 0 After DTC data transfer ends, the CPU interrupt is disabled unless the transfer counter is 0 1 After DTC data transfer ends, the CP
Appendix B Internal I/O Registers CRA—DTC Transfer Count Register A Bit : Initial value : Read/Write : 15 14 13 12 11 H'F800—H'FBFF 10 9 8 7 6 5 4 DTC 3 2 1 0 Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Unde- Undefined fined fined fined fined fined fined fined fined fined fined fined fined fined fined fined — — — — — — — — — — — CRAH — — — — — CRAL Specifies the number of DTC data transfers CRB—DTC Transfer Count Register B Bit
Appendix B Internal I/O Registers TCR3—Timer Control Register 3 Bit : 7 6 5 CCLR2 CCLR1 CCLR0 H'FE80 4 3 CKEG1 CKEG0 TPU3 2 1 0 TPSC2 TPSC1 TPSC0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Timer Prescaler 0 0 1 1 0 1 0 Internal clock: counts on φ/1 1 Internal clock: counts on φ/4 0 Internal clock: counts on φ/16 1 Internal clock: counts on φ/64 0 External clock: counts on TCLKA pin input 1 Internal clock: counts on φ/102
Appendix B Internal I/O Registers TMDR3—Timer Mode Register 3 Bit : H'FE81 TPU3 7 6 5 4 3 2 1 0 MD0 — — BFB BFA MD3 MD2 MD1 Initial value : 1 1 0 0 0 0 0 0 Read/Write : — — R/W R/W R/W R/W R/W R/W Mode 0 0 0 1 1 0 1 1 * * 0 Normal operation 1 Reserved 0 PWM mode 1 1 PWM mode 2 0 Phase counting mode 1 1 Phase counting mode 2 0 Phase counting mode 3 1 Phase counting mode 4 * — * : Don’t care Notes: 1. MD3 is a reserved bit.
Appendix B Internal I/O Registers TIOR3H—Timer I/O Control Register 3H H'FE82 TPU3 7 6 5 4 3 2 1 0 Initial value : IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Bit : TGR3A I/O Control 0 0 0 0 1 1 0 TGR3A Output disabled is output compare Initial output is register 0 output 1 1 0 1 Toggle output at compare match 0 Output disabled 1 Initial output is 1 output 0 1 1 0 0 0 1 1 1 * * * 0 outpu
Appendix B Internal I/O Registers TIOR3L—Timer I/O Control Register 3L Bit H'FE83 TPU3 7 6 5 4 3 2 1 0 IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0 : Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W TGR3C I/O Control 0 0 0 1 1 0 1 1 0 1 0 TGR3C Output disabled is output 1 compare Initial output is 1 0 output 0 register* 1 output at compare match 1 Toggle output at compare match 0 Output disabled 1 Initial output is 1 output 0 0
Appendix B Internal I/O Registers TIER3—Timer Interrupt Enable Register 3 Bit : H'FE84 TPU3 7 6 5 4 3 2 1 0 TTGE — — TCIEV TGIED TGIEC TGIEB TGIEA Initial value : 0 1 0 0 0 0 0 0 Read/Write : R/W — — R/W R/W R/W R/W R/W TGR Interrupt Enable A 0 Interrupt request (TGIA) by TGFA bit disabled 1 Interrupt request (TGIA) by TGFA bit enabled TGR Interrupt Enable B 0 Interrupt request (TGIB) by TGFB bit disabled 1 Interrupt request (TGIB) by TGFB bit enabled TGR Inter
Appendix B Internal I/O Registers TSR3—Timer Status Register 3 Bit : H'FE85 TPU3 7 6 5 4 3 2 1 0 — — — TCFV TGFD TGFC TGFB TGFA Initial value : 1 1 0 0 0 0 0 0 Read/Write : — — — R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Input Capture/Output Compare Flag A 0 [Clearing conditions] • When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 • When DMAC is activated by TGIA interrupt while DTA bit of DMABCR in DMAC*1 is 1 • When 0 is written to TGFA after readi
Appendix B Internal I/O Registers TCNT3—Timer Counter 3 Bit : Initial value : Read/Write : H'FE86 TPU3 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Up-counter TGR3A—Timer General Register 3A TGR3B—Timer General Register 3B TGR3C—Timer General Register 3C TGR3D—Timer General Register 3D Bit H'FE88 H'FE8A H'FE8C H'FE8E TPU3 TPU3 TPU3 TPU3 : 15 14 13 12 11 10 9 8 7 6 5
Appendix B Internal I/O Registers TCR4—Timer Control Register 4 Bit : 7 6 5 — CCLR1 CCLR0 H'FE90 4 3 CKEG1 CKEG0 TPU4 2 1 0 TPSC2 TPSC1 TPSC0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : — R/W R/W R/W R/W R/W R/W R/W Timer Prescaler 0 0 1 1 0 1 0 Internal clock: counts on φ/1 1 Internal clock: counts on φ/4 0 Internal clock: counts on φ/16 1 Internal clock: counts on φ/64 0 External clock: counts on TCLKA pin input 1 External clock: counts on TCLKC pin i
Appendix B Internal I/O Registers TMDR4—Timer Mode Register 4 Bit : H'FE91 TPU4 7 6 5 4 3 2 1 0 — — — — MD3 MD2 MD1 MD0 Initial value : 1 1 0 0 0 0 0 0 Read/Write : — — — — R/W R/W R/W R/W Mode 0 0 0 1 1 0 1 1 * * 0 Normal operation 1 Reserved 0 PWM mode 1 1 PWM mode 2 0 Phase counting mode 1 1 Phase counting mode 2 0 Phase counting mode 3 1 Phase counting mode 4 * — * : Don’t care Note: MD3 is a reserved bit.
Appendix B Internal I/O Registers TIOR4—Timer I/O Control Register 4 Bit H'FE92 TPU4 7 6 5 4 3 2 1 0 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 : Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W TGR4A I/O Control 0 0 0 1 1 0 1 0 TGR4A Output disabled is output 1 compare Initial output is 0 output 0 register 0 output at compare match 1 Toggle output at compare match 0 Output disabled 1 Initial output is 1 output 0 1 1 0 0 0 1
Appendix B Internal I/O Registers TIER4—Timer Interrupt Enable Register 4 Bit : H'FE94 TPU4 7 6 5 4 3 2 1 0 TTGE — TCIEU TCIEV — — TGIEB TGIEA Initial value : 0 1 0 0 0 0 0 0 Read/Write : R/W — R/W R/W — — R/W R/W TGR Interrupt Enable A 0 Interrupt request (TGIA) by TGFA bit disabled 1 Interrupt request (TGIA) by TGFA bit enabled TGR Interrupt Enable B 0 Interrupt request (TGIB) by TGFB bit disabled 1 Interrupt request (TGIB) by TGFB bit enabled Overflow Interru
Appendix B Internal I/O Registers TSR4—Timer Status Register 4 Bit : H'FE95 7 6 5 4 3 2 1 0 TCFD — TCFU TCFV — — TGFB TGFA Initial value : 1 1 0 0 0 0 0 0 Read/Write : R — R/(W)* R/(W)* — — R/(W)* R/(W)* TPU4 Input Capture/Output Compare Flag A 0 [Clearing conditions] • When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 • When DMAC is activated by TGIA interrupt while DTA bit of DMABCR in DMAC*1 is 1 • When 0 is written to TGFA after reading TG
Appendix B Internal I/O Registers TCNT4—Timer Counter 4 Bit H'FE96 TPU4 : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Up/down-counter* Note: * This timer counter can be used as an up/down-counter only in phase counting mode or when performing overflow/underflow counting on another channel. In other cases it functions as an up-counter.
Appendix B Internal I/O Registers TCR5—Timer Control Register 5 Bit : 7 6 5 — CCLR1 CCLR0 H'FEA0 4 3 CKEG1 CKEG0 TPU5 2 1 0 TPSC2 TPSC1 TPSC0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : — R/W R/W R/W R/W R/W R/W R/W Time Prescaler 0 0 1 1 0 1 0 Internal clock: counts on φ/1 1 Internal clock: counts on φ/4 0 Internal clock: counts on φ/16 1 Internal clock: counts on φ/64 0 External clock: counts on TCLKA pin input 1 External clock: counts on TCLKC pin in
Appendix B Internal I/O Registers TMDR5—Timer Mode Register 5 Bit : H'FEA1 TPU5 7 6 5 4 3 2 1 0 MD0 — — — — MD3 MD2 MD1 Initial value : 1 1 0 0 0 0 0 0 Read/Write : — — — — R/W R/W R/W R/W Mode 0 0 0 1 1 0 1 1 * * 0 Normal operation 1 Reserved 0 PWM mode 1 1 PWM mode 2 0 Phase counting mode 1 1 Phase counting mode 2 0 Phase counting mode 3 1 Phase counting mode 4 * — * : Don’t care Note: MD3 is a reserved bit.
Appendix B Internal I/O Registers TIOR5—Timer I/O Control Register 5 Bit H'FEA2 TPU5 7 6 5 4 3 2 1 0 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 : Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W TGR5A I/O Control 0 0 0 1 1 0 1 0 TGR5A Output disabled is output 1 compare Initial output is 0 output 0 register 1 output at compare match 1 Toggle output at compare match 0 Output disabled 1 Initial output is 1 output 0 1 1 * 0 1 0
Appendix B Internal I/O Registers TIER5—Timer Interrupt Enable Register 5 Bit : H'FEA4 TPU5 7 6 5 4 3 2 1 0 TTGE — TCIEU TCIEV — — TGIEB TGIEA Initial value : 0 1 0 0 0 0 0 0 Read/Write : R/W — R/W R/W — — R/W R/W TGR Interrupt Enable A 0 Interrupt request (TGIA) by TGFA bit disabled 1 Interrupt request (TGIA) by TGFA bit enabled TGR Interrupt Enable B 0 Interrupt request (TGIB) by TGFB bit disabled 1 Interrupt request (TGIB) by TGFB bit enabled Overflow Interru
Appendix B Internal I/O Registers TSR5—Timer Status Register 5 Bit : H'FEA5 7 6 5 4 3 2 1 0 TCFD — TCFU TCFV — — TGFB TGFA Initial value : 1 1 0 0 0 0 0 0 Read/Write : R — R/(W)* R/(W)* — — R/(W)* R/(W)* TPU5 Input Capture/Output Compare Flag A 0 [Clearing conditions] • When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 • When DMAC is activated by TGIA interrupt while DTA bit of DMABCR in DMAC*1 is 1 • When 0 is written to TGFA after reading TG
Appendix B Internal I/O Registers TCNT5—Timer Counter 5 Bit H'FEA6 TPU5 : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Up/down-counter* Note: * This timer counter can be used as an up/down-counter only in phase counting mode or when performing overflow/underflow counting on another channel. In other cases it functions as an up-counter.
Appendix B Internal I/O Registers P2DDR—Port 2 Data Direction Register Bit : 7 6 H'FEB1 5 4 Port 2 3 2 0 1 P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR Initial value : 0 0 0 0 0 0 0 0 Read/Write : W W W W W W W W Specify input or output for individual port 2 pins P3DDR—Port 3 Data Direction Register Bit : Initial value : Read/Write : 7 6 — — 5 — 4 Port 3 3 2 0 1 P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR Undefined Undefined — H'FEB2 0 0 0 0 0
Appendix B Internal I/O Registers P6DDR—Port 6 Data Direction Register Bit : 7 6 5 H'FEB5 4 3 Port 6 2 0 1 P67DDR P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR Initial value : 0 0 0 0 0 0 0 0 Read/Write : W W W W W W W W Specify input or output for individual port 6 pins PADDR—Port A Data Direction Register Bit : 7 6 5 H'FEB9 4 Port A 3 2 0 1 PA7DDR PA6DDR PA5DDR PA4DDR PA3DDR PA2DDR PA1DDR PA0DDR Initial value : 0 0 0 0 0 0 0 0 Read/Write : W W W W
Appendix B Internal I/O Registers PCDDR—Port C Data Direction Register Bit : 7 6 H'FEBB 5 4 3 Port C 2 1 0 PC7DDR PC6DDR PC5DDR PC4DDR PC3DDR PC2DDR PC1DDR PC0DDR Initial value : 0 0 0 0 0 0 0 0 Read/Write : W W W W W W W W Specify input or output for individual port C pins PDDDR—Port D Data Direction Register Bit : 7 6 5 H'FEBC 4 3 Port D 2 1 0 PD7DDR PD6DDR PD5DDR PD4DDR PD3DDR PD2DDR PD1DDR PD0DDR Initial value : 0 0 0 0 0 0 0 0 Read/Write : W W W W
Appendix B Internal I/O Registers PFDDR—Port F Data Direction Register Bit : 7 6 5 H'FEBE 4 3 Port F 2 1 0 PF7DDR PF6DDR PF5DDR PF4DDR PF3DDR PF2DDR PF1DDR PF0DDR Modes 4 to 6 Initial value : 1 0 0 0 0 0 0 0 Read/Write : W W W W W W W W Initial value : 0 0 0 0 0 0 0 0 Read/Write : W W W W W W W W Mode 7 Specify input or output for individual port F pins PGDDR—Port G Data Direction Register Bit : 7 6 5 — — — H'FEBF 4 3 Port G 2 1 0 PG4DDR PG3D
Appendix B Internal I/O Registers IPRA IPRB IPRC IPRD IPRE IPRF IPRG IPRH IPRI IPRJ IPRK Bit — — — — — — — — — — — Interrupt Priority Register A Interrupt Priority Register B Interrupt Priority Register C Interrupt Priority Register D Interrupt Priority Register E Interrupt Priority Register F Interrupt Priority Register G Interrupt Priority Register H Interrupt Priority Register I Interrupt Priority Register J Interrupt Priority Register K : H'FEC4 H'FEC5 H'FEC6 H'FEC7 H'FEC8 H'FEC9 H'FECA H'FECB H'FEC
Appendix B Internal I/O Registers ABWCR—Bus Width Control Register Bit : H'FED0 Bus Controller 7 6 5 4 3 2 1 0 ABW7 ABW6 ABW5 ABW4 ABW3 ABW2 ABW1 ABW0 Modes 5 to 7 Initial value : 1 1 1 1 1 1 1 1 R/W R/W R/W R/W R/W R/W R/W R/W Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W : Mode 4 Area 7 to 0 Bus Width Control 0 Area n is designated for 16-bit access 1 Area n is designated for 8-bit access (n = 7 to 0) ASTCR—A
Appendix B Internal I/O Registers WCRH—Wait Control Register H Bit : H'FED2 Bus Controller 7 6 5 4 3 2 1 0 W71 W70 W61 W60 W51 W50 W41 W40 Initial value : 1 1 1 1 1 1 1 1 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Area 4 Wait Control 0 1 0 Program wait not inserted 1 1 program wait state inserted 0 2 program wait states inserted 1 3 program wait states inserted Area 5 Wait Control 0 1 0 Program wait not inserted 1 1 program wait state inserted 0 2 pr
Appendix B Internal I/O Registers WCRL—Wait Control Register L H'FED3 Bus Controller 7 6 5 4 3 2 1 0 W31 W30 W21 W20 W11 W10 W01 W00 Initial value : 1 1 1 1 1 1 1 1 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Bit : Area 0 Wait Control 0 1 0 Program wait not inserted 1 1 program wait state inserted 0 2 program wait states inserted 1 3 program wait states inserted Area 1 Wait Control 0 1 0 Program wait not inserted 1 1 program wait state inserted 0 2 p
Appendix B Internal I/O Registers BCRH—Bus Control Register H Bit : 7 6 H'FED4 5 4 3 Bus Controller 1 0 RMTS1 RMTS0 2 ICIS1 ICIS0 Initial value : 1 1 0 1 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W BRSTRM BRSTS1 BRSTS0 RMTS2 RAM Type Select RMTS2 RMTS1 RMTS0 Area 5 Area 4 Area 3 Area 2 0 0 Normal space 0 1 1 1 0 — DRAM space Normal space Normal space DRAM space 1 DRAM space — — Notes: 1.
Appendix B Internal I/O Registers BCRL—Bus Control Register L H'FED5 Bus Controller 7 6 5 4 3 2 1 0 BRLE BREQOE EAE — DDS — WDBE WAITE Initial value : 0 0 1 1 1 1 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Bit : WAIT Pin Enable 0 Wait input by WAIT pin* disabled 1 Wait input by WAIT pin* enabled Note: * The WAIT input pin can be switched between PF2 and P53 by means of WAITPS.
Appendix B Internal I/O Registers MCR—Memory Control Register (Not supported in H8S/2321) Bit H'FED6 Bus Controller 7 6 5 4 3 2 1 0 TPC BE RCDM — MXC1 MXC0 RLW1 RLW0 : Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Refresh Cycle Wait Control 0 1 0 No wait state inserted 1 1 wait state inserted 0 2 wait states inserted 1 3 wait states inserted Multiplex Shift Count 0 1 0 8-bit shift 1 9-bit shift 0 10-bit shift 1 — Reser
Appendix B Internal I/O Registers DRAMCR—DRAM Control Register (Not supported in H8S/2321) Bit H'FED7 Bus Controller 7 6 5 4 3 2 1 0 RFSHE RCW RMODE CMF CMIE CKS2 CKS1 CKS0 : Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Refresh Counter Clock Select 0 0 1 1 0 1 0 Count operation disabled 1 Count uses φ/2 0 Count uses φ/8 1 Count uses φ/32 0 Count uses φ/128 1 Count uses φ/512 0 Count uses φ/2048 1 Count uses φ/4096 C
Appendix B Internal I/O Registers RTCNT—Refresh Timer Counter (Not supported in H8S/2321) Bit H'FED8 Bus Controller : 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Internal clock count value RTCOR—Refresh Time Constant Register (Not supported in H8S/2321) Bit : 7 6 5 H'FED9 4 3 Bus Controller 2 1 0 Initial value : 1 1 1 1 1 1 1 1 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Sets the period for compar
Appendix B Internal I/O Registers RAMER—RAM Emulation Register (Valid only in F-ZTAT version) Bit : H'FEDB Bus Controller 7 6 5 4 3 2 1 0 — — — — RAMS RAM2 RAM1 RAM0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : — — — — R/W R/W R/W R/W RAM Select, Flash Memory Area Select RAMS RAM2 RAM1 RAM0 RAM Area Block Name 0 * * * H'FFDC00 to H'FFEBFF RAM area, 4 kbytes 1 0 0 0 H'000000 to H'000FFF EB0 (4 kbytes) 1 H'001000 to H'001FFF EB1 (4 kbytes) 0 H'002000 t
Appendix B Internal I/O Registers MAR0AH—Memory Address Register 0AH (Not supported in H8S/2321) MAR0AL—Memory Address Register 0AL (Not supported in H8S/2321) H'FEE0 DMAC H'FEE2 DMAC Bit : 31 30 29 28 27 26 25 24 MAR0AH : — — — — — — — — 23 22 21 20 19 18 17 16 * * * * * * * * Initial value : 0 0 0 0 0 0 0 0 Read/Write : — — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MAR0AL : * * *
Appendix B Internal I/O Registers ETCR0A—Transfer Count Register 0A (Not supported in H8S/2321) Bit : ETCR0A : Initial value : H'FEE6 DMAC 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 * * * * * * * * * * * * * * * * Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Sequential mode Idle mode Normal mode Repeat mode Transfer counter Transfer number storage register Transfer counter Block size storage register Block size counter Block transfer m
Appendix B Internal I/O Registers IOAR0B—I/O Address Register 0B (Not supported in H8S/2321) Bit : IOAR0B : 15 14 13 12 11 H'FEEC 10 9 8 7 6 DMAC 5 4 3 2 1 0 Initial value : * * * * * * * * * * * * * * * * Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W * : Undefined In short address mode: Specifies transfer source/transfer destination address In full address mode: Not used ETCR0B—Transfer Count Register 0B (Not supported in H8S/2321) Bit : ETCR0B :
Appendix B Internal I/O Registers MAR1AH—Memory Address Register 1AH (Not supported in H8S/2321) MAR1AL—Memory Address Register 1AL (Not supported in H8S/2321) H'FEF0 DMAC H'FEF2 DMAC Bit : 31 30 29 28 27 26 25 24 MAR1AH : — — — — — — — — Initial value : 0 0 0 0 0 0 0 0 Read/Write : — — — — — — — — R/W R/W R/W R/W R/W R/W R/W R/W Bit : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 MAR1AL : * * * * * * * * * * * * * * * * Initial value :
Appendix B Internal I/O Registers ETCR1A—Transfer Count Register 1A (Not supported in H8S/2321) Bit : ETCR1A : Initial value : H'FEF6 DMAC 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 * * * * * * * * * * * * * * * * Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Sequential mode Idle mode Normal mode Transfer counter Repeat mode Transfer number storage register Transfer counter Block size storage register Block size counter Block transfer m
Appendix B Internal I/O Registers IOAR1B—I/O Address Register 1B (Not supported in H8S/2321) Bit : IOAR1B : Initial value : H'FEFC DMAC 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 * * * * * * * * * * * * * * * * Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W * : Undefined In short address mode: Specifies transfer source/transfer destination address In full address mode: Not used ETCR1B—Transfer Count Register 1B (Not supported in H8S/2321) Bit
Appendix B Internal I/O Registers DMAWER—DMA Write Enable Register (Not supported in H8S/2321) H'FF00 DMAC : 7 6 5 4 3 2 1 0 DMAWER : — — — — WE1B WE1A WE0B WE0A Initial value : 0 0 0 0 0 0 0 0 Read/Write : — — — — R/W R/W R/W R/W Bit Write Enable 0A 0 Writes to all bits in DMACR0A, and bits 8, 4, and 0 in DMABCR are disabled 1 Writes to all bits in DMACR0A, and bits 8, 4, and 0 in DMABCR are enabled Write Enable 0B 0 Writes to all bits in DMACR0B, bits 9, 5, an
Appendix B Internal I/O Registers DMATCR—DMA Terminal Control Register (Not supported in H8S/2321) H'FF01 DMAC : 7 6 5 4 3 2 1 0 : — — TEE1 TEE0 — — — — Initial value : 0 0 0 0 0 0 0 0 Read/Write : — — R/W R/W — — — — Bit DMATCR Transfer End Enable 0 0 TEND0 pin output disabled 1 TEND0 pin output enabled Transfer End Enable 1 0 TEND1 pin output disabled 1 TEND1 pin output enabled Rev.6.00 Sep.
Appendix B Internal I/O Registers DMACR0A—DMA Control Register 0A (Not supported in H8S/2321) DMACR0B—DMA Control Register 0B (Not supported in H8S/2321) DMACR1A—DMA Control Register 1A (Not supported in H8S/2321) DMACR1B—DMA Control Register 1B (Not supported in H8S/2321) H'FF02 DMAC H'FF03 DMAC H'FF04 DMAC H'FF05 DMAC Full address mode Bit : 15 14 13 12 11 10 9 8 DMACRA : DTSZ SAID SAIDE BLKDIR BLKE — — — Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R
Appendix B Internal I/O Registers Full address mode (cont) Bit : 7 6 5 4 3 2 1 0 DMACRB : — DAID DAIDE — DTF3 DTF2 DTF1 DTF0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Reserved Only 0 should be written to this bit Reserved Only 0 should be written to this bit Data Transfer Factor DTF DTF DTF DTF 3 2 1 0 0 0 0 0 — 1 1 0 1 1 0 0 1 1 0 1 1 Activated by A/D converter conversion end interrupt 0 Activated by DREQ pin falling e
Appendix B Internal I/O Registers Short address mode Bit : 7 6 5 4 3 2 1 0 DMACR : DTSZ DTID RPE DTDIR DTF3 DTF2 DTF1 DTF0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Data Transfer Factor Data Transfer Direction 0 1 DTF DTF DTF DTF Channel A 3 2 1 0 0 0 0 0 — Dual address mode: Transfer with MAR as source address and IOAR as destination address Single address mode: Transfer with MAR as source address and DACK pin as write strobe 1
Appendix B Internal I/O Registers DMABCRH — DMA Band Control Register (Not supported in H8S/2321) DMABCRL — DMA Band Control Register (Not supported in H8S/2321) H'FF06 DMAC H'FF07 DMAC Full address mode Bit : DMABCRH : 15 14 13 12 11 10 9 8 FAE1 FAE0 — — DTA1 — DTA0 — Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Reserved Only 0 should be written to this bit Channel 0 Data Transfer Acknowledge 0 Clearing of selected internal interru
Appendix B Internal I/O Registers Full address mode (cont) Bit : DMABCRL : 7 6 5 4 DTME1 DTE1 DTME0 DTE0 3 2 0 1 DTIE1B DTIE1A DTIE0B DTIE0A Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Channel 0 Data Transfer Interrupt Enable A 0 Transfer end interrupt disabled 1 Transfer end interrupt enabled Channel 0 Data Transfer Interrupt Enable B 0 Transfer suspended interrupt disabled 1 Transfer suspended interrupt enabled Channel 1 Data Trans
Appendix B Internal I/O Registers Short address mode Bit : DMABCRH : 15 14 13 12 11 10 9 8 FAE1 FAE0 SAE1 SAE0 DTA1B DTA1A DTA0B DTA0A Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Channel 0A Data Transfer Acknowledge 0 Clearing of selected internal interrupt source at time of DMA transfer is disabled 1 Clearing of selected internal interrupt source at time of DMA transfer is enabled Channel 0B Data Transfer Acknowledge 0 Clearing of s
Appendix B Internal I/O Registers Short address mode (cont) Bit : DMABCRL : 7 6 5 4 DTE1B DTE1A DTE0B DTE0A 3 2 DTIE1B DTIE1A 0 1 DTIE0B DTIE0A Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Channel 0A Data Transfer Interrupt Enable 0 Transfer end interrupt disabled 1 Transfer end interrupt enabled Channel 0B Data Transfer Interrupt Enable 0 Transfer end interrupt disabled 1 Transfer end interrupt enabled Channel 1A Data Transfer Interr
Appendix B Internal I/O Registers ISCRH — IRQ Sense Control Register H ISCRL — IRQ Sense Control Register L H'FF2C H'FF2D Interrupt Controller Interrupt Controller ISCRH Bit : 15 14 13 12 11 10 9 8 IRQ7SCB IRQ7SCA IRQ6SCB IRQ6SCA IRQ5SCB IRQ5SCA IRQ4SCB IRQ4SCA Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W 1 0 IRQ7 to IRQ4 Sense Control ISCRL Bit : 7 6 5 4 3 2 IRQ3SCB IRQ3SCA IRQ2SCB IRQ2SCA IRQ1SCB IRQ1SCA IRQ0SCB IRQ0SCA Initial valu
Appendix B Internal I/O Registers IER—IRQ Enable Register Bit : H'FF2E Interrupt Controller 7 6 5 4 3 2 1 0 IRQ7E IRQ6E IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W IRQn Enable 0 IRQn interrupt disabled 1 IRQn interrupt enabled (n = 7 to 0) ISR—IRQ Status Register Bit : H'FF2F Interrupt Controller 7 6 5 4 3 2 1 0 IRQ7F IRQ6F IRQ5F IRQ4F IRQ3F IRQ2F IRQ1F IRQ0F Initial value : 0
Appendix B Internal I/O Registers DTCERA to DTCERF—DTC Enable Registers Bit : H'FF30 to H'FF35 DTC 7 6 5 4 3 2 1 0 DTCE7 DTCE6 DTCE5 DTCE4 DTCE3 DTCE2 DTCE1 DTCE0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W DTC Activation Enable 0 DTC activation by this interrupt is disabled [Clearing conditions] • When the DISEL bit is 1 and data transfer has ended • When the specified number of transfers have ended 1 DTC activation by this interrup
Appendix B Internal I/O Registers DTVECR—DTC Vector Register Bit : 7 6 H'FF37 5 4 3 DTC 2 1 0 SWDTE DTVEC6 DTVEC5 DTVEC4 DTVEC3 DTVEC2 DTVEC1 DTVEC0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Sets vector number for DTC software activation DTC Software Activation Enable 0 DTC software activation is disabled [Clearing conditions] • When the DISEL bit is 0 and the specified number of transfers have not ended • When SWDTEND is
Appendix B Internal I/O Registers SBYCR—Standby Control Register Bit : H'FF38 Power-Down State 7 6 5 4 3 2 1 0 SSBY STS2 STS1 STS0 OPE — — IRQ37S Initial value : 0 0 0 0 1 0 0 0 Read/Write : R/W R/W R/W R/W R/W — — R/W IRQ37 Software Standby Clear Select 0 IRQ3 to IRQ7 cannot be used as software standby mode clearing sources 1 IRQ3 to IRQ7 can be used as software standby mode clearing sources Output Port Enable 0 In software standby mode, address bus and bus contr
Appendix B Internal I/O Registers SYSCR—System Control Register Bit : H'FF39 7 6 5 4 — — INTM1 INTM0 MCU 3 2 0 1 NMIEG LWROD IRQPAS RAME Initial value : 0 0 0 0 0 0 0 1 Read/Write : R/W — R/W R/W R/W R/W R/W R/W RAM Enable 0 On-chip RAM disabled 1 On-chip RAM enabled IRQ Port Switching Select 0 IRQ4 to IRQ7 can be input from PA4 to PA7 1 IRQ4 to IRQ7 can be input from P50 to P53 Note: IRQ4 to IRQ7 input is always performed from only one of the ports.
Appendix B Internal I/O Registers SCKCR—System Clock Control Register Bit : H'FF3A Clock Pulse Generator 7 6 5 4 3 2 1 0 PSTOP — DIV — — SCK2 SCK1 SCK0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W — — R/W R/W R/W Division Ratio Select Reserved Only 0 should be written to this bit System Clock Select SCK2 SCK1 SCK0 0 0 1 1 0 1 DIV = 0 DIV = 1 0 Bus master is in high-speed mode Bus master is in high-speed mode 1 Medium-speed clock is φ/2 Clock sup
Appendix B Internal I/O Registers MDCR—Mode Control Register Bit : H'FF3B MCU 7 6 5 4 3 2 1 0 — — — — — MDS2 MDS1 MDS0 Initial value : 1 0 0 0 0 —* —* —* Read/Write : — — — — — R R R Current mode pin operating mode Note: * Determined by pins MD2 to MD0 MSTPCRH — Module Stop Control Register H MSTPCRL — Module Stop Control Register L H'FF3C H'FF3D Power-Down State Power-Down State MSTPCRH Bit MSTPCRL : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial
Appendix B Internal I/O Registers SYSCR2—System Control Register 2 Bit : H'FF42 MCU (Valid only in F-ZTAT versions) 7 6 5 4 3 2 1 0 — — — — FLSHE — — — Initial value : 0 0 0 0 0 0 0 0 Read/Write : — — — — R/W — — — (R/W) In the H8S/2329B only this bit is R/W, and should only be written with 0 Flash Memory Control Register Enable 0 H8S/2329B F-ZTAT, H8S/2328B F-ZTAT, and H8S/2326 F-ZTAT • Flash control registers are not selected for addresses H'FFFFC8 to H'FFFFCB 1
Appendix B Internal I/O Registers PFCR1—Port Function Control Register 1 Bit : H'FF45 7 6 5 4 3 2 1 0 — — — — A23E A22E A21E A20E Initial value : 0 0 0 0 1 1 1 1 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Address 20 Output Enable* 0 PA4DR is output when PA4DDR = 1 1 A20 is output when PA4DDR = 1 Address 21 Output Enable* 0 PA5DR is output when PA5DDR = 1 1 A21 is output when PA5DDR = 1 Address 22 Output Enable* 0 PA6DR is output when PA6DDR = 1 1 A22 is out
Appendix B Internal I/O Registers PCR—PPG Output Control Register Bit : 7 6 H'FF46 5 4 3 PPG 2 1 0 G3CMS1 G3CMS0 G2CMS1 G2CMS0 G1CMS1 G1CMS0 G0CMS1 G0CMS0 Initial value : 1 1 1 1 1 1 1 1 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Output Trigger for Pulse Output Group 0 0 1 0 Compare match in TPU channel 0 1 Compare match in TPU channel 1 0 Compare match in TPU channel 2 1 Compare match in TPU channel 3 Output Trigger for Pulse Output Group 1 0 1 0 Compare match i
Appendix B Internal I/O Registers PMR—PPG Output Mode Register Bit : H'FF47 7 6 5 4 PPG 3 2 1 0 G3INV G2INV G1INV G0INV Initial value : 1 1 1 1 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W G3NOV G2NOV G1NOV G0NOV Pulse Output Group n Normal/Non-Overlap Operation Select 0 Normal operation in pulse output group n (output values updated at compare match A in the selected TPU channel) 1 Non-overlapping operation in pulse output group n (independent 1 and 0 output
Appendix B Internal I/O Registers NDERH — Next Data Enable Register H NDERL — Next Data Enable Register L H'FF48 H'FF49 PPG PPG NDERH Bit : 7 6 5 4 3 2 1 0 NDER15 NDER14 NDER13 NDER12 NDER11 NDER10 NDER9 NDER8 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W 1 0 Pulse Output Enable/Disable 0 Pulse outputs PO15 to PO8 are disabled 1 Pulse outputs PO15 to PO8 are enabled NDERL Bit : 7 NDER7 6 5 NDER6 NDER5 4 3 NDER4 NDER3 2 NDER2 ND
Appendix B Internal I/O Registers PODRH — Output Data Register H PODRL — Output Data Register L H'FF4A H'FF4B PPG PPG PODRH Bit : 7 6 5 4 3 2 1 0 POD15 POD14 POD13 POD12 POD11 POD10 POD9 POD8 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* Stores output data for use in pulse output PODRL Bit : 7 6 5 4 3 2 1 0 POD7 POD6 POD5 POD4 POD3 POD2 POD1 POD0 Initial value : 0 0 0 0 0 0 0 0 Read/Wr
Appendix B Internal I/O Registers NDRH—Next Data Register H H'FF4C (FF4E) PPG (1) When pulse output group output triggers are the same (a) Address: H'FF4C Bit : 7 6 5 4 3 2 1 0 NDR15 NDR14 NDR13 NDR12 NDR11 NDR10 NDR9 NDR8 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Stores the next data for pulse output groups 3 and 2 (b) Address: H'FF4E Bit : 7 6 5 4 3 2 1 0 — — — — — — — — Initial value : 1 1 1 1 1 1 1 1
Appendix B Internal I/O Registers NDRL—Next Data Register L H'FF4D (FF4F) PPG (1) When pulse output group output triggers are the same (a) Address: H'FF4D Bit : 7 6 5 4 3 2 1 0 NDR7 NDR6 NDR5 NDR4 NDR3 NDR2 NDR1 NDR0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Stores the next data for pulse output groups 1 and 0 (b) Address: H'FF4F Bit : 7 6 5 4 3 2 1 0 — — — — — — — — Initial value : 1 1 1 1 1 1 1 1 Read
Appendix B Internal I/O Registers PORT1—Port 1 Register Bit : H'FF50 Port 1 7 6 5 4 3 2 1 0 P17 P16 P15 P14 P13 P12 P11 P10 Initial value : —* —* —* —* —* —* —* —* Read/Write : R R R R R R R R State of port 1 pins Note: * Determined by the state of pins P17 to P10.
Appendix B Internal I/O Registers PORT4—Port 4 Register Bit : H'FF53 Port 4 7 6 5 4 3 2 1 0 P47 P46 P45 P44 P43 P42 P41 P40 Initial value : —* —* —* —* —* —* —* —* Read/Write : R R R R R R R R State of port 4 pins Note: * Determined by the state of pins P47 to P40.
Appendix B Internal I/O Registers PORTA—Port A Register Bit : H'FF59 Port A 7 6 5 4 3 2 1 0 PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0 Initial value : —* —* —* —* —* —* —* —* Read/Write : R R R R R R R R State of port A pins Note: * Determined by the state of pins PA7 to PA0.
Appendix B Internal I/O Registers PORTD—Port D Register Bit : H'FF5C Port D 7 6 5 4 3 2 1 0 PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 Initial value : —* —* —* —* —* —* —* —* Read/Write : R R R R R R R R State of port D pins Note: * Determined by the state of pins PD7 to PD0.
Appendix B Internal I/O Registers PORTG—Port G Register Bit : H'FF5F 7 6 5 4 3 2 1 0 — — — PG4 PG3 PG2 PG1 PG0 —* —* —* —* —* R R R R R Initial value : Undefined Undefined Undefined Read/Write : Port G — — — State of port G pins Note: * Determined by the state of pins PG4 to PG0.
Appendix B Internal I/O Registers P3DR—Port 3 Data Register Bit : H'FF62 7 6 5 4 3 2 1 0 — — P35DR P34DR P33DR P32DR P31DR P30DR 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W Initial value : Undefined Undefined Read/Write : Port 3 — — Stores output data for port 3 pins (P35 to P30) P5DR—Port 5 Data Register Bit : H'FF64 7 6 5 4 3 2 1 0 — — — — P53DR P52DR P51DR P50DR 0 0 0 0 R/W R/W R/W R/W Initial value : Undefined Undefined Undefined Undefined Read/Wri
Appendix B Internal I/O Registers PADR—Port A Data Register Bit : H'FF69 Port A 7 6 5 4 3 2 1 0 PA7DR PA6DR PA5DR PA4DR PA3DR PA2DR PA1DR PA0DR Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Stores output data for port A pins (PA7 to PA0) PBDR—Port B Data Register Bit : H'FF6A Port B 7 6 5 4 3 2 1 0 PB7DR PB6DR PB5DR PB4DR PB3DR PB2DR PB1DR PB0DR Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W
Appendix B Internal I/O Registers PDDR—Port D Data Register Bit : 7 PD7DR H'FF6C 6 5 PD6DR PD5DR 4 3 PD4DR PD3DR Port D 2 PD2DR 1 0 PD1DR PD0DR Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Stores output data for port D pins (PD7 to PD0) PEDR—Port E Data Register Bit : H'FF6D Port E 7 6 5 4 3 2 1 0 PE7DR PE6DR PE5DR PE4DR PE3DR PE2DR PE1DR PE0DR Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W
Appendix B Internal I/O Registers PGDR—Port G Data Register Bit : H'FF6F 7 6 5 — — — 4 — — 3 2 — 0 1 PG4DR PG3DR PG2DR Initial value : Undefined Undefined Undefined Read/Write : Port G PG1DR PG0DR 0 0 0 0 0 R/W R/W R/W R/W R/W Stores output data for port G pins (PG4 to PG0) PAPCR—Port A MOS Pull-Up Control Register Bit : 7 6 5 4 H'FF70 3 Port A 2 0 1 PA7PCR PA6PCR PA5PCR PA4PCR PA3PCR PA2PCR PA1PCR PA0PCR Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W
Appendix B Internal I/O Registers PCPCR—Port C MOS Pull-Up Control Register Bit : 7 6 5 4 H'FF72 3 Port C 2 1 0 PC7PCR PC6PCR PC5PCR PC4PCR PC3PCR PC2PCR PC1PCR PC0PCR Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Controls the MOS input pull-up function incorporated into port C on a bit-by-bit basis PDPCR—Port D MOS Pull-Up Control Register Bit : 7 6 5 4 H'FF73 3 Port D 2 1 0 PD7PCR PD6PCR PD5PCR PD4PCR PD3PCR PD2PCR PD1PCR PD0PCR Initia
Appendix B Internal I/O Registers P3ODR—Port 3 Open Drain Control Register Bit : 7 6 — — 5 — 4 3 Port 3 2 1 0 P35ODR P34ODR P33ODR P32ODR P31ODR P30ODR Initial value : Undefined Undefined Read/Write : H'FF76 — 0 0 0 0 0 0 R/W R/W R/W R/W R/W R/W Controls the PMOS on/off status for each port 3 pin (P35 to P30) PAODR—Port A Open Drain Control Register Bit : 7 6 5 H'FF77 4 3 Port A 2 1 0 PA7ODR PA6ODR PA5ODR PA4ODR PA3ODR PA2ODR PA1ODR PA0ODR Initial value : 0 0 0 0
Appendix B Internal I/O Registers SMR0—Serial Mode Register 0 Bit : H'FF78 SCI0 7 6 5 4 3 2 1 0 C/A CHR PE O/E STOP MP CKS1 CKS0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Clock Select 0 1 0 φ clock 1 φ/4 clock 0 φ/16 clock 1 φ/64 clock Multiprocessor Mode 0 Multiprocessor function disabled 1 Multiprocessor format selected Stop Bit Length 0 1 stop bit 1 2 stop bits Parity Mode 0 Even parity 1 Odd parity Parity Ena
Appendix B Internal I/O Registers SMR0—Serial Mode Register 0 Bit : H'FF78 Smart Card Interface 0 7 6 5 4 3 2 1 0 GM BLK PE O/E BCP1 BCP0 CKS1 CKS0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Clock Select 0 1 0 φ clock 1 φ/4 clock 0 φ/16 clock 1 φ/64 clock Base Clock Pulse BCP1 BCP0 0 1 Base Clock Pulse 0 32 clocks 1 64 clocks 0 372 clocks 1 256 clocks Parity Mode 0 Even parity 1 Odd parity Parity Enable (Set to
Appendix B Internal I/O Registers BRR0—Bit Rate Register 0 Bit H'FF79 SCI0, Smart Card Interface 0 : 7 6 5 4 3 2 1 0 Initial value : 1 1 1 1 1 1 1 1 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Sets the serial transfer bit rate Note: For details, see section 14.2.8, Bit Rate Register (BRR). Rev.6.00 Sep.
Appendix B Internal I/O Registers SCR0—Serial Control Register 0 Bit : H'FF7A SCI0 7 6 5 4 3 2 1 0 TIE RIE TE RE MPIE TEIE CKE1 CKE0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Clock Enable 0 0 1 1 0 1 Asynchronous mode Internal clock/SCK pin functions as I/O port Synchronous mode Asynchronous mode Synchronous mode Internal clock/SCK pin functions as serial clock output Internal clock/SCK pin functions as clock output*1 Interna
Appendix B Internal I/O Registers SCR0—Serial Control Register 0 Bit : H'FF7A Smart Card Interface 0 7 6 5 4 3 2 1 0 TIE RIE TE RE MPIE TEIE CKE1 CKE0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Clock Enable SCMR SMR SMIF GM SCR setting CKE1 0 CKE0 SCK pin function See SCI specification 1 0 0 0 Operates as port I/O pin 1 0 0 1 Clock output as SCK output pin 1 1 0 0 Fixed-low output as SCK output pin 1 1 0 1 C
Appendix B Internal I/O Registers TDR0—Transmit Data Register 0 Bit H'FF7B SCI0, Smart Card Interface 0 : 7 6 5 4 3 2 1 0 Initial value : 1 1 1 1 1 1 1 1 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Stores data for serial transmission Rev.6.00 Sep.
Appendix B Internal I/O Registers SSR0—Serial Status Register 0 Bit : H'FF7C 7 6 5 4 3 2 1 0 TDRE RDRF ORER FER PER TEND MPB MPBT Initial value : 1 0 0 0 0 1 0 0 Read/Write : R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R R R/W SCI0 Multiprocessor Bit Transfer 0 Data with a 0 multiprocessor bit is transmitted 1 Data with a 1 multiprocessor bit is transmitted Multiprocessor Bit 0 [Clearing condition] When data with a 0 multiprocessor bit is received 1 [Setting condition] W
Appendix B Internal I/O Registers SSR0—Serial Status Register 0 Bit : H'FF7C 7 6 5 4 3 2 1 0 TDRE RDRF ORER ERS PER TEND MPB MPBT Initial value : 1 0 0 0 0 1 0 0 Read/Write : R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R R R/W Smart Card Interface 0 Multiprocessor Bit Transfer 0 Data with a 0 multiprocessor bit is transmitted 1 Data with a 1 multiprocessor bit is transmitted Multiprocessor Bit 0 [Clearing condition] When data with a 0 multiprocessor bit is received 1 [Se
Appendix B Internal I/O Registers RDR0—Receive Data Register 0 Bit H'FF7D SCI0, Smart Card Interface 0 : 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R R R R R R R R Stores received serial data SCMR0—Smart Card Mode Register 0 Bit : H'FF7E SCI0, Smart Card Interface 0 7 6 5 4 3 2 1 0 — — — — SDIR SINV — SMIF Initial value : 1 1 1 1 0 0 1 0 Read/Write : — — — — R/W R/W — R/W Smart Card Interface Mode Select 0 Smart card in
Appendix B Internal I/O Registers SMR1—Serial Mode Register 1 Bit : H'FF80 SCI1 7 6 5 4 3 2 1 0 C/A CHR PE O/E STOP MP CKS1 CKS0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Clock Select 0 1 0 φ clock 1 φ/4 clock 0 φ/16 clock 1 φ/64 clock Multiprocessor Mode 0 Multiprocessor function disabled 1 Multiprocessor format selected Stop Bit Length 0 1 stop bit 1 2 stop bits Parity Mode 0 Even parity 1 Odd parity Parity Ena
Appendix B Internal I/O Registers SMR1—Serial Mode Register 1 Bit : H'FF80 Smart Card Interface 1 7 6 5 4 3 2 1 0 GM BLK PE O/E BCP1 BCP0 CKS1 CKS0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Clock Select 0 1 0 φ clock 1 φ/4 clock 0 φ/16 clock 1 φ/64 clock Base Clock Pulse BCP1 BCP0 0 1 Base Clock Pulse 0 32 clocks 1 64 clocks 0 372 clocks 1 256 clocks Parity Mode (Set to 1 when using the smart card interface) 0 Ev
Appendix B Internal I/O Registers BRR1—Bit Rate Register 1 Bit H'FF81 SCI1, Smart Card Interface 1 : 7 6 5 4 3 2 1 0 Initial value : 1 1 1 1 1 1 1 1 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Sets the serial transfer bit rate Note: For details, see section 14.2.8, Bit Rate Register (BRR). Rev.6.00 Sep.
Appendix B Internal I/O Registers SCR1—Serial Control Register 1 Bit : H'FF82 SCI1 7 6 5 4 3 2 1 0 TIE RIE TE RE MPIE TEIE CKE1 CKE0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Clock Enable 0 1 0 Asynchronous mode Synchronous mode Internal clock/SCK pin functions as I/O port Internal clock/SCK pin functions as serial clock output 1 Asynchronous mode Synchronous mode Internal clock/SCK pin functions as clock output*1 0 1 Async
Appendix B Internal I/O Registers SCR1—Serial Control Register 1 Bit : H'FF82 Smart Card Interface 1 7 6 5 4 3 2 1 0 TIE RIE TE RE MPIE TEIE CKE1 CKE0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Clock Enable SCMR SMR SMIF GM SCR setting CKE1 0 CKE0 SCK pin function See SCI specification 1 0 0 0 Operates as port I/O pin 1 0 0 1 Clock output as SCK output pin 1 1 0 0 Fixed-low output as SCK output pin 1 1 0 1 Clo
Appendix B Internal I/O Registers TDR1—Transmit Data Register 1 Bit H'FF83 SCI1, Smart Card Interface 1 : 7 6 5 4 3 2 1 0 Initial value : 1 1 1 1 1 1 1 1 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Stores data for serial transmission Rev.6.00 Sep.
Appendix B Internal I/O Registers SSR1—Serial Status Register 1 Bit : H'FF84 7 6 5 4 3 2 1 0 TDRE RDRF ORER FER PER TEND MPB MPBT Initial value : 1 0 0 0 0 1 0 0 Read/Write : R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R R R/W Multiprocessor Bit Transfer 0 Data with a 0 multiprocessor bit is transmitted 1 Data with a 1 multiprocessor bit is transmitted Multiprocessor Bit 0 [Clearing condition] When data with a 0 multiprocessor bit is received 1 [Setting condition] When dat
Appendix B Internal I/O Registers SSR1—Serial Status Register 1 Bit : H'FF84 7 6 5 4 3 2 1 0 TDRE RDRF ORER ERS PER TEND MPB MPBT Initial value : 1 0 0 0 0 1 0 0 Read/Write : R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R R R/W Smart Card Interface 1 Multiprocessor Bit Transfer 0 Data with a 0 multiprocessor bit is transmitted 1 Data with a 1 multiprocessor bit is transmitted Multiprocessor Bit 0 [Clearing condition] When data with a 0 multiprocessor bit is received 1 [Se
Appendix B Internal I/O Registers RDR1—Receive Data Register 1 Bit H'FF85 SCI1, Smart Card Interface 1 : 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R R R R R R R R Stores received serial data SCMR1—Smart Card Mode Register 1 Bit : H'FF86 SCI1, Smart Card Interface 1 7 6 5 4 3 2 1 0 — — — — SDIR SINV — SMIF Initial value : 1 1 1 1 0 0 1 0 Read/Write : — — — — R/W R/W — R/W Smart Card Interface Mode Select 0 Smart card in
Appendix B Internal I/O Registers SMR2—Serial Mode Register 2 Bit : H'FF88 SCI2 7 6 5 4 3 2 1 0 C/A CHR PE O/E STOP MP CKS1 CKS0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Clock Select 0 1 0 φ clock 1 φ/4 clock 0 φ/16 clock 1 φ/64 clock Multiprocessor Mode 0 Multiprocessor function disabled 1 Multiprocessor format selected Stop Bit Length 0 1 stop bit 1 2 stop bits Parity Mode 0 Even parity 1 Odd parity Parity Ena
Appendix B Internal I/O Registers SMR2—Serial Mode Register 2 Bit : H'FF88 Smart Card Interface 2 7 6 5 4 3 2 1 0 GM BLK PE O/E BCP1 BCP0 CKS1 CKS0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Clock Select 0 1 0 φ clock 1 φ/4 clock 0 φ/16 clock 1 φ/64 clock Base Clock Pulse BCP1 BCP0 0 1 Base Clock Pulse 0 32 clocks 1 64 clocks 0 372 clocks 1 256 clocks Parity Mode (Set to 1 when using the smart card interface) 0 Ev
Appendix B Internal I/O Registers BRR2—Bit Rate Register 2 Bit H'FF89 SCI2, Smart Card Interface 2 : 7 6 5 4 3 2 1 0 Initial value : 1 1 1 1 1 1 1 1 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Sets the serial transfer bit rate Note: For details, see section 14.2.8, Bit Rate Register (BRR). Rev.6.00 Sep.
Appendix B Internal I/O Registers SCR2—Serial Control Register 2 Bit : H'FF8A SCI2 7 6 5 4 3 2 1 0 TIE RIE TE RE MPIE TEIE CKE1 CKE0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Clock Enable 0 0 1 1 0 1 Asynchronous mode Synchronous mode Asynchronous mode Synchronous mode Asynchronous mode Synchronous mode Asynchronous mode Synchronous mode Internal clock/SCK pin functions as I/O port Internal clock/SCK pin functions as serial clo
Appendix B Internal I/O Registers SCR2—Serial Control Register 2 Bit : H'FF8A Smart Card Interface 2 7 6 5 4 3 2 1 0 TIE RIE TE RE MPIE TEIE CKE1 CKE0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Clock Enable SCMR SMR SMIF GM SCR setting CKE1 0 CKE0 SCK pin function See SCI specification 1 0 0 0 Operates as port I/O pin 1 0 0 1 Clock output as SCK output pin 1 1 0 0 Fixed-low output as SCK output pin 1 1 0 1 C
Appendix B Internal I/O Registers TDR2—Transmit Data Register 2 Bit H'FF8B SCI2, Smart Card Interface 2 : 7 6 5 4 3 2 1 0 Initial value : 1 1 1 1 1 1 1 1 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Stores data for serial transmission Rev.6.00 Sep.
Appendix B Internal I/O Registers SSR2—Serial Status Register 2 Bit : H'FF8C 7 6 5 4 3 2 1 0 TDRE RDRF ORER FER PER TEND MPB MPBT Initial value : 1 0 0 0 0 1 0 0 Read/Write : R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R R R/W SCI2 Multiprocessor Bit Transfer 0 Data with a 0 multiprocessor bit is transmitted 1 Data with a 1 multiprocessor bit is transmitted Multiprocessor Bit 0 [Clearing condition] When data with a 0 multiprocessor bit is received 1 [Setting condition] W
Appendix B Internal I/O Registers SSR2—Serial Status Register 2 Bit : H'FF8C 7 6 5 4 3 2 1 0 TDRE RDRF ORER ERS PER TEND MPB MPBT Initial value : 1 0 0 0 0 1 0 0 Read/Write : R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* R R R/W Smart Card Interface 2 Multiprocessor Bit Transfer 0 Data with a 0 multiprocessor bit is transmitted 1 Data with a 1 multiprocessor bit is transmitted Multiprocessor Bit 0 [Clearing condition] When data with a 0 multiprocessor bit is received 1 [Se
Appendix B Internal I/O Registers RDR2—Receive Data Register 2 Bit H'FF8D SCI2, Smart Card Interface 2 : 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R R R R R R R R Stores received serial data SCMR2—Smart Card Mode Register 2 Bit : H'FF8E SCI2, Smart Card Interface 2 7 6 5 4 3 2 1 0 — — — — SDIR SINV — SMIF Initial value : 1 1 1 1 0 0 1 0 Read/Write : — — — — R/W R/W — R/W Smart Card Interface Mode Select 0 Smart card inte
Appendix B Internal I/O Registers ADDRAH ADDRAL ADDRBH ADDRBL ADDRCH ADDRCL ADDRDH ADDRDL — A/D Data Register AH — A/D Data Register AL — A/D Data Register BH — A/D Data Register BL — A/D Data Register CH — A/D Data Register CL — A/D Data Register DH — A/D Data Register DL Bit : 15 14 13 12 11 H'FF90 H'FF91 H'FF92 H'FF93 H'FF94 H'FF95 H'FF96 H'FF97 10 9 8 7 6 A/D Converter A/D Converter A/D Converter A/D Converter A/D Converter A/D Converter A/D Converter A/D Converter 5 4 3 2 1 0 AD9
Appendix B Internal I/O Registers ADCSR—A/D Control/Status Register Bit : H'FF98 A/D Converter 7 6 5 4 3 2 1 0 CH0 ADF ADIE ADST SCAN CKS CH2 CH1 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/(W)*1 R/W R/W R/W R/W R/W R/W R/W Channel Select Note: These bits select the analog input channels. Ensure that conversion is halted (ADST = 0) before making a channel selection.
Appendix B Internal I/O Registers ADCR—A/D Control Register Bit : H'FF99 A/D Converter 7 6 5 4 3 2 1 0 TRGS1 TRGS0 — — CKS1 CH3 — — Initial value : 0 0 1 1 1 1 1 1 Read/Write : R/W R/W — — R/W R/W — — Channel Select Reserved Only 1 should be written to this bit Clock Select Bit 3 ADCSR Bit 3 CKS1 CKS 0 0 Conversion time = 530 states (max) 1 Conversion time = 68 states (max) 0 Conversion time = 266 states (max) 1 Conversion time = 134 states (max) 1 Descr
Appendix B Internal I/O Registers DADR0—D/A Data Register 0 DADR1—D/A Data Register 1 Bit H'FFA4 H'FFA5 D/A Converter D/A Converter : 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Stores data for D/A conversion Rev.6.00 Sep.
Appendix B Internal I/O Registers DACR01—D/A Control Register 01 Bit : H'FFA6 D/A Converter 7 6 5 4 3 2 1 0 DAOE1 DAOE0 DAE — — — — — Initial value : 0 0 0 1 1 1 1 1 Read/Write : R/W R/W R/W — — — — — D/A Output Enable 0 0 Analog output DA0 is disabled 1 Channel 0 D/A conversion is enabled Analog output DA0 is enabled D/A Output Enable 1 0 Analog output DA1 is disabled 1 Channel 1 D/A conversion is enabled Analog output DA1 is enabled D/A Conversion Control DAO
Appendix B Internal I/O Registers PFCR2—Port Function Control Register 2 Bit : 7 H'FFAC 5 6 4 WAITPS BREQOPS CS167E CS25E Initial value : 0 0 1 1 Read/Write : R/W R/W R/W R/W Ports 3 2 1 0 ASOD — — — R/W 0 0 0 R R R AS Output Disable 0 PF6 is designated as AS output pin 1 PF6 is designated as I/O port, and does not function as AS output pin Note: This bit is valid in modes 4 to 6.
Appendix B Internal I/O Registers TCR0—Time Control Register 0 TCR1—Time Control Register 1 Bit : H'FFB0 H'FFB1 8-Bit Timer Channel 0 8-Bit Timer Channel 1 7 6 5 4 3 2 1 0 CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W Clock Select 0 0 1 1 0 1 0 Clock input disabled 1 Internal clock: counted at falling edge of ø/8 0 Internal clock: counted at falling edge of ø/64 1 Internal clock: co
Appendix B Internal I/O Registers TCSR0—Timer Control/Status Register 0 TCSR1—Timer Control/Status Register 1 TCSR0 Bit : Initial value : Read/Write : TCSR1 Bit : H'FFB2 H'FFB3 8-Bit Timer Channel 0 8-Bit Timer Channel 1 7 6 5 4 3 2 1 0 CMFB CMFA OVF ADTE OS3 OS2 OS1 OS0 0 0 0 0 0 0 0 0 R/(W)* R/(W)* R/(W)* R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 CMFB CMFA OVF — OS3 OS2 OS1 OS0 Initial value : 0 0 0 1 0 0 0 0 Read/Write : R/(W)* R/(W)* R/(W)* —
Appendix B Internal I/O Registers TCORA0—Time Constant Register A0 TCORA1—Time Constant Register A1 H'FFB4 H'FFB5 8-Bit Timer Channel 0 8-Bit Timer Channel 1 TCORA0 Bit TCORA1 : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W TCORB0—Time Constant Register B0 TCORB1—Time Constant Register B1 H'FFB6 H'FFB7 8-Bit Timer Channel 0 8-Bit Timer Channel 1 TCO
Appendix B Internal I/O Registers TCSR—Timer Control/Status Register Bit : Initial value : Read/Write*1 : H'FFBC (W), H'FFBC (R) WDT 7 6 5 4 3 2 1 0 OVF WT/IT TME — — CKS2 CKS1 CKS0 0 R/(W)*2 0 0 1 1 0 0 0 R/W R/W — — R/W R/W R/W Clock Select CKS2 CKS1 CKS0 0 0 1 1 0 1 Clock Overflow period* (when φ = 20 MHz) 0 φ/2 (Initial value) 25.6 µs 1 φ/64 819.2 µs 0 φ/128 1.6 ms 1 φ/512 6.6 ms 0 φ/2048 26.2 ms 1 φ/8192 104.9 ms 0 φ/32768 419.
Appendix B Internal I/O Registers TCNT—Timer Counter Bit H'FFBC (W), H'FFBD (R) WDT : 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W RSTCSR—Reset Control/Status Register Bit : H'FFBE (W), H'FFBF (R) WDT 7 6 5 4 3 2 1 0 WOVF RSTE — — — — — — Initial value : 0 0 0 1 1 1 1 1 Read/Write : R/(W)* R/W R/W — — — — — Reserved This bit should be written with 0 Reset Enable 0 Reset signal is not generat
Appendix B Internal I/O Registers TSTR—Timer Start Register Bit : H'FFC0 TPU 7 6 5 4 3 2 1 0 — — CST5 CST4 CST3 CST2 CST1 CST0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : — — R/W R/W R/W R/W R/W R/W Counter Start 0 TCNTn count operation is stopped 1 TCNTn performs count operation (n = 5 to 0) Note: If 0 is written to the CST bit during operation with the TIOC pin designated for output, the counter stops but the TIOC pin output compare output level is retained.
Appendix B Internal I/O Registers FLMCR1—Flash Memory Control Register 1 H'FFC8 (H8S/2329B F-ZTAT, H8S/2328B F-ZTAT) Bit : Flash Memory 7 6 5 4 3 2 1 0 FWE SWE ESU PSU EV PV E P Initial value : —* 0 0 0 0 0 0 0 Read/Write : R R/W R/W R/W R/W R/W R/W R/W Program 0 Program mode cleared 1 Transition to program mode [Setting condition] When FWE = 1, SWE = 1, and PSU = 1 Erase 0 Erase mode cleared 1 Transition to erase mode [Setting condition] When FWE = 1, SWE = 1, a
Appendix B Internal I/O Registers FLMCR1—Flash Memory Control Register 1 (H8S/2326 F-ZTAT) Bit : Initial value : R/W : H'FFC8 Flash Memory 7 6 5 4 3 2 1 0 FWE SWE1 ESU1 PSU1 EV1 PV1 E1 P1 —*1 0 0 0 0 0 0 0 R R/W R/W R/W R/W R/W R/W R/W Program 1*2 0 1 Program mode cleared Transition to program mode [Setting condition] When FWE = 1, SWE1 = 1, and PSU1 = 1 Erase 1*2 0 Erase mode cleared 1 Transition to erase mode [Setting condition] When FWE = 1, SWE1 = 1, and ESU1 = 1
Appendix B Internal I/O Registers FLMCR2—Flash Memory Control Register 2 H'FFC9 (H8S/2329B F-ZTAT, H8S/2328B F-ZTAT) Flash Memory 7 6 5 4 3 2 1 0 FLER — — — — — — — Initial value : 0 0 0 0 0 0 0 0 Read/Write : R — — — — — — — Bit : Flash Memory Error 0 Flash memory is operating normally Flash memory program/erase protection (error protection) is disabled [Clearing condition] Reset or hardware standby mode 1 An error has occurred during flash memory programming/erasi
Appendix B Internal I/O Registers FLMCR2—Flash Memory Control Register 2 (H8S/2326 F-ZTAT) Bit : H'FFC9 Flash Memory 7 6 5 4 3 2 1 0 FLER SWE2 ESU2 PSU2 EV2 PV2 E2 P2 Initial value : 0 0 0 0 0 0 0 0 R/W R R/W R/W R/W R/W R/W R/W R/W : Program 2* 0 1 Program mode cleared Transition to program mode [Setting condition] When FWE = 1, SWE2 = 1, and PSU2 = 2 Erase 2* 0 Erase mode cleared 1 Transition to erase mode [Setting condition] When FWE = 1, SWE2 = 1, and ESU2 = 1 P
Appendix B Internal I/O Registers EBR1—Erase Block Register 1 H'FFCA (H8S/2329B F-ZTAT, H8S/2328B F-ZTAT) EBR2—Erase Block Register 2 H'FFCB (H8S/2329B F-ZTAT, H8S/2328B F-ZTAT) Bit : EBR1 Flash Memory Flash Memory 7 6 5 4 3 2 1 0 EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 EBR2 — — EB13* EB12* EB11 EB10 EB9 EB8 Initial value : 0 0 0 0 0 0 0 0 Read/Write : — —
Appendix B Internal I/O Registers EBR1—Erase Block Register 1 (H8S/2326 F-ZTAT) EBR2—Erase Block Register 2 (H8S/2326 F-ZTAT) Bit : EBR1 H'FFCA Flash Memory H'FFCB Flash Memory 7 6 5 4 3 2 1 0 EB7 EB6 EB5 EB4 EB3 EB2 EB1 EB0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W 7 6 5 4 3 2 1 0 Bit : EB15 EB14 EB13 EB12 EB11 EB10 EB9 EB8 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W
Appendix B Internal I/O Registers TCR0—Timer Control Register 0 Bit : 7 6 5 H'FFD0 4 3 TPU0 2 1 0 TPSC0 CCLR2 CCLR1 CCLR0 TPSC2 TPSC1 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W CKEG1 CKEG0 Time Prescaler 0 0 1 1 0 1 0 Internal clock: counts on φ/1 1 Internal clock: counts on φ/4 0 Internal clock: counts on φ/16 1 Internal clock: counts on φ/64 0 External clock: counts on TCLKA pin input 1 External clock: counts on TCLKB p
Appendix B Internal I/O Registers TMDR0—Timer Mode Register 0 Bit : H'FFD1 TPU0 7 6 5 4 3 2 1 0 — — BFB BFA MD3 MD2 MD1 MD0 Initial value : 1 1 0 0 0 0 0 0 Read/Write : — — R/W R/W R/W R/W R/W R/W Mode 0 0 0 1 1 0 1 1 * * 0 Normal operation 1 Reserved 0 PWM mode 1 1 PWM mode 2 0 Phase counting mode 1 1 Phase counting mode 2 0 Phase counting mode 3 1 Phase counting mode 4 * — * : Don’t care Notes: 1. MD3 is a reserved bit.
Appendix B Internal I/O Registers TIOR0H—Timer I/O Control Register 0H Bit : H'FFD2 TPU0 7 6 5 4 3 2 1 0 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W TGR0A I/O Control 0 0 0 1 1 0 1 0 TGR0A Output disabled is output 1 compare Initial output is 0 output 0 register 0 output at compare match 1 Toggle output at compare match 0 Output disabled 1 Initial output is 1 output 0 1 1 0 1 0
Appendix B Internal I/O Registers TIOR0L—Timer I/O Control Register 0L Bit H'FFD3 TPU0 : 7 6 5 4 3 2 1 0 : IOD3 IOD2 IOD1 IOD0 IOC3 IOC2 IOC1 IOC0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W TGR0C I/O Control 0 0 0 0 1 1 0 TGR0C Output disabled is output compare Initial output is register 0 output 1 1 0 1 0 0 Output disabled 1 Initial output is 1 output 0 0 1 1 1 * * * 1 output at compare match Toggle output at co
Appendix B Internal I/O Registers TIER0—Timer Interrupt Enable Register 0 Bit : H'FFD4 TPU0 7 6 5 4 3 2 1 0 TGIEA TTGE — — TCIEV TGIED TGIEC TGIEB Initial value : 0 1 0 0 0 0 0 0 Read/Write : R/W — — R/W R/W R/W R/W R/W TGR Interrupt Enable A 0 Interrupt request (TGIA) by TGFA bit disabled 1 Interrupt request (TGIA) by TGFA bit enabled TGR Interrupt Enable B 0 Interrupt request (TGIB) by TGFB bit disabled 1 Interrupt request (TGIB) by TGFB bit enabled TGR Interr
Appendix B Internal I/O Registers TSR0—Timer Status Register 0 Bit : Initial value : Read/Write : H'FFD5 7 6 5 4 3 2 1 0 — — — TCFV TGFD TGFC TGFB TGFA 1 1 0 0 0 0 0 0 — — — R/(W)* R/(W)* R/(W)* R/(W)* R/(W)* TPU0 Input Capture/Output Compare Flag A 0 [Clearing conditions] • When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 • When DMAC*1 is activated by TGIA interrupt while DTA bit of DMABCR in DMAC*1 is 1 • When 0 is written to TGFA after read
Appendix B Internal I/O Registers TCNT0—Timer Counter 0 Bit H'FFD6 TPU0 : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Up/down-counter* Note: * This timer counter can be used as an up/down-counter only in phase counting mode or when performing overflow/underflow counting on another channel. In other cases it functions as an up-counter.
Appendix B Internal I/O Registers TCR1—Timer Control Register 1 Bit : 7 6 5 H'FFE0 4 3 TPU1 2 1 0 TPSC0 — CCLR1 CCLR0 TPSC2 TPSC1 Initial value : 0 0 0 0 0 0 0 0 Read/Write : — R/W R/W R/W R/W R/W R/W R/W CKEG1 CKEG0 Time Prescaler 0 0 1 1 0 1 0 Internal clock: counts on φ/1 1 Internal clock: counts on φ/4 0 Internal clock: counts on φ/16 1 Internal clock: counts on φ/64 0 External clock: counts on TCLKA pin input 1 External clock: counts on TCLKB pin inp
Appendix B Internal I/O Registers TMDR1—Timer Mode Register 1 Bit : H'FFE1 TPU1 7 6 5 4 3 2 1 0 — — — — MD3 MD2 MD1 MD0 Initial value : 1 1 0 0 0 0 0 0 Read/Write : — — — — R/W R/W R/W R/W Mode 0 0 0 1 1 0 1 1 * * 0 Normal operation 1 Reserved 0 PWM mode 1 1 PWM mode 2 0 Phase counting mode 1 1 Phase counting mode 2 0 Phase counting mode 3 1 Phase counting mode 4 * — * : Don’t care Note: MD3 is a reserved bit.
Appendix B Internal I/O Registers TIOR1—Timer I/O Control Register 1 Bit : H'FFE2 TPU1 7 6 5 4 3 2 1 0 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W TGR1A I/O Control 0 0 0 0 1 1 0 TGR1A Output disabled is output compare Initial output is register 0 output 1 1 0 1 0 0 Output disabled 1 Initial output is 1 output 0 0 1 1 1 * * * 1 output at compare match Toggle output at compare
Appendix B Internal I/O Registers TIER1—Timer Interrupt Enable Register 1 Bit : H'FFE4 TPU1 7 6 5 4 3 2 1 0 TGIEA TTGE — TCIEU TCIEV — — TGIEB Initial value : 0 1 0 0 0 0 0 0 Read/Write : R/W — R/W R/W — — R/W R/W TGR Interrupt Enable A 0 Interrupt request (TGIA) by TGFA bit disabled 1 Interrupt request (TGIA) by TGFA bit enabled TGR Interrupt Enable B 0 Interrupt request (TGIB) by TGFB bit disabled 1 Interrupt request (TGIB) by TGFB bit enabled Overflow Interrup
Appendix B Internal I/O Registers TSR1—Timer Status Register 1 Bit : Initial value : Read/Write : H'FFE5 7 6 5 4 3 2 1 0 TCFD — TCFU TCFV — — TGFB TGFA 1 1 0 0 0 0 0 0 R — R/(W)* R/(W)* — — R/(W)* R/(W)* TPU1 Input Capture/Output Compare Flag A 0 [Clearing conditions] • When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 • When DMAC*1 is activated by TGIA interrupt while DTA bit of DMABCR in DMAC*1 is 1 • When 0 is written to TGFA after reading T
Appendix B Internal I/O Registers TCNT1—Timer Counter 1 Bit H'FFE6 TPU1 : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Up/down-counter* Note: * This timer counter can be used as an up/down-counter only in phase counting mode or when performing overflow/underflow counting on another channel. In other cases it functions as an up-counter.
Appendix B Internal I/O Registers TCR2—Timer Control Register 2 Bit : 7 6 5 H'FFF0 4 3 TPU2 2 1 0 TPSC0 — CCLR1 CCLR0 TPSC2 TPSC1 Initial value : 0 0 0 0 0 0 0 0 Read/Write : — R/W R/W R/W R/W R/W R/W R/W CKEG1 CKEG0 Time Prescaler 0 0 1 1 0 1 0 Internal clock: counts on φ/1 1 Internal clock: counts on φ/4 0 Internal clock: counts on φ/16 1 Internal clock: counts on φ/64 0 External clock: counts on TCLKA pin input 1 External clock: counts on TCLKB pin inp
Appendix B Internal I/O Registers TMDR2—Timer Mode Register 2 Bit : H'FFF1 TPU2 7 6 5 4 3 2 1 0 — — — — MD3 MD2 MD1 MD0 Initial value : 1 1 0 0 0 0 0 0 Read/Write : — — — — R/W R/W R/W R/W Mode 0 0 0 1 1 0 1 1 * * 0 Normal operation 1 Reserved 0 PWM mode 1 1 PWM mode 2 0 Phase counting mode 1 1 Phase counting mode 2 0 Phase counting mode 3 1 Phase counting mode 4 * — * : Don’t care Note: MD3 is a reserved bit.
Appendix B Internal I/O Registers TIOR2—Timer I/O Control Register 2 Bit : H'FFF2 TPU2 7 6 5 4 3 2 1 0 IOB3 IOB2 IOB1 IOB0 IOA3 IOA2 IOA1 IOA0 Initial value : 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W TGR2A I/O Control 0 0 0 1 0 TGR2A is output 1 compare 0 register Output disabled Initial output is 0 output 1 1 0 1 * 0 1 1 output at compare match Toggle output at compare match 0 Output disabled 1 Initial output is 1 output 0 1 1 0
Appendix B Internal I/O Registers TIER2—Timer Interrupt Enable Register 2 Bit : H'FFF4 TPU2 7 6 5 4 3 2 1 0 TTGE — TCIEU TCIEV — — TGIEB TGIEA Initial value : 0 1 0 0 0 0 0 0 Read/Write : R/W — R/W R/W — — R/W R/W TGR Interrupt Enable A 0 Interrupt request (TGIA) by TGFA bit disabled 1 Interrupt request (TGIA) by TGFA bit enabled TGR Interrupt Enable B 0 Interrupt request (TGIB) by TGFB bit disabled 1 Interrupt request (TGIB) by TGFB bit enabled Overflow Interru
Appendix B Internal I/O Registers TSR2—Timer Status Register 2 Bit : H'FFF5 TPU2 7 6 5 4 3 2 1 0 TCFD — TCFU TCFV — — TGFB TGFA Initial value : 1 1 0 0 0 0 0 0 Read/Write : R — R/(W)* R/(W)* — — R/(W)* R/(W)* Input Capture/Output Compare Flag A 0 [Clearing conditions] • When DTC is activated by TGIA interrupt while DISEL bit of MRB in DTC is 0 • When DMAC*1 is activated by TGIA interrupt while DTA bit of DMABCR in DMAC*1 is 1 • When 0 is written to TGFA after reading
Appendix B Internal I/O Registers TCNT2—Timer Counter 2 Bit H'FFF6 TPU2 : 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Initial value : 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Read/Write : R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Up/down-counter* Note: * This timer counter can be used as an up/down-counter only in phase counting mode or when performing overflow/underflow counting on another channel. In other cases it functions as an up-counter.
Appendix C I/O Port Block Diagrams Appendix C I/O Port Block Diagrams C.
Appendix C I/O Port Block Diagrams R Q D P1nDDR C WDDR1 Reset R Q D P1nDR C P1n WDR1 RDR1 Internal data bus Reset PPG module Pulse output enable Pulse output TPU module Output compare output/ PWM output enable Output compare output/ PWM output RPOR1 Input capture input External clock input Legend: WDDR1: WDR1: RDR1: RPOR1: Write to P1DDR Write to P1DR Read P1DR Read port 1 Note: n = 2, 3, 5, 7 Figure C.1 (b) Port 1 Block Diagram (Pins P12, P13, P15, and P17) Rev.6.00 Sep.
Appendix C I/O Port Block Diagrams R Q D P1nDDR C WDDR1 Reset Internal data bus Reset R Q D P1nDR C P1n WDR1 PPG module Pulse output enable Pulse output TPU module Output compare output/ PWM output enable Output compare output/ PWM output RDR1 RPOR1 Input capture input Legend: WDDR1: WDR1: RDR1: RPOR1: Write to P1DDR Write to P1DR Read P1DR Read port 1 Note: n = 4 or 6 Figure C.1 (c) Port 1 Block Diagram (Pins P14 and P16) Rev.6.00 Sep.
Appendix C I/O Port Block Diagrams C.2 Port 2 R Q D P2nDDR C WDDR2 Reset R Q D P2nDR C P2n WDR2 Internal data bus Reset PPG module Pulse output enable Pulse output TPU module Output compare output/ PWM output enable Output compare output/ PWM output RDR2 RPOR2 Input capture input Legend: WDDR2: WDR2: RDR2: RPOR2: Write to P2DDR Write to P2DR Read P2DR Read port 2 Note: n = 0 or 1 Figure C.2 (a) Port 2 Block Diagram (Pins P20 and P21) Rev.6.00 Sep.
Appendix C I/O Port Block Diagrams R Q D P2nDDR C WDDR2 Reset R Q D P2nDR C P2n WDR2 Internal data bus Reset PPG module Pulse output enable Pulse output TPU module Output compare output/ PWM output enable Output compare output/ PWM output RDR2 RPOR2 Input capture input 8-bit timer module Counter external reset input Legend: WDDR2: WDR2: RDR2: RPOR2: Write to P2DDR Write to P2DR Read P2DR Read port 2 Note: n = 2 or 4 Figure C.2 (b) Port 2 Block Diagram (Pins P22 and P24) Rev.6.00 Sep.
Appendix C I/O Port Block Diagrams R Q D P2nDDR C WDDR2 Reset R Q D P2nDR C P2n WDR2 Internal data bus Reset PPG module Pulse output enable Pulse output TPU module Output compare output/ PWM output enable Output compare output/ PWM output RDR2 RPOR2 Input capture input 8-bit timer module Counter external clock inpu Legend: WDDR2: WDR2: RDR2: RPOR2: Write to P2DDR Write to P2DR Read P2DR Read port 2 Note: n = 3 or 5 Figure C.2 (c) Port 2 Block Diagram (Pins P23 and P25) Rev.6.00 Sep.
Appendix C I/O Port Block Diagrams R Q D P2nDDR C WDDR2 Reset R Q D P2nDR C P2n WDR2 Internal data bus Reset PPG module Pulse output enable Pulse output 8-bit timer module Compare match output enable Compare match output TPU module Output compare output/ PWM output enable Output compare output/ PWM output RDR2 RPOR2 Input capture input Legend: WDDR2: WDR2: RDR2: RPOR2: Write to P2DDR Write to P2DR Read P2DR Read port 2 Note: n = 6 or 7 Figure C.
Appendix C I/O Port Block Diagrams C.3 Port 3 R Q D P3nDDR C WDDR3 *1 Reset R Q D P3nDR C P3n Internal data bus Reset WDR3 Reset *2 R Q D P3nODR C WODR3 RODR3 SCI module Serial transmit enable Serial transmit data RDR3 RPOR3 Legend: WDDR3: WDR3: WODR3: RDR3: RPOR3: RODR3: Write to P3DDR Write to P3DR Write to P3ODR Read P3DR Read port 3 Read P3ODR Notes: n = 0 or 1 1. Output enable signal 2. Open drain control signal Figure C.3 (a) Port 3 Block Diagram (Pins P30 and P31) Rev.6.00 Sep.
Appendix C I/O Port Block Diagrams R Q D P3nDDR C WDDR3 *1 Reset R Q D P3nDR C P3n Internal data bus Reset WDR3 *2 Reset R Q D P3nODR C WODR3 RODR3 RDR3 SCI module Serial receive data enable RPOR3 Serial receive data Legend: WDDR3: WDR3: WODR3: RDR3: RPOR3: RODR3: Write to P3DDR Write to P3DR Write to P3ODR Read P3DR Read port 3 Read P3ODR Notes: n = 2 or 3 1. Output enable signal 2. Open drain control signal Figure C.3 (b) Port 3 Block Diagram (Pins P32 and P33) Rev.6.00 Sep.
Appendix C I/O Port Block Diagrams R Q D P3nDDR C WDDR3 *1 Reset R Q D P3nDR C P3n Internal data bus Reset WDR3 Reset *2 R Q D P3nODR C WODR3 RODR3 SCI module Serial clock output enable Serial clock output RDR3 Serial clock input enable RPOR3 Legend: WDDR3: WDR3: WODR3: RDR3: RPOR3: RODR3: Write to P3DDR Write to P3DR Write to P3ODR Read P3DR Read port 3 Read P3ODR Serial clock input Notes: n = 4 or 5 1. Output enable signal 2. Open drain control signal Figure C.
Appendix C I/O Port Block Diagrams Port 4 RPOR4 P4n Internal data bus C.4 A/D converter module Analog input Legend: RPOR4: Read port 4 Note: n = 0 to 5 RPOR4 P4n Internal data bus Figure C.4 (a) Port 4 Block Diagram (Pins P40 to P45) A/D converter module Analog input D/A converter module Output enable Analog output Legend: RPOR4: Read port 4 Note: n = 6 or 7 Figure C.4 (b) Port 4 Block Diagram (Pins P46 and P47) Rev.6.00 Sep.
Appendix C I/O Port Block Diagrams C.5 Port 5 R Q D P50DDR C WDDR0 Reset Internal data bus Reset R Q D P50DR C P50 WDR5 SCI module Serial transmit output enable Serial transmit data RDR5 RPOR5 Legend: WDDR5: WDR5: RDR5: RPOR5: IRQPAS: IRQPAS IRQ4 interrupt input Write to P5DDR Write to P5DR Read P5DR Read port 5 IRQ port switching select Figure C.5 (a) Port 5 Block Diagram (Pin P50) Rev.6.00 Sep.
Appendix C I/O Port Block Diagrams R Q D P51DDR C WDDR5 Reset Internal data bus Reset R Q D P51DR C P51 WDR5 SCI module Serial receive data enable RDR5 RPOR5 Serial receive data Legend: WDDR5: WDR5: RDR5: RPOR5: IRQPAS: IRQPAS IRQ5 interrupt input Write to P5DDR Write to P5DR Read P5DR Read port 5 IRQ port switching select Figure C.5 (b) Port 5 Block Diagram (Pin P51) Rev.6.00 Sep.
Appendix C I/O Port Block Diagrams R Q D P52DDR C WDDR5 Reset R Q D P52DR C P52 WDR5 Internal data bus Reset SCI module Serial clock output enable Serial clock output Serial clock input enable RDR5 RPOR5 Serial clock input Legend: WDDR5: WDR5: RDR5: RPOR5: IRQPAS: IRQPAS IRQ6 interrupt input Write to P5DDR Write to P5DR Read P5DR Read port 5 IRQ port switching select Figure C.5 (c) Port 5 Block Diagram (Pin P52) Rev.6.00 Sep.
Appendix C I/O Port Block Diagrams R Q D P53DDR C WDDR5 Reset P53 Modes 4 to 6 Internal data bus Reset Bus controller R Q D P53DR C WDR5 Bus request output enable Bus request output RDR5 BREQOPS RPOR5 A/D converter A/D converter external trigger input IRQPAS IRQ7 interrupt input Modes 4 to 6 WAITPS Wait input pin enable Bus controller Wait input Legend: WDDR5: WDR5: RDR5: RPOR5: IRQPAS: WAITPS: BREQOPS: Write to P5DDR Write to P5DR Read P5DR Read port 5 IRQ port switching select Wait pin select BREQ
Appendix C I/O Port Block Diagrams C.6 Port 6 R Q D P60DDR C WDDR6 Mode 7 P60 Modes 4 to 6 Reset Internal data bus Reset R Q D P60DR C WDR6 Bus controller Chip select RDR6 CS25E RPOR6 DMA controller* DMA request input Legend: WDDR6: WDR6: RDR6: RPOR6: CS25E: Write to P6DDR Write to P6DR Read P6DR Read port 6 CS25 enable Note: * The DMAC is not supported in the H8S/2321. Figure C.6 (a) Port 6 Block Diagram (Pin P60) Rev.6.00 Sep.
Appendix C I/O Port Block Diagrams R Q D P61DDR C WDDR6 Reset Mode 7 Internal data bus Reset R Q D P61DR C P61 Modes 4 to 6 WDR6 CS25E Bus controller Chip select DMA controller* DMA transfer end enable DMA transfer end RDR6 RPOR6 Legend: WDDR6: WDR6: RDR6: RPOR6: CS25E: Write to P6DDR Write to P6DR Read P6DR Read port 6 CS25 enable Note: * The DMAC is not supported in the H8S/2321. Figure C.6 (b) Port 6 Block Diagram (Pin P61) Rev.6.00 Sep.
Appendix C I/O Port Block Diagrams R Q D P62DDR C WDDR6 Reset Internal data bus Reset R Q D P62DR C P62 WDR6 RDR6 RPOR6 DMA controller* DMA request input Legend: WDDR6: WDR6: RDR6: RPOR6: Write to P6DDR Write to P6DR Read P6DR Read port 6 Note: * The DMAC is not supported in the H8S/2321. Figure C.6 (c) Port 6 Block Diagram (Pin P62) Rev.6.00 Sep.
Appendix C I/O Port Block Diagrams R Q D P63DDR C WDDR6 Reset R Q D P63DR C P63 Internal data bus Reset WDR6 DMA controller* DMA transfer end enable DMA transfer end RDR6 RPOR6 Legend: WDDR6: WDR6: RDR6: RPOR6: Write to P6DDR Write to P6DR Read P6DR Read port 6 Note: * The DMAC is not supported in the H8S/2321. Figure C.6 (d) Port 6 Block Diagram (Pin P63) Rev.6.00 Sep.
Appendix C I/O Port Block Diagrams R Q D P6nDDR C WDDR6 Reset R Q D P6nDR C P6n Internal data bus Reset WDR6 RDR6 RPOR6 IRQm interrupt input Legend: WDDR6: WDR6: RDR6: RPOR6: Write to P6DDR Write to P6DR Read P6DR Read port 6 Note: n = 4 or 5 m = 0 or 1 Figure C.6 (e) Port 6 Block Diagram (Pins P64 and P65) Rev.6.00 Sep.
Appendix C I/O Port Block Diagrams R Q D P6nDDR C WDDR6 Mode 7 P6n Modes 4 to 6 Reset R Q D P6nDR C WDR6 Internal data bus Reset Bus controller Chip select RDR6 RPOR6 IRQm interrupt input Legend: WDDR6: WDR6: RDR6: RPOR6: CS167E: CS167E Write to P6DDR Write to P6DR Read P6DR Read port 6 CS167 enable Note: n = 6 or 7 m = 2 or 3 Figure C.6 (f) Port 6 Block Diagram (Pins P66 and P67) Rev.6.00 Sep.
Appendix C I/O Port Block Diagrams Port A R Q D PAnPCR C WPCRA RPCRA Reset Modes 4 and 5 R Q D PAnDDR C WDDRA *1 Reset Mode 7 Modes 4 to 6 PAn R Q D PAnDR C WDRA *2 Reset R Q D PAnODR C WODRA RODRA RDRA RPORA Legend: WDDRA: WDRA: WODRA: WPCRA: RDRA: RPORA: RODRA: RPCRA: Write to PADDR Write to PADR Write to PAODR Write to PAPCR Read PADR Read port A Read PAODR Read PAPCR Notes: n = 0 to 3 1. Output enable signal 2. Open drain control signal Figure C.
Appendix C I/O Port Block Diagrams Reset WPCRA RPCRA Internal address bus R Q D PA4PCR C Internal data bus Modes 6 and 7 Reset Modes 4 and 5 R Q D PA4DDR C WDDRA *1 A20E Reset Mode 7 Modes 4 to 6 PA4 R Q D PA4DR C WDRA Reset *2 R Q D PA4ODR C WODRA RODRA RDRA RPORA IRQPAS Legend: WDDRA: WDRA: WODRA: WPCRA: RDRA: RPORA: RODRA: RPCRA: A20E: IRQPAS: Write to PADDR Write to PADR Write to PAODR Write to PAPCR Read PADR Read port A Read PAODR Read PAPCR Address 20 enable IRQ port switching sele
Appendix C I/O Port Block Diagrams R Q D PAnPCR C WPCRA RPCRA Internal address bus Reset Internal data bus Modes 4 to 7 Reset R Q D PAnDDR C WDDRA *1 Reset Mode 7 PAn Modes 4 to 6 R Q D PAnDR C WDRA Reset *2 Mode 7 AmE R Q D PAnODR C WODRA RODRA RDRA RPORA IRQPAS Legend: WDDRA: WDRA: WODRA: WPCRA: RDRA: RPORA: RODRA: RPCRA: AmE: IRQPAS: Write to PADDR Write to PADR Write to PAODR Write to PAPCR Read PADR Read port A Read PAODR Read PAPCR Address output enable IRQ port switching select IRQn i
Appendix C I/O Port Block Diagrams Port B R Q D PBnPCR C WPCRB RPCRB Internal address bus Reset Modes 6 and 7 Internal data bus C.8 Modes 4 and 5 Reset R Q D PBnDDR C WDDRB Reset Mode 7 Modes 4 to 6 PBn R Q D PBnDR C WDRB RDRB RPORB Legend: WDDRB: WDRB: WPCRB: RDRB: RPORB: RPCRB: Write to PBDDR Write to PBDR Write to PBPCR Read PBDR Read port B Read PBPCR Note: n = 0 to 7 Figure C.8 Port B Block Diagram (Pins PB0 to PB7) Rev.6.00 Sep.
Appendix C I/O Port Block Diagrams Port C R Q D PCnPCR C WPCRC RPCRC Modes 4 and 5 Reset R Q D PCnDDR C WDDRC Reset Mode 7 Modes 4 to 6 PCn R Q D PCnDR C WDRC RDRC RPORC Legend: WDDRC: WDRC: WPCRC: RDRC: RPORC: RPCRC: Write to PCDDR Write to PCDR Write to PCPCR Read PCDR Read port C Read PCPCR Note: n = 0 to 7 Figure C.9 Port C Block Diagram (Pins PC0 to PC7) Rev.6.00 Sep. 27, 2007 Page 1244 of 1268 REJ09B0220-0600 Internal address bus Reset Modes 6 and 7 Internal data bus C.
Appendix C I/O Port Block Diagrams Port D R Q D PDnPCR C WPCRD RPCRD Internal lower data bus Reset Internal upper data bus C.
Appendix C I/O Port Block Diagrams C.11 Port E WPCRE RPCRE Internal lower data bus R Q D PEnPCR C Internal upper data bus Reset Mode 7 Bus controller 8-bit bus mode Reset External address write Modes 4 to 6 PEn Modes 4 to 6 R Q D PEnDDR C WDDRE Reset R Q D PEnDR C WDRE RDRE RPORE Legend: WDDRE: WDRE: WPCRE: RDRE: RPORE: RPCRE: Write to PEDDR Write to PEDR Write to PEPCR Read PEDR Read port E Read PEPCR External address lower read Note: n = 0 to 7 Figure C.
Appendix C I/O Port Block Diagrams Port F Reset R Q D PF0DDR C Internal data bus C.12 WDDRF Bus controller BRLE bit Modes 4 to 6 Reset R Q D PF0DR C PF0 WDRF RDRF RPORF Bus request input Legend: WDDRF: WDRF: RDRF: RPORF: Write to PFDDR Write to PFDR Read PFDR Read port F Figure C.12 (a) Port F Block Diagram (Pin PF0) Rev.6.00 Sep.
Appendix C I/O Port Block Diagrams R Q D PF1DDR C WDDRF Reset R Q D PF1DR C PF1 Internal data bus Reset WDRF Modes 4 to 6 Bus controller BRLE bit Bus request acknowledge output RDRF RPORF Legend: WDDRF: WDRF: RDRF: RPORF: Write to PFDDR Write to PFDR Read PFDR Read port F Figure C.12 (b) Port F Block Diagram (Pin PF1) Rev.6.00 Sep.
Reset R Q D PF2DDR C WDDRF Internal data bus Appendix C I/O Port Block Diagrams Reset PF2 Modes 4 to 6 R Q D PF2DR C WDRF Bus controller Modes 4 to 6 Bus request output enable Bus request output RDRF RPORF Wait input LCAS output enable* Modes 4 and 6 Legend: WDDRF: WDRF: RDRF: RPORF: WAITPS: BREQOPS: LCAS output* Wait enable WAITPS Write to PFDDR Write to PFDR Read PFDR Read port F WAIT pin select BREQO pin select BREQOPS Note: * Not supported in the H8S/2321. Figure C.
Appendix C I/O Port Block Diagrams Modes 4 to 6 R Q D PF3DDR C WDDRF Mode 7 PF3 Modes 4 to 6 Reset R Q D PF3DR C Internal data bus Reset WDRF Interrupt controller LWROD Bus controller LWR output RDRF RPORF Legend: WDDRF: WDRF: RDRF: RPORF: LWROD: Write to PFDDR Write to PFDR Read PFDR Read port F LWR output disable Figure C.12 (d) Port F Block Diagram (Pin PF3) Rev.6.00 Sep.
Appendix C I/O Port Block Diagrams Modes 4 to 6 R Q D PF4DDR C WDDRF Mode 7 PF4 Modes 4 to 6 Reset R Q D PF4DR C Internal data bus Reset WDRF Bus controller HWR output RDRF RPORF Legend: WDDRF: WDRF: RDRF: RPORF: Write to PFDDR Write to PFDR Read PFDR Read port F Figure C.12 (e) Port F Block Diagram (Pin PF4) Rev.6.00 Sep.
Appendix C I/O Port Block Diagrams Modes 4 to 6 R Q D PF5DDR C WDDRF Mode 7 PF5 Modes 4 to 6 Reset Internal data bus Reset R Q D PF5DR C WDRF Bus controller RD output RDRF RPORF Legend: WDDRF: WDRF: RDRF: RPORF: Write to PFDDR Write to PFDR Read PFDR Read port F Figure C.12 (f) Port F Block Diagram (Pin PF5) Rev.6.00 Sep.
Appendix C I/O Port Block Diagrams Modes 4 to 6 R Q D PF6DDR C WDDRF Mode 7 PF6 Modes 4 to 6 Reset Internal data bus Reset R Q D PF6DR C WDRF Interrupt controller ASOD Bus controller AS output RDRF RPORF Legend: WDDRF: WDRF: RDRF: RPORF: ASOD: Write to PFDDR Write to PFDR Read PFDR Read port F AS output disable Figure C.12 (g) Port F Block Diagram (Pin PF6) Rev.6.00 Sep.
Appendix C I/O Port Block Diagrams Modes 4 to 6 Mode 7 S R Q D PF7DDR C WDDRF Reset Internal data bus Reset R Q D PF7DR C PF7 WDRF φ RDRF RPORF Legend: WDDRF: WDRF: RDRF: RPORF: Write to PFDDR Write to PFDR Read PFDR Read port F Figure C.12 (h) Port F Block Diagram (Pin PF7) Rev.6.00 Sep.
Appendix C I/O Port Block Diagrams Port G Reset R Q D PG0DDR C WDDRG Reset R Q D PG0DR C PG0 Internal data bus C.13 WDRG Modes 4 to 6 Bus controller CAS enable* CAS output* RDRG RPORG Legend: WDDRG: WDRG: RDRG: RPORG: Write to PGDDR Write to PGDR Read PGDR Read port G Note: * Not supported in the H8S/2321. Figure C.13 (a) Port G Block Diagram (Pin PG0) Rev.6.00 Sep.
Appendix C I/O Port Block Diagrams R Q D PGnDDR C WDDRG Reset Mode 7 PGn Modes 4 to 6 R Q D PGnDR C Internal data bus Reset Interrupt controller WDRG CS25E Bus controller Chip select RDRG RPORG Legend: WDDRG: WDRG: RDRG: RPORG: CS25E: Write to PGDDR Write to PGDR Read PGDR Read port G CS25 enable Note: n = 1 or 2 Figure C.13 (b) Port G Block Diagram (Pins PG1 and PG2) Rev.6.00 Sep.
Appendix C I/O Port Block Diagrams R Q D PG3DDR C WDDRG Reset Mode 7 PG3 Modes 4 to 6 R Q D PG3DR C Internal data bus Reset Interrupt controller WDRG CS167E Bus controller Chip select RDRG RPORG Legend: WDDRG: WDRG: RDRG: RPORG: CS167E: Write to PGDDR Write to PGDR Read PGDR Read port G CS167 enable Figure C.13 (c) Port G Block Diagram (Pin PG3) Rev.6.00 Sep.
Appendix C I/O Port Block Diagrams Modes 6 and 7 S R Q D PG4DDR C WDDRG Mode 7 PG4 Modes 4 to 6 Reset Internal data bus Modes 4 and 5 Reset R Q D PG4DR C WDRG Bus controller Chip select RDRG RPORG Legend: WDDRG: WDRG: RDRG: RPORG: Write to PGDDR Write to PGDR Read PGDR Read port G Figure C.13 (d) Port G Block Diagram (Pin PG4) Rev.6.00 Sep.
Appendix D Pin States Appendix D Pin States D.1 Port States in Each Mode Table D.
Appendix D Pin States MCU Port Name Operating Pin Name Mode Reset Hardware Standby Mode P67/CS7 T T 4 to 6 P66/CS6 Software Standby Mode Bus-Released State Program Execution State Sleep Mode [CS167E = 0], [CS167E = 0] [CS167E · DDR = 1] kept kept [CS167E · DDR = 1] [CS167E · DDR · kept OPE = 1] [CS167E · DDR = 1] T T [CS167E · DDR · OPE = 1] H [CS167E = 0] I/O port [CS167E · DDR = 1] Input port [CS167E · DDR = 1] CS7 to CS6 7 T T kept kept I/O port P65 to P62 4 to 7 T T kept kept I/
Appendix D Pin States MCU Port Name Operating Pin Name Mode Reset Hardware Standby Mode PA4/A20 L T 4, 5 Software Standby Mode Bus-Released State Program Execution State Sleep Mode [A20E · DDR = 1] kept [A20E · DDR = 1] kept [A20E · DDR = 1] Output port [A20E · OPE = 1] T [A20E+A20E · DDR = 1] T [A20E+A20E · DDR = 1] Address output [A20E = 0] kept [A20E = 0] I/O port [A20E · DDR = 1] kept [A20E · DDR = 1] Output port [A20E · DDR = 1] T [A20E · DDR = 1] Address output [A20E · OPE = 1] k
Appendix D Pin States MCU Port Name Operating Pin Name Mode Reset Hardware Standby Mode Port C L T 4, 5 Software Standby Mode Bus-Released State Program Execution State Sleep Mode [OPE = 0] T T Address output T [DDR = 0] Input port [OPE = 1] kept 6 T T [DDR · OPE = 0] T [DDR · OPE = 1] kept Port D Port E 7 T T kept kept I/O port 4 to 6 T T T T Data bus 7 T T kept kept I/O port 4 to 8-bit 6 bus T T kept kept I/O port 16-bit T bus T T T Data bus T kept kept
Appendix D Pin States MCU Port Name Operating Pin Name Mode Reset Hardware Standby Mode PF3/LWR H T 4 to 6 Software Standby Mode Bus-Released State Program Execution State Sleep Mode [LWROD = 1] kept [LWROD = 1] kept [LWROD = 1] I/O port [LWROD · OPE = 1] [LWROD = 0] T T [LWROD = 0] LWR [LWROD · OPE = 1] H 7 1 PF2/LCAS* / 4 to 6 WAIT/ BREQO T T kept T T [LCASE* + BREQOE · BREQOPS + WAITE · WAITPS =0 kept kept [LCASE* + BREQOE · BREQOPS + WAITE · WAITPS =0 kept [LCASE* + BREQOE · BREQ
Appendix D Pin States MCU Port Name Operating Pin Name Mode Reset Hardware Standby Mode PF0/BREQ T T 4 to 6 Software Standby Mode Bus-Released State [BRLE=0] kept T [BRLE=1] T PG4/CS0 PG3/CS1 [BRLE = 0] I/O port [BRLE = 1] BREQ 7 T T kept kept I/O port 4, 5 H T [DDR · OPE = 0] T T [DDR = 0] Input port 6 T 7 T T kept kept I/O port 4 to 6 T T [CS167E = 0] kept [CS167E = 0] kept [CS167E = 0] I/O port [DDR · OPE = 1] H [DDR = 1] CS0 [CS167E · DDR = 1] [CS167E = 1] T T
Appendix D Pin States MCU Port Name Operating Pin Name Mode 3 PG0/CAS* 4 to 6 Reset Hardware Standby Mode T T Software Standby Mode 4 [DRAME* = 0] kept Bus-Released State T 4 Program Execution State Sleep Mode 4 [DRAME* = 0] Input port 4 [DRAME* · OPE = 1] T [DRAME* = 1] 3 CAS* 4 [DRAME* · OPE = 1] 3 CAS* 7 T T kept kept I/O port Legend: H: High level L: Low level T: High impedance kept: Input port becomes high-impedance, output port retains state DDR: Data direction register OPE: Outp
Appendix E Product Lineup Appendix E Product Lineup Table E.
Appendix F Package Dimensions Appendix F Package Dimensions The package dimension that is shown in the Renesas Semiconductor Package Data Book has priority. JEITA Package Code P-TQFP120-14x14-0.40 RENESAS Code PTQP0120LA-A Previous Code TFP-120/TFP-120V MASS[Typ.] 0.5g HD *1 D 90 61 91 NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET.
Appendix F Package Dimensions JEITA Package Code P-QFP128-14x20-0.50 RENESAS Code PRQP0128KB-A Previous Code FP-128B/FP-128BV MASS[Typ.] 1.7g HD *1 D 102 65 103 NOTE) 1. DIMENSIONS"*1"AND"*2" DO NOT INCLUDE MOLD FLASH 2. DIMENSION"*3"DOES NOT INCLUDE TRIM OFFSET. 64 HE b1 c ZE c1 *2 E bp 39 128 1 ZD Reference Dimension in Millimeters Symbol Min Terminal cross section 38 Index mark c A2 A F A1 θ e *3 y bp x L L1 M Detail F Figure F.2 FP-128B Package Dimensions Rev.6.
Renesas 16-Bit Single-Chip Microcomputer Hardware Manual H8S/2329 Group Publication Date: 1st Edition, March 1999 Rev.6.00, September 27, 2007 Published by: Sales Strategic Planning Div. Renesas Technology Corp. Edited by: Customer Support Department Global Strategic Communication Div. Renesas Solutions Corp. © 2007. Renesas Technology Corp., All rights reserved. Printed in Japan.
Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan RENESAS SALES OFFICES http://www.renesas.com Refer to "http://www.renesas.com/en/network" for the latest and detailed information. Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500, Fax: <1> (408) 382-7501 Renesas Technology Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.K.
H8S/2329 Group Hardware Manual 1753, Shimonumabe, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8668 Japan REJ09B0220-0600