Datasheet

Appendix B Internal I/O Registers
Rev.6.00 Sep. 27, 2007 Page 1121 of 1268
REJ09B0220-0600
DMACR0A—DMA Control Register 0A H'FF02 DMAC
(Not supported in H8S/2321)
DMACR0B—DMA Control Register 0B H'FF03 DMAC
(Not supported in H8S/2321)
DMACR1A—DMA Control Register 1A H'FF04 DMAC
(Not supported in H8S/2321)
DMACR1B—DMA Control Register 1B H'FF05 DMAC
(Not supported in H8S/2321)
15
DTSZ
0
R/W
14
SAID
0
R/W
13
SAIDE
0
R/W
12
BLKDIR
0
R/W
11
BLKE
0
R/W
8
—
0
R/W
10
—
0
R/W
9
—
0
R/W
0
1
Byte-size transfer
Word-size transfer
Data Transfer Size
0
1
Source Address Increment/Decrement
0
1
0
1
MARA is fixed
MARA is incremented after a data transfer
MARA is fixed
MARA is decremented after a data transfer
0
1
Block Direction/Block Enable
Reserved
Only 0 should be written
to these bits
0
1
0
1
Transfer in normal mode
Transfer in block transfer mode, destination side is block area
Transfer in normal mode
Transfer in block transfer mode, source side is block area
Full address mode
Bit
DMACRA
Initial value
Read/Write
:
:
:
: