Datasheet

Section 5 Interrupt Controller
Rev.6.00 Sep. 27, 2007 Page 140 of 1268
REJ09B0220-0600
5.6.2 Block Diagram
Figure 5.9 shows a block diagram of the DTC, DMAC
*
, and interrupt controller.
Note: * The DMAC is not supported in the H8S/2321.
DMAC
*
Selection
circuit
DTCER
DTVECR
Control logic
Determination of
priority
CPU
DTC
DTC activation
request vector
number
Clear signal
CPU interrupt
request vector
number
Select
signal
Interrupt
request
Interrupt source
clear signal
IRQ
interrupt
Note: * The DMAC is not supported in the H8S/2321.
On-chip
supporting
module
Disable signal
Clear signal
Clear signal
Interrupt controller
I, I2 to I0
SWDTE
clear signal
Figure 5.9 Interrupt Control for DTC and DMAC
*