Datasheet

Rev. 3.00 Mar 17, 2006 page x of l
Item Page Revision (See Manual for Details)
17.4 Operation 769 Description added
[2] Set the DAOE0 bit ... The output value is expressed by the
following formula:
256
DADR contents
× Vref
19.12 Usage Notes
Figure 19.12 Power-
On/Off Timing
(H8S/2678Group)
804 Figure 19.12 amended
φ
VCC
FWE
t
OSC1
Min 0 µs
Min 0 µs
t
MDS
*
3
t
MDS
*
3
MD2 to MD0
*
1
RES
SWE bit
SWE set
SWE cleared
Programming/
erasing
possible
Wait time: x Wait time: 100 µs
SWE set
SWE cleared
φ
VCC
FWE
t
OSC1
Min 0 µs
MD2 to MD0
*
1
RES
SWE bit
(2) User Program Mode
(1) Boot Mode
Programming/
erasing
possible
Wait time: x Wait time: 100 µs
t
MDS
*
3
Section 20 Masked
ROM
810 Description amended
The operating mode enables or disables the on-chip ROM.
The operating mode is selected by the mode setting pins,
such as the FWE and MD
2 to MD0 pins shown in table 3.1. ...