Datasheet

Section 6 Bus Controller (BSC)
Rev. 3.00 Mar 17, 2006 page 124 of 926
REJ09B0283-0300
Name Symbol I/O Function
Chip select 5/row address
strobe 5/SDRAMφ
*
CS5/
RAS5/
*
SDRAMφ
*
Output Strobe signal indicating that area 5 is selected,
DRAM row address strobe signal when area 5
is DRAM interface space, or dedicated clock
signal for the synchronous DRAM when the
synchronous DRAM interface is selected.
Chip select 6 CS6 Output Strobe signal indicating that area 6 is selected.
Chip select 7 CS7 Output Strobe signal indicating that area 7 is selected.
Upper column address
strobe/upper data mask
enable
UCAS/
DQMU
*
Output 16-bit DRAM interface space upper column
address strobe signal, 8-bit DRAM interface
space column address strobe signal, upper
data mask signal of 16-bit synchronous DRAM
interface space, or data mask signal of 8-bit
synchronous DRAM interface space.
Lower column address
strobe/lower data mask
enable
LCAS/
DQML
*
Output 16-bit DRAM interface space lower column
address strobe signal or lower data mask signal
for the 16-bit synchronous DRAM interface
space.
Output enable/clock
enable
OE/CKE
*
Output Output enable signal for the DRAM interface
space or clock enable signal for the
synchronous DRAM interface space.
Wait WAIT Input Wait request signal when accessing external
space.
Bus request BREQ Input Request signal for release of bus to external
bus master.
Bus request acknowledge BACK Output Acknowledge signal indicating that bus has
been released to external bus master.
Bus request output BREQO Output External bus request signal used when internal
bus master accesses external address space
when external bus is released.
Data transfer acknowledge
1 (DMAC)
DACK1 Output Data transfer acknowledge signal for single
address transfer by DMAC channel 1.
Data transfer acknowledge
0 (DMAC)
DACK0 Output Data transfer acknowledge signal for single
address transfer by DMAC channel 0.
Data transfer acknowledge
3 (EXDMAC)
EDACK3 Output Data transfer acknowledge signal for single
address transfer by EXDMAC channel 3.
Data transfer acknowledge
2 (EXDMAC)
EDACK2 Output Data transfer acknowledge signal for single
address transfer by EXDMAC channel 2.