Datasheet

Section 6 Bus Controller (BSC)
Rev. 3.00 Mar 17, 2006 page 126 of 926
REJ09B0283-0300
6.3.1 Bus Width Control Register (ABWCR)
ABWCR designates each area in the external address space as either 8-bit access space or 16-bit
access space.
Bit Bit Name Initial Value
*
R/W Description
7
6
5
4
3
2
1
0
ABW7
ABW6
ABW5
ABW4
ABW3
ABW2
ABW1
ABW0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
1/0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Area 7 to 0 Bus Width Control
These bits select whether the corresponding
area is to be designated as 8-bit access space
or 16-bit access space.
0: Area n is designated as 16-bit access space
1: Area n is designated as 8-bit access space
(n = 7 to 0)
Note: * In modes 2, 4, and 6, ABWCR is initialized to 1. In modes 1, 5, and 7, ABWCR is
initialized to 0.
6.3.2 Access State Control Register (ASTCR)
ASTCR designates each area in the external address space as either 2-state access space or 3-state
access space.
Bit Bit Name Initial Value R/W Description
7
6
5
4
3
2
1
0
AST7
AST6
AST5
AST4
AST3
AST2
AST1
AST0
1
1
1
1
1
1
1
1
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Area 7 to 0 Access State Control
These bits select whether the corresponding
area is to be designated as 2-state access
space or 3-state access space. Wait state
insertion is enabled or disabled at the same
time.
0: Area n is designated as 2-state access space
Wait state insertion in area n access is
disabled
1: Area n is designated as 3-state access space
Wait state insertion in area n access is
enabled
(n = 7 to 0)