Datasheet

Section 6 Bus Controller (BSC)
Rev. 3.00 Mar 17, 2006 page 195 of 926
REJ09B0283-0300
DRAM space write
T
rc3
T
rp1
T
rp2
T
p
T
r
Software
standby
T
c1
T
c2
Note: n = 2 to 5
φ
RASn (CSn)
UCAS, LCAS
OE (RD)
WR (HWR)
Data bus
Address bus
Figure 6.40 Example of Timing when Precharge Time after Self-Refreshing Is Extended
by 2 States
Refreshing and All-Module-Clocks-Stopped Mode: In this LSI, if the ACSE bit is set to 1 in
MSTPCRH, and then a SLEEP instruction is executed with the setting for all peripheral module
clocks to be stopped (MSTPCR = H'FFFF) or for operation of the 8-bit timer module alone
(MSTPCR = H'FFFE), and a transition is made to the sleep state, the all-module-clocks-stopped
mode is entered, in which the bus controller and I/O port clocks are also stopped. As the bus
controller clock is also stopped in this mode, CBR refreshing is not executed. If DRAM is
connected externally and DRAM data is to be retained in sleep mode, the ACSE bit must be
cleared to 0 in MSTPCRH.
6.6.13 DMAC and EXDMAC Single Address Transfer Mode and DRAM Interface
When burst mode is selected on the DRAM interface, the DACK and EDACK output timing can
be selected with the DDS and EDDS bits in DRAMCR. When DRAM space is accessed in DMAC