Datasheet

Section 6 Bus Controller (BSC)

Rev. 3.00 Mar 17, 2006 page 200 of 926

REJ09B0283-0300

6.7.3 Data Bus

If the ABW2 bit in ABWCR corresponding to an area designated as continuous synchronous

DRAM space is set to 1, area 2 to 5 are designated as 8-bit continuous synchronous DRAM space;

if the bit is cleared to 0, the areas are designated as 16-bit continuous synchronous DRAM space.

In 16-bit continuous synchronous DRAM space, ×16-bit configuration synchronous DRAM can be

connected directly.

In 8-bit continuous synchronous DRAM space the upper half of the data bus, D15 to D8, is

enabled, while in 16-bit continuous synchronous DRAM space both the upper and lower halves of

the data bus, D15 to D0, are enabled.

Access sizes and data alignment are the same as for the basic bus interface: see section 6.5.1, Data

Size and Data Alignment.

6.7.4 Pins Used for Synchronous DRAM Interface

Table 6.9 shows pins used for the synchronous DRAM interface and their functions. To enable the

synchronous DRAM interface, fix the DCTL pin to 1. Do not vary the DCTL pin during operation.

Since the CS2 to CS4 pins are in the input state after a reset, set DDR to 1 when RAS, CAS, and

WE signals are output. For details, see section 10, I/O Ports. Set the OEE bit of the DRAMCR