Datasheet

Section 7 DMA Controller (DMAC)
Rev. 3.00 Mar 17, 2006 page 273 of 926
REJ09B0283-0300
Bit Bit Name Initial Value R/W Description
13 SAE1 0 R/W Single Address Enable 1
Specifies whether channel 1B is to be used for
transfer in dual address mode or single address
mode. This bit is invalid in full address mode.
0: Dual address mode
1: Single address mode
12 SAE0 0 R/W Single Address Enable 0
Specifies whether channel 0B is to be used for
transfer in dual address mode or single address
mode. This bit is invalid in full address mode.
0: Dual address mode
1: Single address mode
11
10
9
8
DTA1B
DTA1A
DTA0B
DTA0A
0
0
0
0
R/W
R/W
R/W
R/W
Data Transfer Acknowledge 1B
Data Transfer Acknowledge 1A
Data Transfer Acknowledge 0B
Data Transfer Acknowledge 0A
These bits enable or disable clearing when
DMA transfer is performed for the internal
interrupt source selected by the DTF3 to DTF0
bits in DMACR.
It the DTA bit is set to 1 when DTE = 1, the
internal interrupt source is cleared automatically
by DMA transfer. When DTE = 1 and DTA = 1,
the internal interrupt source does not issue an
interrupt request to the CPU or DTC.
If the DTA bit is cleared to 0 when DTE = 1, the
internal interrupt source is not cleared when a
transfer is performed, and can issue an
interrupt request to the CPU or DTC in parallel.
In this case, the interrupt source should be
cleared by the CPU or DTC transfer.
When DTE = 0, the internal interrupt source
issues an interrupt request to the CPU or DTC
regardless of the DTA bit setting.