Datasheet

Section 9 Data Transfer Controller (DTC)
Rev. 3.00 Mar 17, 2006 page 406 of 926
REJ09B0283-0300
Bit Bit Name Initial Value R/W Description
7
6
5
4
3
2
1
0
DTCE7
DTCE6
DTCE5
DTCE4
DTCE3
DTCE2
DTCE1
DTCE0
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DTC Activation Enable
Setting this bit to 1 specifies a relevant interrupt
source to a DTC activation source.
[Clearing conditions]
• When the DISEL bit is 1 and the data transfer has
ended
• When the specified number of transfers have
ended
These bits are not cleared when the DISEL bit is 0
and the specified number of transfers have not
ended
9.2.8 DTC Vector Register (DTVECR)
DTVECR enables or disables DTC activation by software, and sets a vector number for the
software activation interrupt.
Bit Bit Name Initial Value R/W Description
7 SWDTE 0 R/W DTC Software Activation Enable
Setting this bit to 1 activates DTC. Only 1 can be
written to this bit.
[Clearing conditions]
• When the DISEL bit is 0 and the specified
number of transfers have not ended
• When 0 is written to the DISEL bit after a
software-activated data transfer end interrupt
(SWDTEND) request has been sent to the CPU.
When the DISEL bit is 1 and data transfer has ended
or when the specified number of transfers have
ended, this bit will not be cleared.
6
5
4
3
2
1
0
DTVEC6
DTVEC5
DTVEC4
DTVEC3
DTVEC2
DTVEC1
DTVEC0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
DTC Software Activation Vectors 6 to 0
These bits specify a vector number for DTC software
activation.
The vector address is expressed as H'0400 + (vector
number × 2). For example, when DTVEC6 to
DTVEC0 = H'10, the vector address is H'0420. When
the bit SWDTE is 0, these bits can be written.