Datasheet

Section 11 16-Bit Timer Pulse Unit (TPU)
Rev. 3.00 Mar 17, 2006 page 596 of 926
REJ09B0283-0300
11.10.5 Contention between TCNT Write and Increment Operations
If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence
and TCNT is not incremented. Figure 11.46 shows the timing in this case.
TCNT input
clock
Write signal
Address
φ
TCNT address
TCNT
TCNT write cycle
T1 T2
N M
TCNT write data
Figure 11.46 Contention between TCNT Write and Increment Operations