Datasheet

Section 13 8-Bit Timers (TMR)
Rev. 3.00 Mar 17, 2006 page 633 of 926
REJ09B0283-0300
13.3.5 Timer Control/Status Register (TCSR)
TCSR displays status flags, and controls compare match output.
TCSR_0
Bit Bit Name Initial Value R/W Description
7CMFB 0 R/(W)
*
Compare Match Flag B
[Setting condition]
Set when TCNT matches TCORB
[Clearing conditions]
• Cleared by reading CMFB when CMFB = 1,
then writing 0 to CMFB
• When DTC is activated by CMIB interrupt
while DISEL bit of MRB in DTC is 0
6CMFA 0 R/(W)
*
Compare Match Flag A
[Setting condition]
Set when TCNT matches TCORA
[Clearing conditions]
• Cleared by reading CMFA when CMFA = 1,
then writing 0 to CMFA
• When DTC is activated by CMIA interrupt
while DISEL bit of MRB in DTC is 0
5OVF 0 R/(W)
*
Timer Overflow Flag
[Setting condition]
Set when TCNT overflows from H'FF to H'00
[Clearing condition]
Cleared by reading OVF when OVF = 1, then
writing 0 to OVF
4 ADTE 0 R/W A/D Trigger Enable
Selects enabling or disabling of A/D converter
start requests by compare match A.
0: A/D converter start requests by compare
match A are disabled
1: A/D converter start requests by compare
match A are enabled