Datasheet

Section 13 8-Bit Timers (TMR)
Rev. 3.00 Mar 17, 2006 page 643 of 926
REJ09B0283-0300
13.8 Usage Notes
13.8.1 Contention between TCNT Write and Clear
If a timer counter clock pulse is generated during the T
2
state of a TCNT write cycle, the clear
takes priority, so that the counter is cleared and the write is not performed.
Figure 13.10 shows this operation.
φ
Address
TCNT address
Internal write signal
Counter clear signal
TCNT
N H'00
T
1
T
2
TCNT write cycle by CPU
Figure 13.10 Contention between TCNT Write and Clear