Datasheet

Section 19 Flash Memory (F-ZTAT Version)
Rev. 3.00 Mar 17, 2006 page 781 of 926
REJ09B0283-0300
19.4 Input/Output Pins
Table 19.2 shows the pin configuration of the flash memory.
Table 19.2 Pin Configuration
Pin Name I/O Function
RES Input Reset
FWE
*
Input Flash program/erase protection by hardware
MD2 Input Sets this LSI’s operating mode
MD1 Input Sets this LSI’s operating mode
MD0 Input Sets this LSI’s operating mode
P52 Input Sets operating mode in programmer mode
P51 Input Sets operating mode in programmer mode
P50 Input Sets operating mode in programmer mode
TxD1 Output Serial transmit data output
RxD1 Input Serial receive data input
Note: * Only in H8S/2678 Group.
19.5 Register Descriptions
The flash memory has the following registers. For details on the system control register, refer to
section 3.2.2, System Control Register (SYSCR).
• Flash memory control register 1 (FLMCR1)
• Flash memory control register 2 (FLMCR2)
• Erase block register 1 (EBR1)
• Erase block register 2 (EBR2)
• RAM emulation register (RAMER)
19.5.1 Flash Memory Control Register 1 (FLMCR1)
FLMCR1 is a register that makes the flash memory transit to program mode, program-verify
mode, erase mode, or erase-verify mode. For details on register setting, refer to section 19.8, Flash
Memory Programming/Erasing.