Datasheet

ManualsBrandsRENESAS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 144 (20x20) 16-Bit 33 MHz I/O number 103

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Section 20 Masked ROM

Rev. 3.00 Mar 17, 2006 page 809 of 926

REJ09B0283-0300

Section 20 Masked ROM

This Group microcomputer has 64, 128, or 256 kbytes of on-chip masked ROM. The on-chip

ROM is connected to the CPU, data transfer controller (DTC), and DMA controller (DMAC) with

a 16-bit data bus. The on-chip ROM can be accessed by the CPU, DTC, and DMAC in 8 or 16-bit

units. The data in the on-chip ROM can always be accessed in one state.

H'000000

H'000002

H'03FFFE

H'000001

H'000003

H'03FFFF

Internal data bus (upper 8 bits)

Modes 4 and 7 Modes 5 and 6

Internal data bus (lower 8 bits)

H'100000

H'100002

H'13FFFE

H'100001

H'100003

H'13FFFF

Internal data bus (upper 8 bits)

Internal data bus (lower 8 bits)

Figure 20.1 Block Diagram of 256-kbyte Masked ROM (HD6432676)

H'000000

H'000002

H'01FFFE

H'000001

H'000003

H'01FFFF

Internal data bus (upper 8 bits)

Modes 4 and 7 Modes 5 and 6

Internal data bus (lower 8 bits)

H'100000

H'100002

H'11FFFE

H'100001

H'100003

H'11FFFF

Internal data bus (upper 8 bits)

Internal data bus (lower 8 bits)

Figure 20.2 Block Diagram of 128-kbyte Masked ROM (HD6432675)