Datasheet

Section 22 Power-Down Modes
Rev. 3.00 Mar 17, 2006 page 819 of 926
REJ09B0283-0300
Section 22 Power-Down Modes
In addition to the normal program execution state, this LSI has power-down modes in which
operation of the CPU and oscillator is halted and power dissipation is reduced. Low-power
operation can be achieved by individually controlling the CPU, on-chip peripheral modules, and
so on.
This LSI’s operating modes are high-speed mode and six power down modes:
• Clock division mode
• Sleep mode
• Module stop mode
• All module clock stop mode
• Software standby mode
• Hardware standby mode
Sleep mode is a CPU state, clock division mode is a CPU and bus master state, and module stop
mode is an on-chip peripheral function (including bus masters other than the CPU) state. A
combination of these modes can be set.
After a reset, this LSI is in high-speed mode.
Table 22.1 shows the internal states of this LSI in each mode. Figure 21.1 shows the mode
transition diagram.
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