Datasheet

Section 28 Electrical Characteristics
Rev. 2.00 Sep. 28, 2009 Page 969 of 994
REJ09B0452-0200
Item Symbol Min. Max. Unit
Test
Conditions
Input clock rise time t
SCKr
⎯ 1.5
Input clock fall time t
SCKf
⎯ 1.5
t
cyc
Figure 28.20
Transmit data delay time (synchronous) t
TXD
⎯ 50
Receive data setup time (synchronous) t
RXS
50 ⎯
SCI
Receive data hold time (synchronous) t
RXH
50 ⎯
ns Figure 28.21
FSI Clock cycle t
CYC
30 ⎯ ns Figure 28.22
Clock pulse width (high) t
CKH
13 ⎯
Clock pulse width (low) t
CKL
13 ⎯
SS signal rise delay time t
SSH
12 ⎯
SS signal fall delay time t
SSL
12 ⎯
Transmit signal delay time t
TXD
⎯ 12
Receive signal setup time t
RXS
5 ⎯
Receive signal hold time t
RXH
5 ⎯
Notes: 1. Applied only for the peripheral modules that are available during subclock operation.
2. Other than P52, P97, P86, P42, port A, port G, and port I.
φ
Ports 1 to 9
and A to J (read)
t
PRS
T
1
T
2
t
PWD
t
PRH
Ports 1 to 6, 8, 9,
A to D and F to J
(write)
Figure 28.9 I/O Port Input/Output Timing