Datasheet

Rev. 2.00 Sep. 28, 2009 Page x of xl
REJ09B0452-0200
Item Page Revision (See Manual for Details)
8.4.2 Pulse Division
Mode
Figure 8.8 Example of
Additional Pulse Timing
(Upper 4 Bits in
PWMREG = B'1000)
215 Figure amended
No pulse added
Pulse added
Resolution width
Additional pulse
Figure 8.9 Example of
WMU Setting
216 Figure amended
: Position of additional pulse
1 conversion period
Duty cycle
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
127/256
128/256
129/256
130/256
PWMREG
setting
example
H'7F
H'80
H'81
H'82
10.3.3 Timer I/O
Control Register (TIOR)
Table 10.13 TIORL_0
(channel 0)
253 Table amended
Bit 3
IOC3
Bit 2
IOC2
Bit 1
IOC1
Bit 0
IOC0
11.3.6 TCM Status
Register (TCMCSR)
312 Table amended
Bit Bit Name
Initial
Value
R/W Description
0 0 R/W Reserved
The initial value should not be changed.
14.3.2 Timer
Control/Status Register
(TCSR)
394 Table amended
Bit Bit Name
Initial
Value
R/W Description
4 0
R/W Reserved
The initial value should not be changed.