Datasheet

Rev. 2.00 Sep. 28, 2009 Page xv of xl
REJ09B0452-0200
Item Page Revision (See Manual for Details)
20.1 Features
Figure 20.1 Block
Diagram of LPC
616 Figure amended
IDR4
IDR3
IDR2
IDR1
TWR0MW
TWR1 to
TWR15
20.3 Register
Descriptions
Table 20.2 Register
Configuration
619 Table amended
R/W
Register Name Abbreviation Slave Host
Initial
Value Address
Data Bus
Width
Bidirectional data register 0MW TWR0MW R W H'00 H'FE20 8
Bidirectional data register 0SW TWR0SW W R H'00 H'FE20 8
20.3.1 Host Interface
Control Registers 0 and
1 (HICR0 and HICR1)
• HICR1
625 Table amended
R/W
Bit Bit Name
Initial
Value Slave Host Description
0 LSCIB 0 R/W
—
LSCI output Bit
Controls LSCI output in combination with the LSCIE
bit . For details, refer to description on the LSCIE
bit in HICR0.
20.3.2 Host Interface
Control Registers 2 and
3 (HICR2 and HICR3)
• HICR2
627 Table amended
R/W
Bit Bit Name
Initial
Value Slave Host Description
3 IBFIE3 0 R/W
—
IDR3 and TWR Receive Complete interrupt Enable
Enables or disables IBFI3 interrupt to the slave (this
LSI).
0: Input data register IDR3 and TWR receive
complete interrupt requests disabled
1: [When TWRE = 0 in LADR3]
Input data register (IDR3) receive complete
interrupt requests enabled
[When TWRE = 1 in LADR3]
Input data register (IDR3) and TWR receive
complete interrupt requests enabled