Datasheet

Rev. 2.00 Sep. 28, 2009 Page xvi of xl
REJ09B0452-0200
Item Page Revision (See Manual for Details)
20.3.11 Bidirectional
Data Registers 0 to 15
(TWR0 to TWR15)
638 Description amended
When the host and slave begin a write, after the respective
registers of TWR0 have been written to, arbitration for
simultaneous access is performed by checking the status flags
whether or not those writes were valid.
When the host has access rights, TWR0MW is selected in
TWR0 and the state of TWR0MW is returned when the host
reads TWR0SW. Attempts by the slave to write to TWR0SW
are invalid.
When the slave has access rights, TWR0SW is selected in
TWR0 and the state of TWR0SW is returned when the slave
reads TWR0MW. Attempts by the host to write to TWR0MW
are invalid.
For the registers selected from the host according to the I/O
address, see section 20.3.7, LPC Channel 3 Address Registers
H and L (LADR3H and LADR3L).
20.3.12 Status
Registers 1 to 4 (STR1
to STR4)
• STR4
644 Table amended
R/W
Bit Bit Name Initial Value Slave Host Description
0 OBF4 0 R/(W)
*
R Output Buffer Full
0: [Clearing conditions]
When the host reads ODR4 in I/O read cycle
When the slave writes 0 to the OBF4 bit
1: [Setting condition]
When the slave writes to ODR4
21.4.5 FSI Memory
Cycle (LPC-SPI
Command Transfer)
Figure 21.13 FSI
Command Read
(Example)
716 Figure amended
FSILSTR1
FSIGPR1
FSIGPRE
FSIGPRF
FSIGPR2 to D
LPC internal flags
EC CPU write
21.5 Reset Conditions
Table 21.8 Range of
Initialization of FSI in
Each Mode
723, 724 Table amended
Register Name
System
Reset
LPC Reset
LPC
Shutdown
LPC Abort FSI Reset
FSILSTR1 Bits 7, 6, 4,
and 3
Initialized Initialized Retained Retained
Retained
Bit 2 Initialized Initialized Retained Retained Initialized
Bits 5, 1, and
0
Initialized Retained Retained Retained Retained
FSISTR Bits 6 and 5 Initialized Retained Retained Retained Initialized