Datasheet

Section 7 I/O Ports
Rev. 2.00 Sep. 28, 2009 Page 164 of 994
REJ09B0452-0200
(3) P84/IRQ3/TxD1
The pin function is switched as shown below according to the combination of the register setting
of the SCI and the P84DDR bit.
Setting
SCI I/O Port
Module
Name
Pin Function
TxD1_OE P84DDR
SCI TxD1 output 1 ⎯
I/O port P84 output 0 1
P84 input
(initial setting)
0 0
(4) P83/LPCPD
The pin function is switched as shown below according to the combination of the FSILIE bit in
SLCR of FSI, the SCIFE bit in HICR5 and the LPC4E bit in HICR4 of the LPC, LPC3E to LPC1E
bits in HICR0, and the P83DDR bit. LPCENABLE in the following table is expressed by the
following logical expression.
LPCENABLE = 1 : FSILIE + SCIFE + LPC4E + LPC3E + LPC2E + LPC1E
Setting
Logical Expression I/O Port
Module
Name
Pin Function
LPCENABLE P83DDR
LPC LPCPD input 1 ⎯
I/O port P83 output 0 1
P83 input
(initial setting)
0 0