Datasheet

Section 7 I/O Ports
Rev. 2.00 Sep. 28, 2009 Page 165 of 994
REJ09B0452-0200
(5) P82/CLKRUN
The pin function is switched as shown below according to the combination of the FSILIE bit in
SLCR of FSI, the SCIFE bit in HICR5 and the LPC4E bit in HICR4 of the LPC, LPC3E to LPC1E
bits in HICR0, and the P82DDR bit. LPCENABLE in the following table is expressed by the
following logical expression.
LPCENABLE = 1 : FSILIE + SCIFE + LPC4E + LPC3E + LPC2E + LPC1E
Setting
Logical Expression I/O Port
Module
Name
Pin Function
LPCENABLE P82DDR
LPC CLKRUN output 1 ⎯
I/O port P82 output 0 1
P82 input
(initial setting)
0 0
(6) P81/GA20
The pin function is switched as shown below according to the combination of the register setting
of the LPC and the P81DDR bit.
Setting
LPC I/O Port
Module
Name
Pin Function
GA20_OE P81DDR
LPC GA20 output 1 ⎯
I/O port P81 output 0 1
P81 input
(initial setting)
0 0