Datasheet

Section 10 16-Bit Timer Pulse Unit (TPU)
Rev. 2.00 Sep. 28, 2009 Page 302 of 994
REJ09B0452-0200
10.8.9 Conflict between Buffer Register Write and Input Capture
If the input capture signal is generated in the T
2
state of a buffer register write cycle, the buffer
operation takes precedence and the write to the buffer register is not performed. Figure 10.50
shows the timing in this case.
Input capture
signal
Write signal
Address
φ
TCNT
Buffer register write cycle
T1
T2
N
TGR
N
M
M
Buffer
register
Buffer register
address
Figure 10.50 Conflict between Buffer Register Write and Input Capture