Datasheet

Rev. 2.00 Sep. 28, 2009 Page xxxiii of xl
REJ09B0452-0200
15.9.8 Note on Writing to Registers in Transmission, Reception, and
Simultaneous Transmission and Reception .......................................................... 467
Section 16 CIR Interface......................................................................................469
16.1 Features .............................................................................................................................. 469
16.2 Input Pins ........................................................................................................................... 471
16.3 Register Description........................................................................................................... 471
16.3.1 Receive Control Register 1 (CCR1)...................................................................... 472
16.3.2 Receive Control Register 2 (CCR2)...................................................................... 473
16.3.3 Receive Status Register (CSTR) ........................................................................... 474
16.3.4 Interrupt Enable Register (CEIR) ......................................................................... 476
16.3.5 Bit Rate Register (BRR) ....................................................................................... 477
16.3.6 Receive Data Register 0 to 17 (CIRRDR0 to CIRRDR17)................................... 478
16.3.7 Header Minimum/Maximum High-Level Period Register
(HHMIN and HHMAX) ....................................................................................... 478
16.3.8 Header Minimum/Maximum Low-Level Period Register (HLMIN/HLMAX).... 480
16.3.9 Data Level 1 Minimum/Maximum Period Register (DT1MIN/DT1MAX) ......... 480
16.3.10 Data Level 0 Minimum/Maximum Period Register (DT0MIN/DT0MAX) ......... 481
16.3.11 Repeat Header Minimum/Maximum Low-Level Period Register
(RMIN/RMAX) .................................................................................................... 481
16.4 Operation ........................................................................................................................... 482
16.4.1 Determination of Signal Type by Low/High-Level Period................................... 484
16.4.2 Operation of FIFO Register .................................................................................. 486
16.4.3 Operation in Watch Mode..................................................................................... 487
16.4.4 Switching between System Clock and Sub Clock ................................................ 487
16.5 Noise Canceler Circuit ....................................................................................................... 488
16.6 Reset Conditions ................................................................................................................ 490
16.7 Interrupt Sources................................................................................................................ 490
16.8 Usage Note......................................................................................................................... 491
Section 17 Serial Communication Interface with FIFO (SCIF) ..........................493
17.1 Features .............................................................................................................................. 493
17.2 Input/Output Pins ............................................................................................................... 495
17.3 Register Descriptions ......................................................................................................... 496
17.3.1 Receive Shift Register (FRSR) ............................................................................. 497
17.3.2 Receive Buffer Register (FRBR) .......................................................................... 497
17.3.3 Transmitter Shift Register (FTSR)........................................................................ 498
17.3.4 Transmitter Holding Register (FTHR).................................................................. 498
17.3.5 Divisor Latch H, L (FDLH, FDLL) ...................................................................... 498
17.3.6 Interrupt Enable Register (FIER).......................................................................... 499