Datasheet

Section 12 16-Bit Duty Period Measurement Timer (TDP)
Rev. 2.00 Sep. 28, 2009 Page 338 of 994
REJ09B0452-0200
12.3.9 TDP Control Register 1 (TDPCR1)
TDPCR1 selects the input capture input edge, starts the TDPCNT counter, selects the counter
clock, and controls the operating mode.
Bit Bit Name
Initial
Value
R/W Description
7 CST 0 R/W Counter Start
In timer mode, setting this bit to 1 starts counting by
TDPCNT, and clearing it stops counting. After the bit is
cleared, the counter is initialized to H'0000, and the input-
capture operation stops.
Clear this bit to initialize TDPCNT to H'0000 before setting
to cycle measurement mode.
6 POCTL 0 R/W TDPCYI Input Polarity Inversion
0: TDPCYI input is used directly
1: TDPCYI input is inverted for use
Note: Change this bit when CST = 0 and TDPMDS = 0.
5 CPSPE 0 R/W Input Capture Stop Enable
Controls whether counting up by TDPCNT and input-
capture operation stop or continue when any of the
TPDMXOVF, TPDMNUDF, TWDMXOVF, and TWDMNUDF
flags is set to 1 in cycle measurement mode. This bit does
not affect operation in timer mode.
0: Counting up and input-capture operation continue when
any of the flags is set to 1.
1: Counting up and input-capture operation stop when any
of the flags is set to 1.