Datasheet

Section 13 8-Bit Timer (TMR)
Rev. 2.00 Sep. 28, 2009 Page 364 of 994
REJ09B0452-0200
TCR STCR
Channel CKS2 CKS1 CKS0 ICKS1 ICKS0 Description
1 0 1 — — Increments at rising edge of external
clock
Common
1 1 0 — — Increments at falling edge of external
clock
1 1 1 — — Increments at both rising and falling
edges of external clock
Note: * If the TMR_0 clock input is set as the TCNT_1 overflow signal and the TMR_1 clock
input is set as the TCNT_0 compare-match signal simultaneously, a count-up clock
cannot be generated. These settings should not be made.