Datasheet

Section 1 Overview
Rev. 2.00 Sep. 28, 2009 Page 8 of 994
REJ09B0452-0200
1.3 Block Diagram
PA
0
/K
IN8
/PS2
D
C
P
A1
/KIN9
/P
S
2
DD
PA
2
/K
IN1
0
/P
S
2
AC
P
A3
/
KIN1
1
/PS2
A
D
PA4
/KIN1
2
/PS2
BC
PA
5
/K
IN1
3
/P
S
2
B
D
P
A6
/KIN1
4
/PS2
C
C
PA
7
/K
IN1
5
/P
S
2
CD
P20
P21
P22
P23
P24
P25
P
2
6
P
2
7
P10
P11
P1
2
P13
P14
P15
P16
P17
P
3
0
/L
AD
0
P3
1
/LAD1
P3
2
/LAD2
P3
3
/LAD3
P3
4
/L
FR
A
M
E
P
3
5
/L
RE
SET
P3
6
/LCLK
P3
7
/SERIRQ
PB
0
/L
SMI
P
B1
/L
S
CI
PB
2
/RI/PW
MU0
B
P
B3
/
D
CD/PW
MU
1
B
PB4
/DSR/FSI
D
O
PB
5
/DTR/FSIDI
P
B6
/CT
S
/FSICK
PB7/RTS/FS
IS
S
PC0
/TIOCA0
/W
U
E
8
P
C
1
/TIOCB
0
/W
UE9
PC
2
/TIOCC0
/TCLKA/W
UE
1
0
PC3
/TIOC
D0/TCLK
B/
W
UE1
1
PC4
/TIO
CA1
/W
UE1
2
PC5
/TIOCB1/TCLK
C
/
W
UE1
3
PC6/TI
OCA2
/W
UE1
4
P
C7
/TIOCB
2
/TCLK
D
/
W
UE1
5
P50
/
F
TxD
P
5
1
/FR
xD
P52
/SCL
0
RAM
In
terrup
t con
troller
8
-bit t
imer
(
4
ch
a
n
n
e
ls)
ROM
(flasf memory)
Clock pu
lse
gen
e
rator
H8S/2600
CPU
W
DT
(2 ch
a
n
n
e
ls)
PS
2
(4 cha
n
n
e
ls)
S
CIF
(1
ch
a
n
n
e
l)
1
6
-bit TDP
(3 ch
a
n
n
e
l
s)
1
6
-bit
TCM
(4
ch
a
n
n
e
ls)
SCI (2
cha
n
n
e
ls)
Sma
rt Ca
rd I/F
(2 ch
a
n
n
e
l
s)
8
-bit
P
W
M
(
1
2
cha
n
n
e
ls)
IIC
(
3
ch
a
n
n
e
ls)
1
4
-bit PW
M
(2 ch
a
n
n
e
ls)
1
6
-bit TP
U
(3 cha
n
n
e
ls)
1
0
-bit
A
/D co
n
ve
rte
r
(16
ch
a
n
n
e
ls)
RES
XTAL
EXTAL
MD2
MD
1
NMI
ETRST
VCC
VCC
VCC
VCL
VSS
VSS
VS
S
VSS
VSS
AVref AVCC AVSS
L
P
C
(4
ch
a
n
n
e
ls)
H-UDI
P8
0
/
PME
P
8
1
/GA
2
0
P8
2
/CL
KRUN
P
8
3
/L
P
C
P
D
P8
4
/TxD1
/
IRQ3
P8
5
/RxD1
/IRQ4
P
8
6
/SCK1
/SCL1
/I
R
Q5
P4
0
/
T
MI0
/TxD2
/TCMCYI0
P
4
1
/TMO0
/RxD2
/TCMCKI0/TC
MMCI0
P
4
2
/SDA1
/TCMCYI1
P4
3
/TMI1
/SCK2/TCMCKI1
/TCMMCI1
P4
4
/TMO1
/P
W
M
U2
B/T
CMCYI2
P45
/PW
MU
3
B/T
CMCKI
2
/TCM
MCI2
P
4
6
/PWX0
/PW
M
U
4
B/TCMCY
I3
P4
7
/P
WX1
/P
W
MU
5
B/TCMCKI3/TC
MMC
I
3
P6
0
/K
IN0
P61
/
KIN1
P
6
2
/KIN2
P
6
3
/KIN3
P6
4
/K
IN4
P6
5
/K
IN5
P6
6
/
IRQ6
/
KIN6
P67
/IRQ7/KIN7
P9
0
/
IRQ2
P
9
1
/IRQ1
P92
/IRQ
0
P
9
3
/IRQ1
2
P9
4
/IRQ1
3
P9
5
/
IRQ1
4
P9
6
/
φ
/EXCL
P
9
7
/IRQ1
5
/SD
A
0
PE0
/E
xEX
CL
PE1*
1
/ET
CK
P
E2
*
1
/ET
DI
P
E3
*
1
/ET
DO
P
E4
*
1
/ET
MS
Port 8
PG
0
/ExIRQ8
/T
M
IX
/TDPCYI1
PG1/E
xIRQ9
/TMIY
/TDPCKI1
/TDPMCI1
P
G2
/E
xIRQ1
0
/S
DA2
P
G3
/
ExIRQ11
/SCL2
P
G4
/
ExIRQ12
/ExSDAA
P
G5
/
ExIRQ13
/ExSCLA
PG6/ExI
R
Q14
/ExSDAB
PG
7
/ExIRQ
1
5
/E
xSCLB
PI
0
*
2
PI1*
2
PI2*
2
PI3*
2
PI4*
2
PI
5
*
2
PI6*
2
PI7*
2
PJ0*
2
PJ1*
2
PJ2
*
2
PJ3
*
2
PJ4
*
2
PJ5*
2
PJ6
*
2
PJ7
*
2
PF0
/PWM
U0
A/IRQ8
P
F
1
/PWMU
1
A/
IRQ9
PF2
/TM
OY/IRQ1
0
/TDP
CYI0
PF3
/
TMO
X
/IRQ11
/TDPCK
I0
/
T
DP
MCI0
PF4
/PW
M
U2
A
PF5
/P
W
M
U3
A
PF6
/P
W
MU
4
A
PF7
/PWMU5
A
Port B
Port A
Port 9
PH0
/ExIRQ6/TDPCYI2
PH1
/
ExIRQ7/TDPCKI2/TDPMC
I2
PH2/CIRI
PH3
P
H4
P
H5
Notes: 1. Not supported by the system development tool (emulator)
2. Not supported by TFP-144 V and TLP-145 V
PD0/AN8
PD1/AN9
PD2AN10
PD3/AN11
PD4/AN12
PD5/AN13
PD6/AN14
PD7/AN15
P70/AN0
P71/AN1
P72/AN2
P73/AN3
P74/AN4
P75/AN5
P76/AN6
P77/AN7
Port J
Address bus
Data bus
Bus controller
Internal address bus
Internal Data bus
Port IPort HPort GPort FPort EPort C
Port 2 Port 1Port 3Port 4Port 5Port 6Port 7
Port D
FSI
(1 channel)
CIR
(1 channel)
Figure 1.2 Internal Block Diagram