Datasheet

Section 16 CIR Interface
Rev. 2.00 Sep. 28, 2009 Page 470 of 994
REJ09B0452-0200
Module data bus
4-stage filter
Reception control
Baud rate generator
Sampling clock
[Legend]
SFR: Receive shift register
CCR1: Receive control register 1
CCR2: Receive control register 2
CSTR: Receive status register
CEIR: Interrupt enable register
BRR: Bit rate register
CIRRDR0 to 17: Receive data register 0 to 17
HHMIN: Header minimum high-level period register
HHMAX: Header maximum high-level period register
HLMIN: Header minimum low-level period register
HLMAX: Header maximum low-level period register
DT1MIN: Data level 1 minimum period register
DT1MAX: Data level 1 maximum period register
DT0MIN: Data level 0 minimum period register
DT0MAX: Data level 0 maximum period register
RMIN: Repeat header minimum low-level period register
RMAX: Repeat header maximum low-level period register
CIRRDR
0 to 17
(18-byte
FIFO)
SFR
HHMAX
HLMAX
DT0MAX
DT1MAX
RMAX
HHMIN
HLMIN
DT0MIN
DT1MIN
RMIN
CCR1
CCR2
CSTR
CEIR
BRR
φ
φ/2
φ/4
φ
SUB
CIRI
RENDI
OVEI
REPI
FREI
ABI
HEADFI
Figure 16.1 CIR Block Diagram