Datasheet

Section 16 CIR Interface
Rev. 2.00 Sep. 28, 2009 Page 472 of 994
REJ09B0452-0200
Register Name Abbreviation R/W Initial Value Address
Repeat header minimum low-level period
register
RMIN R/W H'00 H'FA50
Repeat header maximum low-level period
register
RMAX R/W H'00 H'FA51
Notes: 1. Before accessing these registers, clear the MSTPA3 bit (bit 3) in MSTPCRA to 0.
2. See the description of each register for details on R/W.
16.3.1 Receive Control Register 1 (CCR1)
CCR1 enable/disable the CIR reception, controls a software reset of the CIR, select the polarity of
the CIR input signals, and select the reference clock for CIR reception.
Bit Bit Name
Initial
Value
R/W Description
7 CIRE 0 R/W CIR Receive Enable
0: The CIR reception is disabled.
1: The CIR reception is enabled (Port is CIRI input
pin).
6 SRES 0 R/W CIR Software Reset
Controls initialization of the internal sequencer of the
CIR.
0: Normal operation
1: The internal sequencer is cleared.
Writing 1 to this bit generates a clear signal for the
internal sequencer in the corresponding module,
resulting in the initialization of the CIR's internal state.
5 CPHS 0 R/W Input Signal Polarity Select
0: CIR input signal is used as is.
1: CIR input signal is inverted before use.
4 MLS 0 R/W Receive Data Format Select
0: LSB-first data is received.
1: MSB-first data is received.