Datasheet

Section 16 CIR Interface
Rev. 2.00 Sep. 28, 2009 Page 479 of 994
REJ09B0452-0200
• HHMAX
Bit Bit Name
Initial
Value
R/W Description
15
14
FLT1
FLT0
0
0
R/W
R/W
Number of Stages of Noise Canceler Circuit Select
00: The noise canceler circuit consists of one stage
01: The noise canceler circuit consists of two stages
10: The noise canceler circuit consists of three
stages
11: The noise canceler circuit consists of four stages
13 FLTE 0 R/W Noise Canceler Circuit Enable
0: Disables the noise canceler circuit
1: Enables the noise canceler circuit
12
11
FLTCK1
FLTCK0
0
0
R/W
R/W
Division Ratio Select for Noise Canceler Circuit
Clock
Divides the frequency of the sampling clock for CIR
reception selected by BRR.
00: Not divided
01: Divided by 2
10: Divided by 4
11: Divided by 8
10 ⎯ 0 R/W Reserved
The initial value should not be changed.
9 to 0 HHMAX9 to
HHMAX0
All 0 R/W Specifies the maximum high-level period for a
header or repeat header and the maximum low-level
period for a stop.