Datasheet

Section 17 Serial Communication Interface with FIFO (SCIF)
Rev. 2.00 Sep. 28, 2009 Page 524 of 994
REJ09B0452-0200
(6) Suspension of Data Reception
Figure 17.11 shows an example of the data reception suspension flowchart.
Clear RTS bit in FMCR to 0
Receive FIFO trigger level interrupt
Read receive FIFO
Read FLSR
Set RTS bit in FMCR to 1
(Transmission/reception standby flow)
DR = 0
No
Yes
[1]
[2]
[3]
[4]
[1] When data is received at a trigger level higher than
the receive FIFO trigger level specified in the
initialization flow, a receive FIFO trigger level interrupt
occurs.
[2] Clear the RTS bit in FMCR to 0.
[3] Read the receive FIFO until the DR flag is cleared to 0.
[4] Set the RTS bit in FMCR to 1, and then go to the
transmission/reception standby flow.
Figure 17.11 Example of Data Reception Suspension Flowchart