Datasheet

Section 17 Serial Communication Interface with FIFO (SCIF)
Rev. 2.00 Sep. 28, 2009 Page 525 of 994
REJ09B0452-0200
17.4.5 Data Transmission/Reception Through the LPC Interface
As shown in table 17.3, setting the SCIFE bit in HICR5 to 1 allows registers (except SCIFCR) to
be accessed from the LPC interface. The initial setting of SCIFCR by the CPU and setting of the
SCIFE bit in HICR5 to 1 enable the flow settings for initialization and data transmission/reception
shown in figures 17.3 to 17.5 to be made from the LPC interface. Table 17.7 shows the
correspondence between LPC interface I/O address and access to the SCIF registers. For details of
the LPC interface settings, see section 20, LPC interface (LPC).
Table 17.7 Correspondence Between LPC Interface I/O Address and the SCIF Registers
LPC Interface I/O Address
Bits 15 to 3 Bit 2 Bit 1 Bit 0 R/W Condition
SCIF
Register
R FLCR[7] = 0 FRBR
W FLCR[7] = 0 FTHR
SCIFADR (bits 15 to 3) 0 0 0
R/W FLCR[7] = 1 FDLL
R/W FLCR[7] = 0 FIER SCIFADR (bits 15 to 3) 0 0 1
R/W FLCR[7] = 1 FDLH
R ⎯ FIIR SCIFADR (bits 15 to 3) 0 1 0
W ⎯ FFCR
SCIFADR (bits 15 to 3) 0 1 1 R/W ⎯ FLCR
SCIFADR (bits 15 to 3) 1 0 0 R/W ⎯ FMCR
SCIFADR (bits 15 to 3) 1 0 1 R ⎯ FLSR
SCIFADR (bits 15 to 3) 1 1 0 R ⎯ FMSR
SCIFADR (bits 15 to 3) 1 1 1 R/W ⎯ FSCR