Datasheet

Section 18 I
2
C Bus Interface (IIC)
Rev. 2.00 Sep. 28, 2009 Page 576 of 994
REJ09B0452-0200
6. Clear the IRIC flag to 0.
7. To end transmission, clear the ACKE bit in ICCR to 0, to clear the acknowledge bit stored in
the ACKB bit to 0.
8. Clear the TRS bit to 0 for the next address reception, to set slave receive mode.
9. Dummy-read ICDR to release SCL on the slave side.
10. When the stop condition is detected, that is, when SDA is changed from low to high when SCL
is high, the BBSY flag in ICCR is cleared to 0 and the STOP flag in ICSR is set to 1. When the
STOPIM bit in ICXR is 0, the IRIC flag is set to 1. If the IRIC flag has been set, it is cleared to
0.
SDA
(master output)
SDA
(slave output)
21 21436587998
Bit 7 Bit 6 Bit 5 Bit 7 Bit 6Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
ICDRE
ICDR
IRIC
SCL
(master output)
Slave receive mode
Slave transmit mode
[3] ICDR write
User processing
Data 1
Data 1
Data 2
Data 2
A
R/W
A
[4]
[3] IRIC clear
[3] IRIC clear
[5] IRIC clear
[5] ICDR write
[2]
Figure 18.17 Example of Slave Transmit Mode Operation Timing
(MLS = 0)