Datasheet

Section 18 I
2
C Bus Interface (IIC)
Rev. 2.00 Sep. 28, 2009 Page 577 of 994
REJ09B0452-0200
18.4.7 IRIC Setting Timing and SCL Control
The interrupt request flag (IRIC) is set at different times depending on the WAIT bit in ICMR, the
FS bit in SAR, and the FSX bit in SARX. If the ICDRE or ICDRF flag is set to 1, SCL is
automatically held low after one frame has been transferred in synchronization with the internal
clock. Figures 18.18 to 18.20 show the IRIC set timing and SCL control.
SCL
SDA
IRIC
User processing
Clear IRIC
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When WAIT = 0, and FS = 0 or FSX = 0 (I
2
C bus format, no wait)
(a) Data transfer ends with ICDRE = 0 at transmission, or ICDRF = 0 at reception.
(b) Data transfer ends with ICDRE = 1 at transmission, or ICDRF = 1 at reception.
SCL
SDA
IRIC
User processing
Clear IRIC
Clear IRICWrite to ICDR (transmit)
or read from ICDR (receive)
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7
1987
Figure 18.18 IRIC Setting Timing and SCL Control (1)