Datasheet

Section 19 Keyboard Buffer Control Unit (PS2)
Rev. 2.00 Sep. 28, 2009 Page 606 of 994
REJ09B0452-0200
19.4.6 KBF Setting Timing and KCLK Control
Figure 19.11 shows the KBF setting timing and the KCLK pin states.
φ*
Note: * φ here indicates the clock signal frequency-divided by N for medium-speed mode.
KCLK
(pin)
Internal
KCLK
Falling edge
signal
RXCR3 to
RXCR0
KCLK
(output)
KBF
11th fall
Automatic I/O inhibit
B'0000B'1010
Figure 19.11 KBF Setting and KCLK Automatic I/O Inhibit Generation Timing