Datasheet

Section 20 LPC Interface (LPC)
Rev. 2.00 Sep. 28, 2009 Page 616 of 994
REJ09B0452-0200
Figure 20.1 shows a block diagram of the LPC.
IDR4
IDR3
IDR2
IDR1
LADR1H/L
LADR2H/L
LADR3H/L
LADR4H/L
SCIFADRH/L
TWR0MW
ODR4
ODR2
ODR3
ODR1
STR3
STR4
STR2
STR1
TWR0SW
SERIRQ
CLKRUN
LSCI
LSMI
PME
LPCPD
LRESET
LCLK
LFRAME
OBEI
IBFI4
IBFI1
IBFI2
IBFI3
ERRI
GA20
SIRQCR0 to 4
HISEL
LSCIE
LSCIB
LSCI input
LSMIE
LSMIB
LSMI input
PMEE
PMEB
PME input
Module data bus
Cycle detection
Serial → parallel conversion
Serial ← parallel conversion
Address match
SYNC output
Parallel → serial conversion
Control logic
Internal interrupt
control
[Legend]
HICR0 to HICR5:
LADR1H/L to 4H/L:
SCIFADRH/L:
IDR1 to IDR4:
ODR1 to ODR4:
TWR1 to
TWR15
TWR1 to
TWR15
LAD0 to
LAD3
HICR0 to HICR5
Host interface control registers 0 to 5
LPC channel 1 to 4 address registers
H and L
SCIF address register H and L
Input data registers 1 to 4
Output data registers 1 to 4
STR1 to STR4:
TWR0MW:
TWR0SW:
TWR1 to TWR15:
SIRQCR0 to SIRQCR4:
HISEL:
Status registers 1 to 4
Bidirectional data register 0MW
Bidirectional data register 0SW
Bidirectional data registers 1 to 15
SERIRQ control registers 0 to 4
Host interface select register
Figure 20.1 Block Diagram of LPC