Datasheet

Section 20 LPC Interface (LPC)
Rev. 2.00 Sep. 28, 2009 Page 623 of 994
REJ09B0452-0200
• HICR1
R/W
Bit Bit Name
Initial
Value Slave Host Description
7 LPCBSY 0 R ⎯ LPC Busy
Indicates that the LPC interface is processing a transfer
cycle.
0: LPC interface is in transfer cycle wait state
• Bus idle, or transfer cycle not subject to processing is
in progress
• Cycle type or address indeterminate during transfer
cycle
[Clearing conditions]
• LPC hardware reset or LPC software reset
• LPC hardware shutdown or LPC software shutdown
• Forced termination (abort) of transfer cycle subject to
processing
• Normal termination of transfer cycle subject to
processing
1: LPC interface is performing transfer cycle processing
[Setting condition]
Match of cycle type and address
6 CLKREQ 0 R ⎯ LCLK Request
Indicates that the LPC interface's SERIRQ output is
requesting a restart of LCLK.
0: No LCLK restart request
[Clearing conditions]
• LPC hardware reset or LPC software reset
• LPC hardware shutdown or LPC software shutdown
• There are no further interrupts for transfer to the host
in quiet mode in which SERIRQ is set to continuous
mode
1: LCLK restart request issued
[Setting condition]
In quiet mode, SERIRQ interrupt output becomes
necessary while LCLK is stopped