Datasheet

Section 20 LPC Interface (LPC)

Rev. 2.00 Sep. 28, 2009 Page 677 of 994

REJ09B0452-0200

Table 20.11 HIRQ Setting and Clearing Conditions when SCIF Channels are Used

Host Interrupt Setting Condition Clearing Condition

HIRQi

(i = 1 to 15)

Internal CPU sets the corresponding

SERIRQ host interrupt request for the

SCIF in SIRQCR4 (for details, see the

description of SIRQCR4).

Changes in the SCIF input signal DCD are

detected.

Reads FMSR and clears the DDCD

bit in FMSR

Slave CPU Master CPU

ODR1 write

Write 1 to IRQ1E1

OBF1 = 0?

Yes

All bytes

transferred?

SERIRQ IRQ1 output

SERIRQ IRQ1

source clear

Interrupt initiation

ODR1 read

Hardware operation

Software operation

Figure 20.8 HIRQ Flowchart (Example of Channel 1)