Datasheet

Section 21 FSI Interface
Rev. 2.00 Sep. 28, 2009 Page 687 of 994
REJ09B0452-0200
R/W
Bit Bit Name
Initial
Value
EC Host Description
3
2
CPHS
CPOS
0
0
R/W
R/W
⎯
⎯
CPHS: Selects the polarity of the FSICK clock.
CPOS: Selects the phase of the FSICK clock.
CPHS CPOS
0 0 Initial value of FSICK: Low level
Data changes at the FSICK
falling edge.
1 1 Initial value of FSICK: High level
Data changes at the FSICK
falling edge.
0 1 Setting prohibited
1 0 Setting prohibited
1 ⎯ 0 R/W ⎯ Reserved
The initial value should not be modified.
0 CKSEL 0 R/W ⎯ Clock select
0: Selects the system clock for FSICK
1: Selects LCLK for FSICK
Note: Before selecting LCLK for FSICK, clear the
CPHS and CPOS bits of FSICR1 to 0.