Datasheet

Section 21 FSI Interface
Rev. 2.00 Sep. 28, 2009 Page 690 of 994
REJ09B0452-0200
R/W
Bit Bit Name
Initial
Value
EC Host Description
2 to 0 RBN2
RBN1
RBN0
0
0
0
R/W ⎯ Receive Byte Count 2-0
These bits specify the number of data bytes to be
received. After the FSI reception operation ends
(when FSIRXI in FSISTR is 1), the RBN value is
decremented (−1) each time FSIRDR is read. When
all the data bytes have been received, RBN is cleared
to B'000.
000: Receives no data
001: Receives one byte of data
010: Receives two bytes of data
011: Receives three bytes of data
100: Receives four bytes of data
101 to 111: Setting prohibited
If reception of five bytes or more is specified, FSIRDR
is overwritten.
21.3.4 FSI Instruction Register (FSIINS)
FSIINS sets an instruction to be sent to the SPI flash memory during command transfer. When
LFBUSY is 1, a write to this register by the EC (this LSI) is invalid. This register should not be set
in the processing other than FSICMDI and FSIWI interrupt processing.
R/W
Bit Bit Name
Initial
Value EC Host Description
7 to 0 bit 7 to bit 0 All 0 R/W ⎯ These bits store an instruction to be transmitted to the
SPI flash memory.