Datasheet

Section 21 FSI Interface
Rev. 2.00 Sep. 28, 2009 Page 693 of 994
REJ09B0452-0200
21.3.8 FSI Transmit Data Registers 0 to 7 (FSITDR0 to FSITDR7)
FSITDR stores a total of 8 bytes of transmit data. A total of 8 bytes of addresses, instructions, and
data items can be transferred continuously from FSITDR0 through FSITDR7 in this order to the
SPI flash memory. When LFBUSY is set to 1, a write to this register by the EC (this LSI) is
invalid. This register should not be set in the processing other than FSICMDI and FSIWI interrupt
processing.
R/W
Bit Bit Name
Initial
Value EC Host Description
7 to 0 bit 7 to bit 0 All 0 R/W ⎯ These bits store transmit data.
21.3.9 FSI Receive Data Register (FSIRDR)
FSIRDR stores a total of 4 bytes of receive data items continuously sent from the SPI flash
memory. This register should not be read in the processing other than FSICMDI interrupt
processing. Note that four bytes of receive registers share a single register address. A register to be
read will be determined according to the RBN bits in FSIBNR. When RBN = B'000, H'00 is read
out.
R/W
Bit Bit Name
Initial
Value EC Host Description
7 to 0 bit 7 to bit 0 All 0 R ⎯ These bits store receive data.