Datasheet

Section 21 FSI Interface
Rev. 2.00 Sep. 28, 2009 Page 700 of 994
REJ09B0452-0200
R/W
Bit Bit Name
Initial
Value
EC Host Description
4 FLDCT 0 R/W ⎯ FSI LPC Direct
Selects access mode in SPI flash memory write. For
details, see section 21.4.6, SPI Flash Memory Write
Operation Mode.
0: LPC-SPI indirect transfer
1: LPC-SPI direct transfer
3 FLWAIT 0 R/W ⎯ FSI LPC Wait
Selects access mode in SPI flash memory write. For
details, see section 21.4.6, SPI Flash Memory Write
Operation Mode.
0: No wait cycle is inserted.
1: Wait cycles can be inserted.
2 to 0 ⎯ All 0 R/W ⎯ Reserved
The initial value should not be modified.
21.3.18 FSI Address Registers H, M, and L (FSIARH, FSIARM, and FSIARL)
FSIAR stores an SPI flash memory address. If the host address matches FSIHBAR, the FSIAR
value is updated. FSIAR value is not updated by command access.
• FSIARH
R/W
Bit Bit Name
Initial
Value
EC Host Description
7 to 0 bit 23 to
bit 16
All 0 R ⎯ These bits store bits [23:16] of the SPI flash memory
address.
• FSIARM
R/W
Bit Bit Name
Initial
Value EC Host Description
7 to 0 bit 15 to
bit 8
All 0 R ⎯ These bits store bits [15:8] of the SPI flash memory
address.