Datasheet

Section 21 FSI Interface

Rev. 2.00 Sep. 28, 2009 Page 711 of 994

REJ09B0452-0200

LCLK

LFRAME

LAD[3:0]

CT ADDR DATA TAR WAIT SY TAR

FSIAR[23:0]

FSIWDR[31:0]

FSICR2 TE bit

FSITDR7 to

FSITDR0

FSISTR OBF bit

FSISS

FSICK (CPOS = CPHS =0)

FSIDO

H'06-4A-70

H'23

H'23-AF

H'AF->23

Figure 21.7 AAI-Program Instruction Execution Timing

(Second and Following Bytes)

(4) Read Instructions

If an LPC/FW memory read cycle occurs while the FRDE bit in FSICR1 is cleared to 0, the SPI

flash memory address is stored in FSIAR. Then, the SPI flash memory address and the instruction

which is stored in FSIRDINS in advance are transferred to FSITDR. After SYNC (long wait) has

been returned, the RE bit in FSICR2 is set, and Read instruction execution starts. The read data is

then received and stored in FSIRDR. When the reception has been completed, SYNC (Ready),

read data, and TAR are returned to the host. Figure 21.8 shows an example of data transfer to

FSIRDR. Figure 21.9 shows the Read instruction execution timing.