Datasheet

Section 21 FSI Interface
Rev. 2.00 Sep. 28, 2009 Page 713 of 994
REJ09B0452-0200
(5) Fast-Read Instruction
If an LPC/FW memory read cycle occurs while the FRDE bit in FSICR1 is set to 1, the host
address is stored in FSIAR. Then, the SPI flash memory address and the instruction which is
stored in FSIRDINS in advance are transferred to FSITDR. After SYNC (long wait) has been
returned, the RE bit in FSICR2 is set, and Fast-Read instruction execution starts. The read data is
then received and stored in FSIRDR. When the reception has been completed, SYNC (Ready),
read data, and TAR are returned to the host. Figure 21.10 shows the Fast-Read Instruction
Execution Timing.
LCLK
LFRAME
LAD[3:0] ST CT ADDR DATATA R W AI T S T TA R
φ
FSIAR[23:0]
FSIRDINS[7:0]
FSICR2 RE bit
FSITDR7 to
FSITDR0
FSISTR FSIRXI bit
FSISS
FSICK (CPOS = CPHS =0)
FSIDO
FSIDI
H'06-4A-70
H'70-4A-06-03
H'01-23-45-67
H'02->06->4A->70->Dummy
H'01->23->45->67
H'0B
FSIRDR3 to
FSIRDR0
Figure 21.10 Fast-Read Instruction Execution Timing