Datasheet

Section 21 FSI Interface
Rev. 2.00 Sep. 28, 2009 Page 719 of 994
REJ09B0452-0200
Written by the CPU
Written by the CPU
Written by the CPU H'4
Written by the CPU H'76-4A-06
Written by the CPU H'52
Cleared by the CPU
Cleared by the CPU
Cleared by the CPU
Cleared by the CPU
Cleared by the CPU
Cleared by the CPU
Automatically cleared
H'00 (Automatically cleared)
STEP1 STEP2 STEP3
H'EFFF_F000 H'EFFF_F000H'2325_4A76
H'06_4A76
H'52->76->4A-> 06
φ
FSIDMYE
FSICMDI
CMDBUSY
LPC_ADDR
FSIAR[23:0]
TE
TBN
FSITDR3 to
FSITDR1
FSIINS
OBF
FSITEI
FSISS
FSICK
FSIDO
Figure 21.16 Execution Timing of SPI Flash Memory
Step 1:
1. Write an erasure setting command (Host).
2. Generate an FSICMDI interrupt request.
3. Set the FSIDMYE bit in FSILSTR1 to 1 and clear the FSICMDI and CMDBUSY bits in
FSILSTR1 to 0.
4. Complete the interrupt processing.
5. Check that the FSIDMYE bit in FSILSTR1 is set to 1 and that the CMDBUSY and FSICMDI
bits in FSILSTR1 are cleared to 0 (Host).
Step 2:
1. Perform a dummy write to the sector or block address to be erased (Host).
2. Store the SPI flash memory address and write data in the FSIAR register and FSIWDR
register, respectively*.
Note: * Use the data stored in FSIWDR if necessary on the user side.
Step 3:
1. Write an erasure setting command (Host).
2. Generate an FSICMDI interrupt request.
3. Clear the FSICMDI bit in FSILSTR1 to 0.