Datasheet

Section 21 FSI Interface
Rev. 2.00 Sep. 28, 2009 Page 720 of 994
REJ09B0452-0200
4. Execute the SPI flash memory erasure instruction.
⎯ Set the TE bit in FSICR2 to 1.
⎯ Set the TBN bit in FSIBNR to 4-byte transfer.
⎯ Write the FSI address stored in FSIAR to FSITDR1 to FSITDR3.
⎯ Write the erasure instruction to FSIINS (start the SPI flash memory erasure instruction
execution).
5. Complete the interrupt processing.
6. Generate an FSITEI interrupt request.
7. Clear the FSIDMYE and CMDBUSY bits in FSILSTR1 to 0.
8. Complete the interrupt processing.
9. Check that the FSIDMYE, CMDBUSY, and FSICMDI bits in FSILSTR1 are cleared to 0
(Host).
(6) FSI Command Usage Example 2 (SPI Flash Memory Status Read)
Figure 21.17 shows an example of the execution timing of the SPI flash memory status read
instruction.
φ
FSIDMYE
FSICMDI
CMDBUSY
LPC_ADDR
RE
TBN
RBN
FSIINS
FSIRXI
FSISS
FSICK
FSIDO
FSIDI
Written by the CPU
Written by the CPU H'1
Written by the CPU H'1
Written by the CPU H'05
Cleared by the CPU
Cleared by the CPU
H'00 (Automatically cleared)
H'00 (Automatically cleared)
Automatically cleared
STEP1 STEP2 STEP3
H'05
H'07
H'EFFF_F000
Automatically cleared
Figure 21.17 Execution Timing of SPI Flash Memory Status Read Instruction
The SPI flash memory status read instruction is executed in the following sequence.